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`Case 4:20-cv-00991 Document 1-1 Filed 12/31/20 Page 1 of 14 PageID #: 69
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`EXHIBIT A
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`EXHIBIT A
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`

`

`USOO666.0651B1
`(10) Patent No.:
`US 6,660,651 B1
`(45) Date of Patent:
`Dec. 9, 2003
`
`6,258,220 B1,
`
`7/2001 Dordi et al. ................ 204/198
`
`(12) United States Patent
`Markle
`
`(54) ADJUSTABLE WAFER STAGE, ANDA
`METHOD AND SYSTEM FOR PERFORMING
`PROCESS OPERATIONS USING SAME
`
`(75) Inventor: Richard J. Markle, Austin, TX (US)
`(73) Assignee: Advanced Micro Devices, Inc., Austin,
`TX (US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 136 days.
`
`(*) Notice:
`
`cited by examiner
`Primary Examiner William A. Powell
`(74) Attorney, Agent, or Firm Williams, Morgan &
`AmerSon, P.C.
`ABSTRACT
`(57)
`A process tool comprised of an adjustable wafer stage and
`various methods and systems for performing process opera
`tions using same is disclosed herein. In one illustrative
`attent." PE r comprised ". proceSS
`chamber, and an adjustable wafer Stage in the process
`chamber to receive a wafer positioned thereabove, the wafer
`(21) Appl. No.: 10/010,463
`Stage having a Surface that is adapted to be raised, lowered
`(22) Filed:
`Nov. 8, 2001
`or tilted. In further embodiments, the process tool further
`7
`comprises at least three pneumatic cylinders or at least three
`(51) Int. Cl." ................................................ H01L 21/00
`rack and pinion combinations, each of which are operatively
`(52) U.S. Cl. ............. 438/729; 156/345.24; 156/345.51;
`coupled to the wafer Stage by a ball and Socket connection.
`438/9; 438/694
`(58) Field of Search ....................... 156/345.23, 345.51, A System disclosed herein is comprised of a metrology tool
`156/345.55, 345.24; 438/8, 9, 694-729;
`for measuring a plurality of waferS processed in a process
`216/67
`tool to determine acroSS-Wafer variations produced by the
`process tool, a process tool comprised of an adjustable wafer
`Stage that has a Surface adapted to receive a wafer to be
`processed in the tool, and a controller for adjusting a plane
`of the Surface of the wafer Stage based upon the determined
`acroSS-wafer variations produced by the tool, whereby the
`process tool processes at least one Subsequently processed
`wafer positioned on the wafer Stage after the plane of the
`Surface of the wafer Stage has been adjusted.
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,836.905 A * 6/1989 Davis et al. ........... 156/345.51
`5,076,877 A * 12/1991 Ueda et al. ............ 156/345.55
`5,928,732 A 7/1999 Law et al. .................. 427/579
`6,057.244. A 5/2000 Hausmann et al. ......... 438/706
`6,068,784. A 5/2000 Collins et al. ................ 216/68
`6,235,646 B1
`5/2001 Sharan et al. .....
`... 438/771
`6.251,792 B1
`6/2001 Collins et al. .............. 438/710
`
`86 Claims, 3 Drawing Sheets
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`76
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`74
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`METROLOGY TOOL
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`CONTROLLER
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`70
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`U.S. Patent
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`Dec. 9, 2003
`
`Sheet 1 of 3
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`US 6,660,651 B1
`
`FIG. 1
`(Prior Art)
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`76
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`74
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`METROLOGY TOOL
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`CONTROLLER
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`70
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`S PROCESS TOOL
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`FIG. 6
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`

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`U.S. Patent
`
`Dec. 9, 2003
`
`Sheet 2 of 3
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`US 6,660,651 B1
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`3
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`FIG. 2
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`54
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`U.S. Patent
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`Dec. 9, 2003
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`Sheet 3 of 3
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`US 6,660,651 B1
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`FIG. 4
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`US 6,660,651 B1
`
`1
`ADJUSTABLE WAFER STAGE, ANDA
`METHOD AND SYSTEM FOR PERFORMING
`PROCESS OPERATIONS USING SAME
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`This invention relates generally to Semiconductor fabri
`cation technology, and, more particularly, to an adjustable
`wafer Stage, and a method and System for performing
`proceSS operations using Same.
`2. Description of the Related Art
`There is a constant drive within the Semiconductor indus
`try to increase the operating Speed of integrated circuit
`15
`devices, e.g., microprocessors, memory devices, and the
`like. This drive is fueled by consumer demands for com
`puters and electronic devices that operate at increasingly
`greater Speeds. This demand for increased Speed has resulted
`in a continual reduction in the size of Semiconductor
`devices, e.g., transistors. That is, many components of a
`typical field effect transistor (FET), e.g., channel length,
`junction depths, gate insulation thickness, and the like, are
`reduced. For example, all other things being equal, the
`Smaller the channel length of the transistor, the faster the
`transistor will operate. Thus, there is a constant drive to
`reduce the size, or Scale, of the components of a typical
`transistor to increase the overall Speed of the transistor, as
`well as integrated circuit devices incorporating Such tran
`Sistors.
`By way of background, an illustrative field effect transis
`tor 10, as shown in FIG. 1, may be formed above a surface
`15 of a semiconducting substrate or wafer 11 comprised of
`doped-silicon. The Substrate 11 may be doped with either
`N-type or P-type dopant materials. The transistor 10 may
`have a doped polycrystalline silicon (polysilicon) gate elec
`trode 14 formed above a gate insulation layer 16. The gate
`electrode 14 and the gate insulation layer 16 may be sepa
`rated from doped source/drain regions 22 of the transistor 10
`by a dielectric Sidewall spacer 20. The Source/drain regions
`22 of the transistor 10 may be formed by performing one or
`more ion implantation processes to introduce dopant atoms,
`e.g., arsenic or phosphorous for NMOS devices, boron for
`PMOS devices, into the Substrate 11. Shallow trench isola
`tion regions 18 may be provided to isolate the transistor 10
`electrically from neighboring Semiconductor devices, Such
`as other transistors (not shown).
`In the process of forming integrated circuit devices,
`millions of transistors, such as the illustrative transistor 10
`depicted in FIG. 1, are formed above a Semiconducting
`Substrate. In general, Semiconductor manufacturing opera
`tions involve, among other things, the formation of layers of
`various materials, e.g., polysilicon, insulating materials,
`metals, etc., and the Selective removal of portions of those
`layers by performing known photolithographic and etching
`techniques. These processes, along with various ion implant
`and heating processes, are continued until Such time as the
`integrated circuit device is complete. Additionally, although
`not depicted in FIG. 1, a typical integrated circuit device is
`comprised of a plurality of conductive interconnections,
`Such as conductive lines and conductive contacts or Vias,
`positioned in multiple layers of insulating material formed
`above the Substrate. These conductive interconnections
`allow electrical Signals to propagate between the transistors
`formed above the Substrate.
`During the course of fabricating Such integrated circuit
`devices, a variety of features, e.g., gate electrodes, conduc
`
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`2
`tive lines, openings in layers of insulating material, etc., are
`formed to very precisely controlled dimensions. Such
`dimensions are Sometimes referred to as the critical dimen
`sion (CD) of the feature. It is very important in modern
`Semiconductor processing that features be formed with a
`high degree of accuracy due to the reduced size of those
`features in Such modern devices. For example, gate elec
`trodes may now be patterned to a width 12 that is approxi
`mately 0.18 um (1800 A), and further reductions are planned
`in the future. The width 12 of the gate electrode 14 corre
`sponds approximately to the channel length 13 of the
`transistor 10 when it is operational. Of course, the critical
`dimension 12 of the gate electrode 14 is but one example of
`a feature that must be formed very accurately in modern
`Semiconductor manufacturing operations. Other examples
`include, but are not limited to, conductive lines, openings in
`insulating layers to allow Subsequent formation of a con
`ductive interconnection, i.e., a conductive line or contact,
`therein, etc. Thus, even slight variations in the actual dimen
`Sion of the feature as fabricated may adversely affect device
`performance. Thus, there is a great desire for a method that
`may be used to accurately, reliably and repeatedly form
`features to their desired critical dimension, e.g., to form the
`gate electrode 14 to its desired critical dimension 12.
`In manufacturing Semiconductor devices, many deposi
`tion processes and etching processes may be performed. For
`example, a variety of process layers, e.g., layers of
`polysilicon, metal or insulating materials, may be formed by
`performing a variety of deposition processes, e.g., chemical
`vapor deposition (“CVD), plasma enhanced chemical
`vapor deposition (“PECVD"), physical vapor deposition
`(“PVD”), etc. Additionally, a variety of etching processes,
`Such as a dry plasma etching process, may be performed to
`pattern an underlying process layer.
`Unfortunately, many processes used in manufacturing
`integrated circuit devices, Such as deposition and etch
`processes, tend to exhibit acroSS-wafer variations. For
`example, a deposition proceSS may tend to produce process
`layers that are thicker near an edge region of the wafer than
`near a center region of the wafer, and Vice versa. Moreover,
`this variation may not be uniform around the circumference
`of the wafer, i.e., the thickness variation may occur in only
`one quadrant of the wafer. Similarly, etching processes may
`exhibit acroSS-wafer non-uniformity characteristics. For
`example, the etching rate may be greater near a center region
`of the wafer than it is near an edge region of the wafer.
`Moreover, as with deposition processes, these variations
`may not be uniform around the circumference of the wafer,
`i.e., they may occur in localized areas.
`Such variations are problematic in modem integrated
`circuit manufacturing. Such variations, even if Small in
`absolute magnitude, may adversely impact the ability to
`form features on integrated circuits with the precision
`required for modem integrated circuit devices. Additionally,
`Such proceSS Variations may require adjustments to Subse
`quent processing operations in an attempt to compensate for
`the acroSS-wafer variations. For example, a deposition pro
`ceSS may result in a process layer that is thicker at the edge
`of the wafer than it is at the center of the wafer, i.e., the
`process layer may have a Surface profile that is approxi
`mately concave. In that situation, a Subsequent chemical
`mechanical polishing (“CMP") process may be performed in
`which parameters of the CMP process are adjusted in an
`effort to increase the polishing performed near the edge
`region of the wafer. Accordingly, Such acroSS-wafer varia
`tions resulting from certain processing operations are unde
`sirable.
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`3
`The present invention is directed to overcoming, or at
`least reducing the effects of, one or more of the problems
`described above.
`
`US 6,660,651 B1
`
`SUMMARY OF THE INVENTION
`The present invention is generally directed to a proceSS
`tool comprised of an adjustable wafer Stage, and various
`methods and Systems for performing proceSS operations
`using Same. In one illustrative embodiment, the process tool
`is comprised of a process chamber, and an adjustable wafer
`Stage positioned in the process chamber to receive a wafer
`positioned thereabove, the wafer Stage having a Surface that
`is adapted to be raised, lowered or tilted. In further
`embodiments, the process tool may be comprised of a
`plurality of pneumatic cylinders or rack and pinion combi
`nations that are operatively coupled to the wafer Stage. The
`cylinders and rack and pinion combinations may be used to
`move or adjust the wafer Stage. In even further
`embodiments, the process tool may further comprise at least
`three pneumatic cylinders or at least three rack and pinion
`combinations, each of which are operatively coupled to the
`wafer Stage by a ball and Socket connection.
`One illustrative method disclosed herein comprises pro
`Viding a process chamber comprised of a wafer Stage, the
`wafer Stage having a Surface that is adjustable, adjusting the
`Surface of the wafer Stage by performing at least one of
`raising, lowering and varying a tilt of the Surface of the
`wafer Stage, positioning a wafer on the wafer Stage, and
`performing a process operation on the wafer positioned on
`the wafer stage. In further embodiments, the method further
`comprises adjusting the Surface of the wafer Stage by
`actuating at least one of a plurality of pneumatic cylinders
`that are operatively coupled to the wafer Stage, or by
`actuating at least one of a plurality of rack and pinion
`combinations that are operatively coupled to the wafer Stage.
`Another illustrative method of the present invention com
`prises performing a process operation in a process tool on
`each of a plurality of wafers, measuring a plurality of the
`processed wafers to determine acroSS-wafer variations pro
`duced by the proceSS operation performed in the proceSS
`tool, adjusting, based upon the measured acroSS-wafer
`variations, a plane of a Surface of an adjustable wafer Stage,
`and performing the process operation on at least one Sub
`Sequently processed wafer positioned on the wafer Stage in
`the proceSS chamber after the plane of the wafer Stage has
`been adjusted. In further embodiments, the method further
`comprises measuring a plurality of the processed wafers to
`determine acroSS-wafer variations in a thickneSS or in feature
`sizes produced by the proceSS operation. The method may
`further comprise performing at least one of raising, lowering
`and tilting, based upon the measured across-wafer
`variations, the plane of the Surface of the adjustable wafer
`Stage.
`The present invention is also directed to a System that may
`be used to perform the methods described herein. In one
`embodiment, the System is comprised of a metrology tool for
`measuring a plurality of wafers processed in a process tool
`to determine acroSS-wafer variations produced by the pro
`ceSS tool, a process tool comprised of an adjustable wafer
`Stage that has a Surface adapted to receive a wafer to be
`processed in the tool, and a controller for adjusting a plane
`of the Surface of the wafer Stage based upon the determined
`acroSS-wafer variations produced by the tool, whereby the
`process tool processes at least one Subsequently processed
`wafer positioned on the wafer Stage after the plane of the
`Surface of the wafer Stage has been adjusted.
`
`4
`BRIEF DESCRIPTION OF THE DRAWINGS
`The invention may be understood by reference to the
`following description taken in conjunction with the accom
`panying drawings, in which like reference numerals identify
`like elements, and in which:
`FIG. 1 is a cross-sectional view of an illustrative prior art
`transistor;
`FIG. 2 is a cross-sectional view depicting an illustrative
`wafer Stage having an adjustable Surface;
`FIG. 3 is a bottom view of the illustrative wafer stage
`depicted in FIG. 2;
`FIGS. 4 and 5 are views of one illustrative rack and pinion
`assembly that may be employed with the present invention;
`and
`FIG. 6 depicts an illustrative embodiment of a system in
`accordance with one embodiment of the present invention.
`While the invention is susceptible to various modifica
`tions and alternative forms, specific embodiments thereof
`have been shown by way of example in the drawings and are
`herein described in detail. It should be understood, however,
`that the description herein of Specific embodiments is not
`intended to limit the invention to the particular forms
`disclosed, but on the contrary, the intention is to cover all
`modifications, equivalents, and alternatives falling within
`the Spirit and Scope of the invention as defined by the
`appended claims.
`DETAILED DESCRIPTION OF THE
`INVENTION
`Illustrative embodiments of the invention are described
`below. In the interest of clarity, not all features of an actual
`implementation are described in this specification. It will of
`course be appreciated that in the development of any Such
`actual embodiment, numerous implementation-Specific
`decisions must be made to achieve the developerS Specific
`goals, Such as compliance with System-related and busineSS
`related constraints, which will vary from one implementa
`tion to another. Moreover, it will be appreciated that Such a
`development effort might be complex and time-consuming,
`but would nevertheless be a routine undertaking for those of
`ordinary skill in the art having the benefit of this disclosure.
`The present invention will now be described with refer
`ence to the attached figures. Although the various regions
`and Structures of a Semiconductor device are depicted in the
`drawings as having very precise, Sharp configurations and
`profiles, those skilled in the art recognize that, in reality,
`these regions and Structures are not as precise as indicated in
`the drawings. Additionally, the relative sizes of the various
`features and Structures depicted in the drawings may be
`exaggerated or reduced as compared to the Size of those
`features or structures on real-word Systems. Moreover, for
`purposes of clarity, the illustrative System depicted herein
`does not include all of the Supporting utilities and devices of
`Such a System. Nevertheless, the attached drawings are
`included to describe and explain illustrative examples of the
`present invention.
`In general, the present invention is directed to a process
`tool comprised of an adjustable wafer Stage, and various
`methods and Systems for performing proceSS operations
`using Same. AS will be readily apparent to those skilled in the
`art upon a complete reading of the present application, the
`present method is applicable to a variety of technologies,
`e.g., NMOS, PMOS, CMOS, etc., and it is readily applicable
`to a variety of devices, including, but not limited to, logic
`devices, memory devices, etc. Moreover, the present inven
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`S
`tion may be employed with a variety of processes performed
`in Semiconductor manufacturing.
`AS Stated previously, in manufacturing integrated circuit
`devices, many deposition and etching processes, e.g., CVD,
`PECVD and PVD deposition processes, chemical etching
`processes, Sputter etching processes, reactive ion etching
`processes, etc., may be performed. The processing tools for
`performing Such processes, i.e., deposition tools and etch
`tools, may have various physical configurations that depend
`upon a variety of factors, e.g., the manufacturer, the type of
`process to be performed, etc. U.S. Pat. Nos. 6,068,784 and
`6,251,792 B 1 depict illustrative processing tools that may be
`used in modern Semiconductor manufacturing. Both of these
`patents are hereby incorporated by reference in their entirety.
`However, many, if not all, of Such tools have a proceSS
`chamber, where processing operations will be performed,
`and a wafer Stage or chuck in the process chamber that is
`adapted to hold a wafer in position during processing,
`typically through use of vacuum pressure or one or more
`clamps. In many tools, the wafer Stage is actually an
`electrode that is used to ground the wafer while a plasma is
`created above the wafer by other electrodes or coils in Such
`tools. The present invention is generally directed to a wafer
`Stage having an adjustable Surface or plane, Such that the
`plane of the wafer Stage may be raised, lowered or tilted. By
`adjusting the plane of the wafer Stage, the present invention
`may be useful in reducing or overcoming Some of the
`problems described in the background Section of this appli
`cation.
`An illustrative wafer Stage 40 in accordance with one
`embodiment of the present invention will now be described
`with reference to FIGS. 2-3. As shown therein, the wafer
`stage 40 has a top surface 42 and a bottom surface 43. In
`operation, a wafer (not shown) may be positioned on the top
`Surface 42 of the wafer Stage 40 and processing operations
`may then be performed on the wafer. The wafer may be
`Secured to the stage by a plurality of clamps (not shown)
`and/or a vacuum chuck (not shown). Given the moveable
`nature of the wafer stage 40 of the present invention, the
`utilities for actuating the clamps and/or providing a vacuum
`may have to be flexibly coupled to the wafer stage 40 via
`flexible hoses and the like. The particular arrangements of
`Such connections are well within the knowledge of those
`skilled in the art. Accordingly, they will not be described in
`any detail.
`The top surface 42 of the wafer stage 40 defines a plane
`44 that, as described more fully below, may be raised,
`lowered or tilted at an angle 45 as desired. The magnitude by
`which the surface 42 may be raised, lowered or tilted may
`vary depending upon the particular application. In one
`embodiment, the surface 42 of the wafer stage 40 may be
`raised or lowered approximately 0.25-3.0 inches, and the
`plane 44 of the surface 42 of the wafer stage 40 may vary
`from approximately 0–25 degrees relative to a horizontal
`surface. Moreover, as will be recognized by those skilled in
`the art after a complete reading of the present application the
`Surface 42 may be adjusted dynamically during a proceSS
`operation, or it may be adjusted only a single time prior to
`performing a proceSS operation on a wafer positioned
`thereon. Additionally, the Surface 42 may be adjusted based
`upon metrology data obtained for wafers to be processed in
`a process tool (i.e., a feed-forward mode), or based upon
`metrology data obtained for wafers that have previously
`been processed in the process tool (i.e., a feed-back mode).
`A mechanism useful in adjusting the position of the wafer
`Stage 40 may be comprised of any of a variety of devices,
`Such as pneumatic, hydraulic, electromagnetic or mechani
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`US 6,660,651 B1
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`6
`cal Systems. In the disclosed embodiment, each of three
`pneumatic cylinders 46 (only one of which is shown in FIG.
`2) are operatively coupled to the bottom surface 43 of the
`wafer stage 40 via a ball and socket connection 48. As shown
`in FIG. 3, a bottom view taken along the line “3-3” in FIG.
`2, the pneumatic cylinderS 46 are Spaced apart approxi
`mately 120 degrees under the wafer stage 40. Also depicted
`in FIG. 2 is an illustrative manifold 60 and a valve 61 that
`will be used in actuating the pneumatic cylinder 46 to
`control the position of the surface 42 of the wafer stage 40.
`Only one valve 61 is depicted in FIG. 2. However, each
`cylinder 46 may have its own valve 61 such that each of the
`cylinders 46 may be independently controlled.
`The pneumatic cylinderS 46 may be any type of pneu
`matic cylinders useful for performing the function of adjust
`ing the surface 42 of the wafer stage 40. For example, the
`pneumatic cylinderS 46 may be dual-acting pneumatic cyl
`inders. The Stroke, Size and Supply pressure to Such cylinders
`may vary depending upon the particular application. Air or
`an inert gas may be Supplied to the cylinderS 46 at the
`required pressure through flexible hoses (not shown).
`The illustrative pneumatic cylinder 46 depicted in FIG. 2
`is comprised of a housing 47, a shaft 49 and a ball 51
`coupled to the shaft 49. The ball 51 of the cylinder 46 is
`operatively coupled to a housing 50 in a ball and Socket
`arrangement 48. The housing 50 is comprised of three
`sections 50A, 50B and 50C. In the disclosed embodiments,
`the section 50C is secured to the bottom Surface 43 of the
`wafer stage 40, and the sections 50A, 50B are secured to the
`section 50C by a plurality of screws 59. See FIG. 3. Of
`course, the ball and Socket connection 48 may be achieved
`by a variety of different structures known to those skilled in
`the art. Moreover, the present inventions may be employed
`in Situations where the pneumatic cylinderS 46 may be
`coupled to the wafer Stage 40 by another type of connection,
`e.g., a pinned connection. Thus, the particular details of the
`manner in which the cylinderS 46 are operatively coupled to
`the wafer stage 40 should not be considered limitations of
`the present invention unless Such details are specifically Set
`forth in the appended claims.
`Also depicted in FIG. 3 are a plurality of guides 54 that
`may or may not be employed in every situation. For clarity,
`guides 54 are not depicted in FIG. 2. In the depicted
`embodiment of FIG. 3, the guides 54 are comprised of a tab
`56 and a guide structure 55. The tab 56 is fixedly coupled to
`the wafer stage 40, and the guide structure 55 is fixedly
`coupled to the process chamber, or other similar fixed
`Structure of a process tool. The guides 54 are provided to
`prevent or limit rotation of the wafer stage 40 in the
`directions indicated by arrow 57. Any number of such guides
`54 may be provided. In the depicted embodiment, two such
`guides 54 are positioned approximately 180 degrees apart.
`Of course, the guides 54 must be sized so as to allow for the
`maximum tilt anticipated for the wafer Stage 40.
`In one embodiment, an end 53 of the cylinder 46 is fixed
`to a portion 39 of the process chamber, or other fixed
`structure. In other embodiments, the end 53 of the cylinder
`46 may be connected to the proceSS chamber by a pinned or
`ball and Socket arrangement, although those Situations are
`not depicted in FIG. 2. It should be understood that the
`portion 39 of the process chamber is intended to be repre
`sentative in nature. That is, the portion 39 may be any
`portion of a proceSS chamber or other Structure that is
`Stationary and provides an adequate foundation for anchor
`ing the end 53 of the cylinder 46.
`Of course, Structures other than the pneumatic cylinders
`46 depicted in FIG.2 may be employed for raising, lowering
`
`

`

`7
`or tilting the surface 42 of the wafer stage 40. For example,
`as shown in FIGS. 4 and 5, in place of each of the pneumatic
`cylinderS 46, a rack and pinion assembly arrangement 80
`may be provided. In one illustrative embodiment, the rack
`and pinion assembly 80 is comprised of a rack 82, a pinion
`86, a guide 84 and an electric motor 88 having a motor
`support 90. Ashaft 81 and ball 83 are coupled to the rack 82.
`The rack 82 is adapted to slide with the guide 84 when the
`motor 88 is actuated. The rack 82 and the motor support 90
`may be fixedly coupled to any portion of the process
`chamber Sufficient to provide the necessary anchoring Sup
`port for these structures. The electric motor 88 may be any
`type of electric motor, Such as a stepper motor. By actuation
`of the electric motor 88, the rack 82 may be raised or
`lowered, thereby raising, lowering or adjusting the angle 45
`of the surface 42 of the wafer stage 40.
`An illustrative system 70 that may be used in one embodi
`ment of the present invention is shown in FIG. 4. In one
`embodiment, the system 70 is comprised of a process tool 72
`and a controller 74. In other embodiments, the system
`further comprises a metrology tool 76. In general, a wafer 28
`is provided to the process tool 72 where a proceSS operation
`will be performed on the wafer 28. The controller 74 may be
`used to raise, lower or adjust the tilt of the surface 42 of the
`wafer stage 40. The controller 74 may use feed-forward or
`feed-back metrology data to raise, lower or tilt the Surface 42
`of the wafer stage 40.
`The process tool 72 may be any type of processing tool
`commonly found in Semiconductor manufacturing opera
`tions. For example, the process tool 72 may be a deposition
`tool adapted to perform at least one of a CVD, PECVD or
`PVD process. AS another example, the process tool may be
`an etching tool, Such as a plasma etching tool, a Sputter etch
`tool, a reactive ion etching tool, etc.
`If used, the metrology tool 76 may be any type of tool
`useful for determining acroSS-wafer variations resulting
`from the process tool 72. For example, the metrology tool 76
`may be an ellipsometer or a profilometer useful for deter
`mining acroSS-wafer thickness variations in a deposited
`proceSS layer. Alternatively, the metrology tool 76 may be a
`Scanning electron microscope or a Scatterometer useful for
`inspecting features formed by an etching process to detect
`for areas of the wafer 28 where the etching process may be
`too aggressive, i.e., where features are formed with critical
`dimensions that are Smaller than anticipated, or features that
`exhibit undercutting. Such a metrology tool 76 may also be
`useful in determining where etching has been less than
`complete.
`In one embodiment, the measurements taken by the
`metrology tool 76 may be performed on any desired number
`of wafers before or after the wafers have been processed in
`the process tool 72. For example, Such measurements may
`be performed on all wafers in one or more lots, or on a
`representative number of wafers in a given lot, and these
`results may then be used to control or adjust the relative
`position of the surface 42 of the wafer stage 40 in the process
`tool 72 on Subsequently processed wafers. Additionally,
`more than one lot of waferS may be analyzed until Such time
`as the proceSS engineer has achieved a Sufficiently high
`degree of confidence that the metrology accurately reflects
`the acroSS-wafer characteristics of a process tool 76 or of a
`particular process flow.
`The number of and location of the measurements taken by
`the metrology tool 76 on any particular wafer may be varied
`as a matter of design choice. The more measurements taken,
`the higher degree of likelihood that the measurements actu
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
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`Case 4:20-cv-00991 Document 1-1 Filed 12/31/20 Page 9 of 14 PageID #: 77
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`US 6,660,651 B1
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`8
`ally reflect real-world conditions. However, the responsible
`process engineer may decide on an appropriate number of
`measurements to be taken, as well as the location of those
`measurements consistent with the degree of confidence
`desired by the proceSS engineer with respect to the particular
`application under consideration.
`Control equations may be employed to raise, lower or
`adjust the angle of the surface 42 of the wafer stage 40 in
`situations where the methods described herein indicate that
`Such an adjustment is warranted, e.g., when acroSS-wafer
`variations in thickness and/or feature sizes are present. That
`is, the metrology data may be used in either a feed-forward
`or feedback manner to control the adjustment of the Surface
`42 of the wafer stage 40. The control equations may be
`developed empirically using commonly known linear or
`non-linear techniques. The controller 74 may automatically
`control the plane 44 of the surface 42 of the wafer stage 40.
`Through use of the present invention, the extent and mag
`nitude of acroSS-wafer variations performed by various
`process tools 72 may be reduced. That is, by effectively
`repositioning all, or a portion, of the Surface 42, the varia
`tions resulting from a process may be reduced or eliminated.
`For example, if a particular area or region of a process layer
`is formed too thick, the surface 42 may be tilted so as to
`position the affected portion further away from, for example,
`a target in a PVD system, thereby reducing the thickness of
`the proceSS layer in that localized area.
`The controller 74 may be used to monitor and control the
`positioning of the surface 42 of the wafer stage 40 within a
`process chamber. Such positioning may be relative to any
`reference point or plane. For example, with respect to a PVD
`System, the positioning of the Surface 42 of the wafer Stage
`40 may be made with respect to an upper electrode (not
`shown), or target, commonly found in Such systems. In
`effect, the adjustable wafer stage 40 of the present invention
`may be used to vary the distance between the target (upper
`electrode) and wafer stage (bottom electrode) in Such
`Systems, thereby affecting the deposition rates of the mate
`rial formed on a wafer during such a PVD process.
`The controller 74 may sense or detect the positioning of
`the surface 42 by a variety