Case 6:20-cv-00194-ADA Document 1-2 Filed 03/17/20 Page 1 of 18
`Case 6:20-cv-00194-ADA Document 1-2 Filed 03/17/20 Page 1 of 18
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`EXHIBIT 2
`EXHIBIT 2
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`

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`Case 6:20-cv-00194-ADA Document 1-2 Filed 03/17/20 Page 2 of 18
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`
`
`US010474595B2
`
`(12) United States Patent
`US 10,474,595 B2
`Lee
`(45) Date of Patent:
`*Nov. 12, 2019
`
`(10) Patent No.:
`
`(54)
`
`MEMORY MODULE HAVING AN
`OPEN-DRAIN OUTPUT PIN FOR PARITY
`ERROR IN A FIRST MODE AND FOR
`TRAINING SEQUENCES IN A SECOND
`MODE
`
`(71)
`
`Applicant: Netlist, Inc., Irvine, CA (US)
`
`(72)
`
`Inventor: Hyun Lee, Ladera Ranch, CA (US)
`
`(73)
`
`Assignee: NETLIST, INC., Irvine, CA (US)
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`This patent is subject to a terminal dis-
`claimer.
`
`(21)
`
`Appl. No.: 15/857,553
`
`(22)
`
`Filed:
`
`Dec. 28, 2017
`
`(65)
`
`Prior Publication Data
`
`US 2018/0293193 A1
`
`Oct. 11, 2018
`
`Related US. Application Data
`
`(63)
`
`Continuation of application No. 15/088,115, filed on
`Apr. 1, 2016, now Pat. No. 9,858,218, which is a
`(Continued)
`
`Int. Cl.
`
`(51)
`
`G06F 13/16
`GIIC 5/04
`
`US. Cl.
`
`(52)
`
`(2006.01)
`(2006.01)
`(Continued)
`
`CPC ........ G06F 13/1694 (2013.01); G06F 3/0619
`(2013.01); G06F 3/0632 (2013.01);
`(Continued)
`
`(58) Field of Classification Search
`CPC
`G11C 5/00; G11C 16/26; G11C 2029/4402;
`G11C 29/78; G11C 7/1066; G11C 29/52;
`(Continued)
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`3,414,781 A
`3,560,935 A
`
`12/1968 Dill
`2/1971 Beers
`
`(Continued)
`
`OTHER PUBLICATIONS
`
`Inter partes review Case No. IPR2017-00548, Petition for Inter
`Partes Review of US. Pat. No. 8,489,837, filed Dec. 30, 2016.
`
`(Continued)
`
`Primary Examiner 7 Mardochee Chery
`(74) Attorney, Agent, or Firm 7 Morgan, Lewis &
`Bockius LLP
`
`ABSTRACT
`(57)
`According to certain aspects, a memory module is coupled
`to a memory controller of a host computer system via an
`interface. The memory module is operable in at least a
`second mode and a first mode. The memory module in the
`second mode is configured to perform training related to one
`or more training sequences initiated by the memory con-
`troller while the memory module is not accessed by the
`memory controller for memory read or write operations. The
`memory module in the first mode is configured to perform
`one or more memory read or write operations not associated
`with the one or more training sequences by communicating
`data signals with the memory module. The memory module
`has an open-drain output pin via which the memory module
`output a signal indicating a parity error having occurred
`while the memory module is performing a normal memory
`read or write operation, and via which the memory module
`output a signal related to the one or more training sequences.
`
`24 Claims, 3 Drawing Sheets
`
`1 6
`
`14
`
`
`
`
`
`

`

`Case 6:20-cv-00194-ADA Document 1-2 Filed 03/17/20 Page 3 of 18
`Case 6:20-cv-00194-ADA Document 1—2 Filed 03/17/20 Page 3 of 18
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`US 10,474,595 B2
`
`Page 2
`
`(60)
`
`(51)
`
`(52)
`
`(58)
`
`Related U.S. Application Data
`
`continuation of application No. 13/942,721, filed on
`Jul. 16, 2013, now Pat. No. 9,311,116, which is a
`continuation of application No. 12/815,339, filed on
`Jun. 14, 2010, now Pat. No. 8,489,837.
`
`Provisional application No. 61/186,799, filed on Jun.
`12, 2009.
`
`Int. Cl.
`
`G11C 7/10
`G06F 9/445
`G06F 13/24
`G06F 3/06
`G06F 11/10
`G11C 29/52
`G06F 12/06
`G11C 5/00
`G11C 16/26
`G11C 29/00
`G11C 29/44
`U.S. Cl.
`
`(2006.01)
`(2018.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`
`CPC .......... G06F 3/0659 (2013.01); G06F 3/0673
`(2013.01); G06F 9/445 (2013.01); G06F
`11/1068 (2013.01); G06F 12/0646 (2013.01);
`G06F 13/1668 (2013.01); G06F 13/24
`(2013.01); G11C 5/04 (2013.01); G11C 7/1063
`(2013.01); G11C 29/52 (2013.01); G11C 5/00
`(2013.01); G11C 7/1066 (2013.01); G11C
`16/26 (2013.01); G11C 29/78 (2013.01); G11C
`2029/4402 (2013.01); G11C 2207/2254
`(2013.01)
`
`Field of Classification Search
`CPC . G11C 7/1063; G11C 5/04; G11C 2207/2254;
`G06F 13/1694; G06F 12/0646; G06F
`3/0619; G06F 11/1068; G06F 3/0673;
`G06F 3/0659; G06F 3/0632; G06F 13/24;
`G06F 9/445; G06F 13/1668
`USPC .......................................................... 711/154
`
`See application file for complete search history.
`
`(56)
`
`References Cited
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`Inter partes review Case No. IPR2017-00548, Power of Attorney of
`Petitioners, filed Dec. 30, 2016.
`Inter partes review Case No. IPR2017-00548, Exhibit 1002 “File
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`Inter partes review Case No. IPR2017-00548, Exhibit 1003 “Dec-
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`Inter partes review Case No.
`IPR2017-00548, Patent Owner’s
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`Inter partes review Case No.
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`Inter partes review Case No.
`IPR2017-00548, Patent Owner’s
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`Inter partes review Case No. IPR2017-00548, Trial Instituted docu-
`ment dated May 15, 2017.
`Inter partes review Case No. IPR2017-00548, Decision, entered
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`Inter partes review Case No. IPR2017-00548, Scheduling Order,
`entered May 15, 2017.
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`of Dr. Donald Alpert, filed Jul. 31, 2017.
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`IPR2017-00548, Joint Notice of
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`IPR2017-00548, Patent Owner’s
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`Inter Partes Review 0fU.S. Pat. No. 8,489,837, Case No. IPR2017-
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`Inter Partes Review 0fU.S. Pat. No. 8,489,837, Case No. IPR2017-
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`Inter Partes Review 0fU.S. Pat. No. 8,489,837, Case No. IPR2017-
`00548, Exhibit 20057Plaintiff Netlist, NC.’s Amended Opening
`Claim Construction Brief filed Sep. 6, 2017.
`
`

`

`Case 6:20-cv-00194-ADA Document 1-2 Filed 03/17/20 Page 4 of 18
`Case 6:20-cv-00194-ADA Document 1—2 Filed 03/17/20 Page 4 of 18
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`US 10,474,595 B2
`
`Page 3
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`(56)
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`
`
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`
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`

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`Case 6:20-cv-00194-ADA Document 1-2 Filed 03/17/20 Page 5 of 18
`Case 6:20-cv-00194-ADA Document 1—2 Filed 03/17/20 Page 5 of 18
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`US 10,474,595 B2
`Page 4
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`Inter Partes Review of L .S. Pat. \Io. 9,535,623, Case \Io. IPR2018-
`00303, Exhibits 1033, ‘Annotated p. 18 of Ex. 2005,’ filed Nov. 9,
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`Inter Partes Review of L .S. Pat. \Io. 9,535,623, Case \Io. IPR2018-
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`00303, Exhibits 1003, ‘Corrected Declaration of Donald Alpert,’
`filed Dec. 19, 2017.
`
`

`

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`U.S. Patent
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`Nov. 12, 2019
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`Sheet 1 013
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`US 10,474,595 B2
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`U.S. Patent
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`Nov. 12, 2019
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`Sheet 2 of 3
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`US 10,474,595 B2
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`100
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`Provide first memory module
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`Cause the first memory
`module to enter initialization mode
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`102
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`104
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`the at least one first output to a second state
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`Drive the at least one first output to a first state
`while the memory module executes initialization
`sequence
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`Upon completion of initialization sequence, drive
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`Figure 4
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`

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`Case 6:20-cv-00194-ADA Document 1-2 Filed 03/17/20 Page 8 of 18
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`U.S. Patent
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`Nov. 12, 2019
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`Sheet 3 of 3
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`US 10,474,595 B2
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`200
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`\4
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`202
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`Provide first memory module
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`Cause the memory module to enter initialization
`mode
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`Receive notification signal
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`Figure 5
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`US 10,474,595 B2
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`1
`MEMORY MODULE HAVING AN
`OPEN-DRAIN OUTPUT PIN FOR PARITY
`ERROR IN A FIRST MODE AND FOR
`
`TRAINING SEQUENCES IN A SECOND
`MODE
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is a continuation of US. application Ser.
`No. 15/088,115, filed Apr. 1, 2016, to be issued as US. Pat.
`No. 9,858,218, on Jan. 2, 2018, which is a continuation of
`US. application Ser. No. 13/942,721, filed Jul. 16, 2013,
`now US. Pat. No. 9,311,116, whichis a continuation ofU.S.
`application Ser. No. 12/815,339, filed Jun. 14, 2010, now
`US. Pat. No. 8,489,837, which claims the benefit ofpriority
`from US. Provisional App. No. 61/186,799, filed Jun. 12,
`2009, each of which is incorporated in its entirety by
`reference herein.
`
`FIELD OF THE DISCLOSURE
`
`The present disclosure relates to the operation of memory
`modules. Specifically, the present disclosure relates to sys-
`tems and methods for handshaking with a memory module
`during or upon completion of initialization.
`
`BACKGROUND OF THE DISCLOSURE
`
`Memory subsystems such as memory modules are gen-
`erally involved in the initialization procedure for computer
`systems, including servers, personal computers, and the like.
`For example, during system-wide initialization, the memory
`subsystems may undergo internal initialization procedures,
`or the system memory controller may otherwise interact
`with the memory subsystems during the initialization pro-
`cedure. As part of this interaction,
`the system memory
`controller may request that the memory subsystem perform
`one or more requested tasks during system initialization.
`
`SUMMARY
`
`According to certain aspects, a memory module is
`coupled to a memory controller of a host computer system
`via an interface. The interface includes data, address and
`control signal pins and an output pin in addition to the data,
`address and control signal pins. The memory module
`receives a first command from the memory controller via the
`address and control signal pins, and enters a first mode in
`response to the first command. The memory module in the
`first mode responds to at least one initialization sequence,
`and sends a first output signal via the output pin to indicate
`a status of the at least one initialization sequence to the
`memory controller. The memory module enters a second
`mode in which the memory module performs memory
`operations including memory read/write operations accord-
`ing to an industry standard. During the read/write opera-
`tions,
`the memory module communicates data with the
`memory controller via the data signal pins in response to
`second memory commands received via the address and
`control signal pins. The memory module may output a
`second output signal related to the read/write operations via
`the output pin.
`According to certain aspects, a memory module is
`coupled to a memory controller of a host computer system
`via an interface. The interface includes data, address and
`control signal pins and an output pin in addition to the data,
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`address and control signal pins. The memory module per-
`forms an internal procedure in a first mode in response to a
`first command from the memory controller whereby the
`memory controller hands of control of the internal proce-
`dure to the first memory module. The memory module sends
`a first output signal via the output pin to indicate a status of
`the internal procedure to the memory controller. The
`memory module enters a second mode in which the memory
`module performs standard operations including one or more
`of memory read/write, pre-charge,
`refresh operations
`according to an industry standard. The memory module may
`output a second output signal related to the standard opera-
`tions via the output pin.
`In another aspect, a memory module is operable in a first
`mode and in a second mode. The memory module operates
`according to an industry standard in the second mode by
`performing standard operations including memory read/
`write operations in response to address and control signals
`from a memory controller of a host computer system. The
`memory module comprises a standard interface including
`data, address and control signal pins and an output pin in
`addition to the data, address and control signal pins. The
`memory module enters the first mode in response to a first
`command from the memory controller, in which the memory
`module responds to at least one initialization sequence. The
`memory module further comprises a notification circuit to
`output a notification signal indicating a status of the at least
`one initialization sequence to the memory controller via the
`output pin.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 shows an example host computer system including
`an example memory module configured to perform hand-
`shaking with a memory controller of the host computer
`system according to certain embodiments described herein.
`FIG. 2 shows an example host computer system including
`example first and second memory modules configured to
`perform handshaking with a system memory controller of
`the host computer system according to certain embodiments
`described herein.
`
`FIG. 3 shows a host computer system including example
`first and second memory modules configured to perform
`handshaking with a memory controller of the host system,
`where the notification circuits of the first and second
`
`memory modules have another example configuration
`according to certain embodiments described herein.
`FIG. 4 and FIG. 5 show example methods of using at least
`one memory module according to certain embodiments
`described herein.
`
`DETAILED DESCRIPTION
`
`Existing initialization schemes have certain inefficiencies
`which lead to wasted time and expense. Thus, there is a need
`to reduce the time and complexity involved in system
`memory controller interactions with memory subsystems
`during initialization. Certain embodiments described herein
`advantageously satisfy at least a portion of this need by
`providing a system and method which utilizes a feedback
`path from a memory subsystem such as a memory module
`to a system memory controller, such as a Memory Controller
`Hub (MCH) of a computer system during initialization.
`In general, there is no existing method of handshaking
`between the MCH (e.g., system memory controller) and a
`memory subsystem (e.g., memory module) during initial-
`ization. For example, in conventional systems, the system
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`3
`memory controller does not monitor the error-out signal
`from the memory subsystem. This causes the MCH to
`perform blind execution. In a typical server (e. g., an Intel or
`AMD or other chipset based server), the lack of any hand-
`shaking between the MCH and the memory subsystem
`during the server initialization period has not been a serious
`issue since the MCH generally has complete control over the
`initialization procedure. However, one possible configura-
`tion for LR-DIMM (Load Reduced DIMM) includes the
`MCH handing over one or more parts of the initialization
`operation sequence to the memory subsystem. This raises an
`unprecedented issue not addressed in conventional systems
`because, in such proposed configurations, the system can
`benefit from the MCH handshaking with the memory sub-
`system controller, as described more fully below.
`Such an LR-DIMM configuration may have the MCH
`inserting a waiting period of predetermined length during
`which the MCH is idle and the memory subsystem controller
`undergoes initialization. However, one shortcoming of this
`LR-DIMM configuration would be that it requires the MCH
`to be in standby (idle, or wait) while the memory subsystem
`controller completes its task. Under such an arrangement,
`since the time to complete a task can be dependent on the
`density, speed and configuration of the memory subsystem,
`and these parameters may be unknown to the MCH, the
`MCH may have to insert a single, predetermined standby
`period. In addition, if there are multiple occasions that the
`MCH needs to hand of control to the memory subsystem
`controller, the required MCH wait periods can be different
`from one occasion to another, and it complicates the corre-
`lation between the MCH and the memory subsystem con-
`troller. For example, the MCH according to such a scheme
`may give control
`to the local memory controller of a
`memory subsystem (e.g., memory module) for execution of
`a training sequence. The MCH may wait for a pre-deter-
`mined period of time and then assume that the local memory
`controller has completed the training sequence. However,
`depending on the memory subsystem parameters (e.g.,
`memory capacity, speed, number of ranks, etc.), the time for
`actually completing the training sequence may vary and may
`be longer or shorter than predetermined period of time.
`In general, handshaking can be implemented in at least
`two ways; polling and notifying. In the polling method, the
`MCH reads a status register in the memory subsystem
`controller to find out if the memory subsystem controller has
`completed the required or requested operation. For example,
`a status register may be read out through a serial interface
`such as System Management Bus (SMBus). However, a
`register polling method is generally inefficient because the
`system memory controller does not know exactly when the
`memory subsystem will have completed the required or
`requested operation. Thus, the system memory controller
`may wait longer than necessary to poll the memory subsys-
`tem,
`thereby delaying the overall
`initialization process.
`Additionally,
`the problem may be compounded because
`multiple training sequences or other initialization sequences
`may be run on the memory subsystem during a particular
`initialization period,
`resulting in accumulation of such
`unnecessary delays. Moreover, polling generally involves
`scheduling polling intervals during which the system
`memory controller
`is not performing other operations,
`resulting in further inefficiency.
`Alternatively, the notifying method is an advantageous
`handshaking method between the MCH and the memory
`subsystem controller. According to a notifying method, the
`memory subsystem controller sends a signal to the MCH
`when the memory subsystem controller completes the
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`required or requested operation. This method allows the
`MCH to execute one or more independent commands while
`it
`is waiting for a notification signal from the memory
`subsystem controller.
`Certain embodiments described herein provide a method
`of establishing a handshake mechanism based on notifica-
`tion signaling. In certain embodiments, this mechanism can
`be implemented by adding a new interface (notifying) signal
`between the MCH and the memory subsystem controller, or
`by adding an additional functionality to an existing, non-
`timing critical signal without altering the memory subsystem
`hardware. In either case, the interface between the MCH and
`the memory subsystem controller of certain embodiments
`can be an open drain signaling from the memory subsystem
`controller to the MCH, although a variety of other configu-
`rations are possible. As will be appreciated by persons
`skilled in the art, the terms MCH, system memory controller,
`and memory subsystem are used generally interchangeable
`throughout this disclosure, and the terms memory module,
`memory subsystem controller, and local memory controller
`are used generally interchangeably throughout this disclo-
`sure.
`
`FIG. 1 illustrates an example host computer system 16
`including an example memory module 10 according to
`certain embodiments described herein. The memory module
`10 can comprise at least one output 12 configured to be
`operatively coupled to a system memory controller 14 of the
`host computer system 16.
`In certain embodiments,
`the
`memory module 10 is configured to operate in at least two
`modes comprising an initialization mode during which the
`memory module 10 executes at
`least one initialization
`sequence, and an operational mode. The memory module 10
`may further include a controller circuit 18. In some embodi-
`ments, the controller circuit 18 is configured to cause the
`memory module 10 to enter the initialization mode. The
`memory module 10 can further include a notification circuit
`20 configured to drive the at least one output 12 while the
`memory module 10 is in the initialization mode to provide
`at least one notification signal to the memory controller 14
`indicating at least one status of the at least one initialization
`sequence.
`The memory module 10 may comprise a printed-circuit
`board (PCB) 22.
`In certain embodiments,
`the memory
`module 10 has a memory capacity of512-MB, 1-GB, 2-