Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 1 of 22
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`UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
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`
`
`
`Case No. _________
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`JURY TRIAL DEMANDED
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`
`
`
`
`
`
`JAMES B. GOODMAN,
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`
`
`
`
`Plaintiff
`
` v.
`
`
`DELL INC., DELL TECHNOLOGIES, INC. and
`DELL TECHNOLOGIES, LLC,
`
`
`
`
`Defendants
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
`
`Plaintiff James B. Goodman (“Plaintiff” or “Goodman”) hereby files this Original
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`Complaint for Patent Infringement against Defendants Dell Inc., Dell Technologies, Inc. and
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`Dell Technologies, LLC (“Defendant” or “Dell”), and alleges, on information and belief, as
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`follows:
`
`THE PARTIES
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`James Goodman is an individual residing in the State of Texas.
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`On information and belief, Defendant Dell Inc. is a company organized and existing
`
`1.
`
`2.
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`under the laws of Delaware, with a principal place of business at 1 Dell Way, Round Rock,
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`Texas 78682. Dell Inc. may be served through its registered agent, Corporation Service
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`Company, at 211 E. 7th Street, Suite 620, Austin, Texas 78701.
`
`3.
`
`On information and belief, Defendant Dell Technologies, Inc. is a company organized
`
`and existing under the laws of Delaware, with a principal place of business at 1 Dell Way, Round
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
`
`
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`

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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 2 of 22
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`Rock, Texas 78682. Dell Inc. may be served through its registered agent, Corporation Service
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`Company, at 251 Little Falls Drive, Wilmington, Delaware 19808.
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`4.
`
`On information and belief, Defendant Dell Technologies, LLC is a company organized
`
`and existing under the laws of Delaware, with a principal place of business at 1 Dell Way, Round
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`Rock, Texas 78682. Dell Inc. may be served through its registered agent, Registered Agents,
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`Ltd., at 1013 Centre Road, Suite 403-A, Wilmington, Delaware 19805.
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`JURISDICTION AND VENUE
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`5.
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`This action arises under the patent laws of the United States, 35 U.S.C. § 1, et seq. This
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`Court has subject matter jurisdiction under 28 U.S.C. §§ 1331, 1332 and 1338(a).
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`6.
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`7.
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`Defendant has committed acts of infringement in this judicial district.
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`On information and belief, Defendant maintains regular and systematic business interests
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`in this district and throughout the State of Texas including through its representatives, employees
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`and physical facilities.
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`8.
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`On information and belief, the Court has personal jurisdiction over Defendant because
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`Defendant has committed, and continues to commit, acts of infringement in the State of Texas,
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`has conducted business in the State of Texas, and/or has engaged in continuous and systematic
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`activities in the State of Texas. On information and belief, Defendant’s accused instrumentalities
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`that are alleged herein to infringe were and continue to be used, imported, offered for sale, and/or
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`sold in the Western District of Texas.
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`9.
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`On information and belief, Defendant voluntarily conducts business, has 71 job openings
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`currently in Austin, Texas and Round Rock, Texas within this District, including, but not limited
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`to, its headquarters located at 1 Dell Way, Round Rock, Texas 78682. See, e.g.:
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`PAGE | 2
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`

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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 3 of 22
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`Dell website as visited on July 23, 2020:https://www.delltechnologies.com/en-
`us/contactus.htm.
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`
`
`
`
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`Source as visited on July 23, 2020 at: https://headquarters-address.com/dell-corporate-office-
`headquarters-address-email-phone-number/.
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`PAGE | 3
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`

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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 4 of 22
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`
`
`Dell website as visited on July 23, 2020 at: https://jobs.dell.com/search-
`jobs/Austin%2C%20Texas/375-30225/4/6252001-4736286-4737316-4671654/30x26715/-
`97x74306/50/2.
`
`
`
`Dell website as visited on July 23, 2020 at: https://jobs.dell.com/search-
`jobs/Round%20Rock%2C%20Texas/375-30225/4/6252001-4736286-4742143-
`4724129/30x50826/-97x6789/50/2
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`
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`PAGE | 4
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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 5 of 22
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`10.
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`On information and belief, Defendant generates substantial revenue within this District
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`and from the acts of infringement as carried out in this District. As such, the exercise of
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`jurisdiction over Defendant would not offend the traditional notions of fair play and substantial
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`justice.
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`11.
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`Venue is proper in the Western District of Texas pursuant to 28 U.S.C. § 1400(b) and 28
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`U.S.C. § 1391(c)(3).
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`NOTICE OF GOODMANS PATENTS
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`12.
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`Goodman is the inventor and owner of U.S. Patent No. 4,617,624B2 (“the ’624 Patent”)
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`entitled “Multiple configuration memory circuit.” A copy may be obtained at:
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`https://patents.google.com/patent/US4617624A/
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`13.
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`Goodman is the inventor and owner of U.S. Patent No. 6,243,315B1 (“the ’315 Patent”
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`and “the Patent-in-Suit”) entitled “Computer memory system with a low power down mode.” A
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`copy may be obtained at:
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`https://patents.google.com/patent/US6243315B1/en?oq=6%2c243%2c315.
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`14.
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`Goodman is the co-inventor and owner of U.S. Patent No. 6,257,911B1 (“the ’911
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`Patent”) entitled “Low insertion force connector with wipe.” A copy may be obtained at:
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`https://patents.google.com/patent/US6257911.
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`15.
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`16.
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`The foregoing Patents are collectively referred to as “the Goodman Patents.”
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`The Goodman Patents are valid, enforceable, and were duly issued in full compliance
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`with Title 35 of the United States Code.
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`17.
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`Defendants, at least by the date of this Original Complaint, are on notice of the Goodman
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`Patents.
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`PAGE | 5
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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 6 of 22
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`ACCUSED INSTRUMENTALITIES
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`18.
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`On information and belief, Defendants make, use, import, sell, and/or offer for sale a
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`multitude of products and services as memory systems including, but not limited to: Dell
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`PowerEdge RAID Controller H740P • Eight internal ports • 72-bit DDR4-2133 DRAM interface
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`with 8GB non-volatile cache memory; PERC H740P 8 GB DDR4 2133 Mhz cache; PERC
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`H745 4 GB DDR4 2133 Mhz cache; PERC H745P MX 8 GB DDR4 2133 Mhz cache; H840 8
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`GB DDR4 2133 Mhz cache; Dell EMC PowerEdge RAID Controller 10 User’s Guide H345,
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`H740P, H745, H745P MX, and H840 (individually and collectively,
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`the “Accused
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`Instrumentalities”). On information and belief, the Accused Instrumentalities are made, used,
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`sold, offered for sale, and/or imported in the United States by Defendants. See e.g.,
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`Dell Press Release dated: 1/9/2018, Dell Pushes Boundaries with New PCs, Software and
`Partnerships at CES 2018, located at: https://www.dell.com/learn/us/en/uscorp1/press-
`releases/2018-01-08-dell-pushes-boundaries-with-new-pcs-software-and-partnerships-at-ces-
`2018
`
`Dell Latitude 7290 7390 7490 Technical Guidebook (Dated 2018) located at:
`https://topics-cdn.dell.com/pdf/latitude-12-7290-laptop_reference-guide3_en-us.pdf
`
`Latitude 7290
`• DDR4 2400 SDRAM operates at 2133 with Intel 7th Gen
`• DDR4 2400 SDRAM operates at 2400 with Intel 8th Gen
`• One DIMM slot up to 16 GB
`
`Latitude 7390
`• DDR4 2400 SDRAM operates at 2133 with Intel 7th Gen
`• DDR4 2400 SDRAM operates at 2400 with Intel 8th Gen
`• One DIMM slot up to 16 GB
`
`Latitude 7490
`• DDR4 2400 SDRAM operates at 2133 with Intel 7th Gen
`• DDR4 2400 SDRAM operates at 2400 with Intel 8th Gen
`•
`2 DIMM slots supporting up to 32GB
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`
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`PAGE | 6
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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 7 of 22
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`19.
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`Dell makes, offers for sale many computer related products, including desktop
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`computers, laptop computers, servers, and the like, and many of these Dell computer related
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`products incorporate memory products known in the industry as DDR4, memory products. The
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`use of the term “DDR4", to include in the designation of a memory product requires the
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`performance of the memory product to comply with the respective industry standards for
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`performance, and operations.
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`20.
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`The standards published by the Joint Electron Device Engineering Council Solid State
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`Technology Association (“JEDEC”) state for the respective DDR4, memory products and their
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`variation: "No claims to be in conformance with this standard may be made unless all
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`requirements stated in the standard are met."
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`21.
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`On information and belief, the use of the terms “DDR4", and variations thereof implies
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`that the respective memory products comply with the corresponding JEDEC Standards.
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`22.
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`Therefore, the DDR4, memory products and their variations must operate in compliance
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`with the respective standards established by the JEDEC Solid State Technology Association,
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`3103 North 10th Street, Suite 240-S, Arlington, VA 22201.
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`23.
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`Any memory product identified as being a DDR4 memory product after June 2017 or a
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`variation thereof including the term “DDR4" must comply with JEDEC Standard JESD79-4B
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`and JESD79-4C.
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`24.
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`On information and belief, the JEDEC JESD79-4B Standard for DDR4 memory product
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`have several relevant operating capabilities in common when installed in an Dell computer
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`related product, for example: (a) Each memory product has at least two banks of volatile
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`memory, and this is the equivalent of a plurality of volatile solid state memory devices under the
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`doctrine of equivalents; (b) A first external device (supplied by Dell computer related product)
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`PAGE | 7
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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 8 of 22
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`connected to the memory product can provide signals for selectively electrically isolating the
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`address and control lines so that signals on the address and control lines do not reach the memory
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`devices; and (c) A second external device (supplied by Dell computer related product) connected
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`to the memory product can determine when the memory system is not being accessed and can
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`initiate a low power for the memory system wherein the first external device isolates the memory
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`devices and places the memory devices in self refresh mode, thereby reducing the electrical
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`energy drawn from the electrical power supply of the Dell computer related product.
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`25.
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`On information and belief, the aforementioned Dell computer related products
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`incorporating a JEDEC JESD79-4B Standard DDR4 memory product provide
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`the
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`aforementioned first and second external devices in order to take advantage of the respective
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`operating specification of the memory products, including the low power mode that saves
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`electrical energy while protecting the memory product against potential signals which could
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`damage or corrupt the stored data.
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`
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`26.
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`27.
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`COUNT I
`(Infringement of U.S. Patent No. 6,243,315B1)
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`Goodman incorporates the above paragraphs by reference.
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`Defendant has been on notice of the ’315 Patent at least as early as the date it received
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`service of this Original Complaint.
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`28.
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`On information and belief, Defendant has directly infringed and continue to infringe the
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`’315 Patent by making, using, importing, selling, and/or, offering for sale the Accused
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`Instrumentalities in the United States.
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`29.
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`On information and belief, Defendant, with knowledge of the ’315 Patent, indirectly
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`infringes the ’315 Patent by inducing others to infringe the ’315 Patent. In particular, Defendant
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`PAGE | 8
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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 9 of 22
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`intends to induce customers to infringe the ’315 Patent by encouraging customers to use the
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`Accused Instrumentalities in a manner that results in infringement.
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`30.
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`On information and belief, Defendant also induces others, including its customers, to
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`infringe the ’315 Patent by providing technical support for the use of the Accused
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`Instrumentalities.
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`31.
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`On information and belief, the Accused Instrumentalities necessarily infringe one or more
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`claims of the ‘315 Patent when used as intended.
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`32.
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`On information and belief, the Accused Instrumentalities infringe at least Claim 5 of the
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`’315 Patent by providing a memory system for use in a computer system that have a plurality of
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`volatile solid state memory devices that retain information when an electrical power source is
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`applied to said memory devices within a predetermined voltage range and capable of being
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`placed in a self refresh mode. For example, the memory systems are DRAM semiconductor
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`microchip. Further, Defendant provides a memory system that is compatible with the dimensions
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`and pin assignments in accordance with JEDEC industry standard 144 PIN SODIMM connector.
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`33.
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`Further, The Smart Modular Court has determined that a “memory system” is “a system
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`capable of retaining data”. The JESD Standard No. 79-4B, P 12 Section 3.2 Basic Functionality
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`states the DDR4 SDRAM is a high-speed dynamic random-access memory internally configured
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`as sixteen-banks, 4 bank group with 4 banks for each bank group for x4/x8 and eight-banks, 2
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`bank group with 4 banks for each bank group for x16 DRAM. The DDR4 SDRAM uses a 8n
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`prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined
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`with an interface designed to transfer two data words per clock cycle at the I/O pins. A single
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`read or write operation for the DDR4 SDRAM consists of a single 8n-bit wide, four clock data
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 10 of 22
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`transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data
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`transfers at the I/O pins.
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`34.
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`The Smart Modular Court has determined that “memory device” means “integrated
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`circuit or chip”; that “a plurality of volatile solid state memory devices” means “two or more
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`memory devices in the memory system into which data may be written or from which data may
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`be retrieved that retain information while a electrical power source, having a predetermined
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`voltage range, is applied to the memory devices and when the voltage reaches a predetermined
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`threshold outside of that range, the memory devices will no longer retain their current state of
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`information” The JESD79-4B at p. 135 refers to the DDR4 SDRAM as being a “chip”. See Sec.
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`4.26 stating, “the chip enters a Refresh cycle”. It appears that the DDR4 is a chip. The JESD79-
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`4B at sec. 3.2 p. 12 refers to the DDR4 SDRAM as being at the “internal DRAM core”. It
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`appears that the DDR4 internal DRAM core is an integrated circuit. The JESD79-4B at p. 174,
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`Table 81 states the absolute maximum DC Ratings. P. 174, Table 82 shows the recommended
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`DC Operating Conditions with a minimum and maximum for the DC voltages. It appears that the
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`DDR4 requires a specific range of applied of voltage to retain data.
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`35.
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`The following is a Claim Chart for Claim 5 of the ‘315 Patent for the DDR4 memory
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`product:
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 11 of 22
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`Claim 1. A memory system for use in a
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`The Smart Modular Court has determined that a “memory
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`computer system, said memory system
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`system” is “a system capable of retaining data”.
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`The JESD Standard No. 79-4B, P 12 Section 3.2 Basic
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`Functionality states the DDR4 SDRAM is a high-speed
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`dynamic random-access memory internally configured as
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`sixteen-banks, 4 bank group with 4 banks for each bank
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`group for x4/x8 and eight-banks, 2 bank group with 4
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`banks for each bank group for x16 DRAM. The DDR4
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`SDRAM uses a 8n prefetch architecture to achieve high-
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`speed operation. The 8n prefetch architecture is combined
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`comprising:
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` a
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` plurality of volatile solid state memory
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`with an interface designed to transfer two data words per
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`devices that retain information when an
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`clock cycle at the I/O pins. A single read or write
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`electrical power source is applied to said
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`operation for the DDR4 SDRAM consists of a single 8n-
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`memory devices within a predetermined
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`bit wide, four clock data transfer at the internal DRAM
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`voltage range and
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`
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`core and eight corresponding n-bit wide, one-half clock
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`cycle data transfers at the I/O pins.
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`The Smart Modular Court has determined that “memory
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`device” means “integrated circuit or chip”; that “a
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`plurality of volatile solid state memory devices” means
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`“two or more memory devices in the memory system
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`into which data may be written or from which data
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`may be retrieved that retain information while a
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`electrical power source, having a predetermined
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`voltage range, is applied to the memory devices and
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`when the voltage reaches a predetermined threshold
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`outside of that range, the memory devices will no
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`longer retain their current state of information”
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` The JESD79-4B atp. 135 refers to the DDR4 SDRAM as
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`being a “chip”. See Sec. 4.26 stating, “the chip enters a
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`Refresh cycle”. It appears that the DDR4 is a chip.
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`PAGE | 11
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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 12 of 22
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`The JESD79-4B at sec. 3.2 p. 12 refers to the DDR4
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`SDRAM as being at the “internal DRAM core”. It
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`appears that the DDR4 internal DRAM core is
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`an integrated circuit.
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`The JESD79-4B at p. 174, Table 81 states the absolute
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`maximum DC Ratings. P. 174, Table 82 shows the
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`recommended DC Operating Conditions with a minimum
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`and maximum for the DC voltages. It appears that the
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`DDR4 requires a specific range of applied of voltage to
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`retain data.
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`PAGE | 12
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`capable of being placed in a self refresh
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`mode;
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`The JESD79-4B shows that the DDR4 is capable of being
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`refreshed at the following places: p. 41, Sec. 4.9.5
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`entitled, “Self Refresh entry and exit”; p. 135, Sec.
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`4.25.7 entitled, “Refresh Command”; and p. 137, Sec.
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`4.27 entitled, “Self refresh Operation”.
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`JESD79-4B, Page 6
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`2.7 Input Description shows CKE HIGH activates, and
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`CKE Low deactivates, internal clock signals and
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`device input buffers and output drivers. Taking CKE Low
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`provides Precharge Power-Down and Self-Refresh
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`operation (all banks idle), or Active Power-Down (row
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`Active in any bank). CKE is synchronous for Self-Refresh
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`exit. After VREFCA and Internal DQ Vref have become
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`stable during the power on and initialization sequence, they
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`must be maintained during all operations (including Self-
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`Refresh). CKE must be maintained high throughout read
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`and write accesses. Input buffers, excluding CK_t, CK_c,
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`ODT and CKE are disabled during power-down. Input
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`buffers, excluding CKE, are disabled during Self-
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`Refresh. NOTE 15 “X” means “don’t care“ (including floating
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`around VREF) in Self-Refresh and Power-Down. It also applies to
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`Address pins.
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`JESD79-4B, P 137 The Self-Refresh command can be
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`used to retain data in the DDR4 SDRAM, even if the rest
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`of the system is powered down. When in the Self-Refresh
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`mode, the DDR4 SDRAM retains data without external
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`clocking. The DDR4 SDRAM device has a built-in timer
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`to accommodate Self-Refresh operation. The Self-
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`Refresh-Entry (SRE) Command is defined by having
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`CS_n, RAS_n/A16, CAS_n/A15, and CKE held low with
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`WE_n/A14 and ACT_n high at the rising edge of the
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`clock. Before issuing the Self-Refresh-Entry command,
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`the DDR4 SDRAM must be idle with all bank precharge
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`PAGE | 13
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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 14 of 22
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`state with tRP satisfied. ‘Idle state’ is defined as all banks
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`are closed (tRP, tDAL, etc. satisfied), no data bursts are in
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`progress, CKE is high, and all timings from previous
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`operations are satisfied (tMRD, tMOD,tRFC, tZQinit,
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`tZQoper, tZQCS, etc.). Deselect command must be
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`registered on last positive clock edge before issuing Self
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`Refresh Entry command.
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`JESD79-4B, P137, When the DDR4 SDRAM has entered
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`Self-Refresh mode, all of the external control signals,
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`except CKE and RESET_n, are “don’t care.
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`JESD79-4B, P6, CKE HIGH activates, and CKE Low
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`deactivates, internal clock signals and device input
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`buffers and output drivers. Taking CKE Low provides
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`Precharge Power-Down and Self-Refresh operation (all
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`banks idle), or Active Power-Down (row Active in any
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`bank). CKE is synchronous for Self-Refresh exit. Input
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`buffers, excluding CK_t, CK_c, ODT and CKE are disabled
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`during power-down. Input buffers, excluding CKE, are
`disabled during Self-Refresh.
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`PAGE | 14
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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 15 of 22
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`said memory devices having address lines and control
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`The Court has determined that “control device” means “a
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`lines; a control device for selectively electrically isolating
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`device in the memory system that is interposed
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`said memory devices from respective address lines and
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`between the respective address lines and respective
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`respective control lines so that when said memory devices
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`control lines that electrically isolates the memory
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`are electrically isolated, any signals received on said
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`devices”; that “selectively electrically isolating said
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`respective address lines and respective control lines do
`not reach said memory devices; and
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`memory devices from respective address lines and
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`respective control lines’ means “inhibiting signals on the
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`respective address and respective control lines from
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`the memory devices such that signals on those lines do
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`not arrive at the memory devices”; that “address lines”
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`mean “lines that carry signals specifying a memory
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`location to be accessed”; “control lines” mean “lines
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`that carry control signals”; and “control signals” mean
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`“signals that control the sequence of addressing and
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`the memory mode”.
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`During testing and evaluation of the DDR4, it is necessary
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`for DELL to connect subsystems to the DDR4 using the
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`input and output terminals of the DDR4. Obviously, the
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`use of the term “interposed” relates to the electrically
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`operation of the control device, not a physical positioning.
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`The JESD79-4B at p. 6, Sec. 2.7 identifies address lines
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`connected to inputs such as for symbols “BA0-BA2", and
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`“A0-A17". The JESD79-4B uses the terms “command
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`signal”, and “command line” for the defined “control
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`signal” and “control line”. At p. 13, Sec. 2.3, RAS, CAS,
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`WE (line over each) are command inputs. The command
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`signals on the input terminals connect into the DDR4 on
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`“control lines” to control the sequence and memory mode.
`See Command Truth Table, p. 28, Sec. 4.1
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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 16 of 22
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`a memory access enable control device coupled to said
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`JESD79-4B, p. 137, Sec. 4.27 states, the Self-Refresh
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`control device and to said control lines for determining
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`command can be used to retain data in the DDR4 SDRAM,
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`when said memory system is not being accessed and for
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`even if the rest of the system is powered down. When in
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`initiating a low power mode for said memory system
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`wherein said control device electrically isolates said
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`memory devices and places said memory devices in said
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`self refresh mode, thereby reducing the amount of
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`electrical energy being drawn from an electrical power
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`supply for said computer system.
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`the Self-Refresh mode, the DDR4 SDRAM retains data
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`without external clocking.The DDR4 SDRAM device has a
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`built-in timer to accommodate Self-Refresh operation. The
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`Self-Refresh-Entry (SRE) Command is defined by having
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`CS_n, RAS_n/A16, CAS_n/A15, and CKE held low with
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`WE_n/A14 and ACT_n high at the rising edge of the clock.
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`Before issuing the Self-Refresh-Entry command, the DDR4
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`SDRAM must be idle with all bank precharge state with tRP
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`satisfied. ‘Idle state’ is defined as all banks are closed (tRP,
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`tDAL, etc. satisfied), no data bursts are in progress, CKE is
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`high, and all timings from previous operations are satisfied
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`(tMRD, tMOD,tRFC, tZQinit, tZQoper, tZQCS, etc.).
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`Deselect command must be registered on last positive
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`clock edge before issuing Self Refresh Entry command.
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`Once the Self Refresh Entry command is registered,
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`Deselect command must also be registered at the next
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`positive clock edge. Once the Self-Refresh Entry command
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`is registered, CKE must be held low to keep the device in
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`Self-Refresh mode. When the DDR4 SDRAM has entered
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`Self-Refresh mode, all of the external control signals,
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`except CKE and RESET_n, are “don’t care.” For proper
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`Self-Refresh operation, all power supply and reference pins
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`(VDD, VDDQ, VSS, VSSQ, VPP, and VRefCA) must be
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`at valid levels.
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`JESD79-4B, Page 29 Sec. 4.2 CKE Truth Table Table 18
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`NOTE 9 Self-Refresh mode can only be entered from the
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`All Banks Idle state.
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`JESD79-4B, Page 29 Sec. 4.2 CKE Truth Table Table 18
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`NOTE 13 Self-Refresh can not be entered during Read or
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`Write operations. For a detailed list of restrictions See
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`4.27 “Self-Refresh Operation” on page 137 and See 4.28
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`PAGE | 16
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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 17 of 22
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`5. The memory system as claimed in claim 1, wherein the
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`memory devices are DRAM semiconductor microchips.
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`“Power-Down Modes” on page 140.
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`JESD79-4B, Page 6 Sec. 2.7 Chip Select: All commands
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`are masked when CS_n is registered HIGH. CS_n provides
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`for external Rank selection on systems with multiple
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`Ranks. CS_n is considered part of the command code.
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`
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`JESD 79-4B, Page 135, Sec.4.26 Refresh Command
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`The Refresh command (REF) is used during normal
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`operation of the DDR4 SDRAMs. This command is non
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`persistent, so it must be issued each time a refresh is
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`required. The DDR4 SDRAM requires Refresh cycles at
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`an average periodic interval of tREFI. When CS_n,
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`RAS_n/A16 and CAS_n/A15 are held Low and
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`WE_n/A14 and ACT_n are held High at the rising edge of
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`the clock, the chip enters a Refresh cycle.
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`JESD79-4B, P. 12 Sec. 3.2 Basic Functionality states the
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`DDR4 SDRAM is a high-speed dynamic random-access
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`memory internally configured as sixteen-banks, 4 bank
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`group with 4 banks for each bank group for x4/x8 and
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`eight-banks, 2 bank group with 4 banks for each
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`bankgroup for x16 DRAM. The DDR4 SDRAM uses a
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`8n prefetch architecture to achieve high-speed operation.
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`The 8n prefetch architecture is combined with an interface
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`designed to transfer two data words per clock cycle at the
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`I/O pins. A single read or write operation for the DDR4
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`SDRAM consists of a single 8n-bit wide, four clock data
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`transfer at the internal DRAM core and eight
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`corresponding n-bit wide, one-half clock cycle data
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`transfers at the I/O pins.
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`PAGE | 17
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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 18 of 22
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`JESD79-4B P.2, Section 2 DDR4 SDRAM Package
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`Pinout and Addressing.
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`PAGE | 18
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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 19 of 22
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`JESD79-4B Standard Website as visited on July 28, 2020:
`http://www.softnology.biz/pdf/JESD79-4B.pdf.
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`PAGE | 19
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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 20 of 22
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`Dell website as visited on July 23, 2020: https://i.dell.com/sites/doccontent/shared-content/data-
`sheets/en/Documents/Dell-PowerEdge-RAID-Controller-H740P.pdf.
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`PAGE | 20
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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 21 of 22
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`Dell website as visited on July 23, 2020: https://topics-cdn.dell.com/pdf/perc10_ug_en-us.pdf,
`page 8.
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`PAGE | 21
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`Case 6:20-cv-00703-ADA Document 1 Filed 07/30/20 Page 22 of 22
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`PRAYER FOR RELIEF
`WHEREFORE, Goodman respectfully requests the Court enter judgment against Defendant:
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`1.
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`2.
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`declaring that the Defendant has infringed each of the Patent-in-Suit;
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`awarding Goodman its damages suffered as a result of Defendant’s infringement of the
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`Patent-in-Suit;
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`3.
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`4.
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`5.
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`awarding Goodman its costs, attorneys’ fees, expenses, and interest;
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`awarding Goodman ongoing post-trial royalties; and
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`granting Goodman such further relief as the Court finds appropriate.
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`Goodman demands trial by jury, under Fed. R. Civ. P. 38.
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`JURY DEMAND
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`Dated: July 30, 2020
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`Respectfully Submitted
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`
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`/s/ _M. Scott Fuller___
`M. Scott Fuller
`Texas Bar No. 24036607
`sfuller@ghiplaw.com
`Thomas G. Fasone III
`Texas Bar No. 00785382
`tfasone@ghiplaw.com
`GARTEISER HONEA, PLLC
`119 W. Ferguson Street
`Tyler, Texas 75702
`Telephone: (903) 705-7420
`Facsimile: (888) 908-4400
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`ATTORNEYS FOR PLAINTIFF
`JAMES B. GOODMAN
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`ORIGINAL COMPLAINT FOR PATENT INFRINGEMENT
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`PAGE | 22
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