Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 1 of 54
`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 1 of 54
`
`
`
`
`(cid:40)(cid:91)(cid:75)(cid:76)(cid:69)(cid:76)(cid:87)(cid:3)(cid:23)(cid:3)
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`

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`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 2 of 54
`
`USOO8626977B2
`
`(12) United States Patent
`Chu
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8,626,977 B2
`Jan. 7, 2014
`
`(54) COMPUTER SYSTEM INCLUDING CPU OR
`PERPHERAL BRIDGE TO COMMUNCATE
`SERAL BITS OF PERPHERAL
`COMPONENT INTERCONNECT BUS
`TRANSACTION AND LOW VOLTAGE
`DIFFERENTIAL SIGNAL CHANNEL TO
`CONVEY THE SERIAL BITS
`
`(75) Inventor: William W.Y. Chu, Los Altos, CA (US)
`Assignee: Acqis LLC. McKinney, TX (US)
`(73)
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 6 days.
`Appl. No.: 13/560,924
`
`(21)
`(22)
`(65)
`
`Filed:
`
`Jul. 27, 2012
`
`Prior Publication Data
`US 2013/OO24.596 A1
`Jan. 24, 2013
`Related U.S. Application Data
`(63) Continuation of application No. 13/087,912, filed on
`Apr. 15, 2011, now Pat. No. 8,234,436, which is a
`continuation of application No. 12/504,534, filed on
`Jul. 16, 2009, now Pat. No. 8,041,873, which is a
`continuation of application No. 12/077.503, filed on
`Mar. 18, 2008, now Pat. No. 7,676,624, which is a
`continuation of application No. 1 1/166,656, filed on
`Jun. 24, 2005, now Pat. No. 7,376,779, which is a
`continuation of application No. 1 1/097.694, filed on
`Mar. 31, 2005, now Pat. No. 7,363,415, which is a
`continuation of application No. 10/772.214, filed on
`Feb. 3, 2004, now Pat. No. 7,099,981, which is a
`continuation of application No. 09/569,758, filed on
`May 12, 2000, now Pat. No. 6,718,415.
`Provisional application No. 60/134,122, filed on May
`14, 1999.
`
`(60)
`
`(51)
`
`Int. C.
`G06F I3/20
`G06F I3/38
`
`(2006.01)
`(2006.01)
`
`(52) U.S. Cl.
`CPC .................................... G06F 13/385 (2013.01)
`USPC .......................................................... 710/313
`(58) Field of Classification Search
`USPC ............... 710/300–315,8–19, 62-64, 72 74;
`709/214-219, 226-227: 714/43–44,
`714/11, 13
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,769,764 A
`4,799,258 A
`
`9, 1988 Levanon
`1/1989 Davies
`(Continued)
`
`FOREIGN PATENT DOCUMENTS
`
`EP
`JP
`
`T 1996
`O722138 A1
`10, 1994
`6-289953
`(Continued)
`OTHER PUBLICATIONS
`Boosten, “Transmission Overhead and Optimal Packet Size', Mar.
`11, 1998, printed on: Jan. 28, 2011, 2 pgs.
`Primary Examiner — Raymond Phan
`(74) Attorney, Agent, or Firm — Cooley LLP
`
`ABSTRACT
`(57)
`A computer system for multi-processing purposes. The com
`puter system has a console comprising a first coupling site and
`a second coupling site. Each coupling site comprises a con
`nector. The console is an enclosure that is capable of housing
`each coupling site. The system also has a plurality of com
`puter modules, where each of the computer modules is
`coupled to a connector. Each of the computer modules has a
`processing unit, a main memory coupled to the processing
`unit, a graphics controller coupled to the processing unit, and
`a mass storage device coupled to the processing unit. Each of
`the computer modules is Substantially similar in design to
`each other to provide independent processing of each of the
`computer modules in the computer system.
`17 Claims, 31 Drawing Sheets
`
`pc Cock
`
`Asynchronous
`
`95
`primary PC Bus
`
`CBs
`Controller
`
`iO Control
`
`92.5
`
`Host
`terface
`Cotrollier
`
`55
`
`
`
`
`
`
`
`
`
`-------
`
`--PDR3:0), PCNR
`RESET;
`---994
`
`Peripheral
`teace
`Controller
`
`955
`
`
`
`
`
`Secondary
`rics
`980
`
`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 3 of 54
`
`US 8,626,977 B2
`Page 2
`
`(56)
`
`References Cited
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`
`2f1992 Mutone
`5,086,499 A
`4, 1992 Fischer
`5,103,446 A
`3/1993 Woodbury et al.
`5, 191581 A
`3, 1993 Lord
`5,198.806 A
`6, 1994 Takeda
`5,319,771 A
`5,463,742 A 10/1995 Kobayashi
`5,519,843. A
`5, 1996 Moran et al.
`5,539,616 A
`7, 1996 Kikinis
`5,546.463. A
`8/1996 Caputo et al.
`5,550,861 A
`8, 1996 Chan et al.
`5,572,441. A 1 1/1996 Boie
`5,590,377 A 12, 1996 Smith
`5,608,608 A
`3, 1997 Flint et al.
`5,623,637 A
`4/1997 Jones et al.
`5,638,521 A
`6, 1997 Buchala et al.
`5,640,302 A
`6, 1997 Kikinis
`5,648,762 A
`7, 1997 Ichimura et al.
`5,689,654. A 1 1/1997 Kikinis et al.
`5,721,842 A
`2/1998 Beasley et al.
`5,751,711 A
`5, 1998 Sakaue
`5,751,950 A
`5, 1998 Crisan
`5,764,924 A
`6/1998 Hong
`5,774,704 A
`6, 1998 Williams
`5,815,681 A
`9, 1998 Kikinis
`5,819,053 A 10/1998 Goodrum et al.
`5,838,932 A 1 1/1998 Alzien
`5,857,085 A
`1/1999 Zhang et al.
`5,862,381 A
`1/1999 Advani et al.
`5,878,211 A
`3/1999 Delagrange et al.
`5,884,049 A
`3, 1999 Atkinson
`5,907,566 A
`5, 1999 Benson et al.
`5,909,559 A
`6, 1999 SO
`5,933,609 A
`8, 1999 Walker et al.
`5,935,226 A
`8, 1999 Klein
`5,941,965 A
`8, 1999 Moroz et al.
`5,941.968 A * 8/1999 Mergard et al. ............... T10,308
`5.974.486 A 10/1999 Siddappa
`5,978,919 A 1 1/1999 Doi et al.
`5.991,833. A 1 1/1999 Wandler et al.
`5.999,476 A 12/1999 Dutton et al.
`5.999,952. A 12/1999 Jenkins et al.
`6,006,243 A 12/1999 Karidis
`6,012,145 A
`58 Most al.
`6,025,989 A
`2/2000 Ayd et al.
`6,029, 183 A
`2/2000 Jenkins et al.
`6,038,621. A
`3/2000 Gale et al.
`6,046,571 A
`4/2000 Bovio et al.
`6,069,615 A
`5, 2000 Abraham et al.
`6,070214 A
`5, 2000 Ahern
`6,104,921 A
`8/2000 Cosley et al.
`6,157.534 A 12/2000 Gallagher et al.
`6,161,157 A 12/2000 Tripathi
`6,161,524. A 12/2000 Akbarian et al.
`6,199,134 B1
`3/2001 Deschepper et al.
`6,202,115 B1
`3/2001 Khosrowpour
`6,202,169 B1
`3/2001 Razzaghe-Ashrafi et al.
`6,216,185 B1
`4/2001 Chu
`6,226,700 B1
`5, 2001 Wandler et al.
`
`7/2001 Khosrowpour
`6.256,689 B1
`7/2001 Pardo
`6,266,539 B1
`10/2001 Krull et al.
`6,301,637 B1
`10/2001 Schneider et al.
`6,304,895 B1
`10/2001 Chu
`6,311,268 B1
`6,314,522 B1 1 1/2001 Chu
`6,321,277 B1
`1 1/2001 Andresen et al.
`6,321,335 B1 1 1/2001 Chu
`6,324,605 B1
`1 1/2001 Rafferty et al.
`6,332,180 B1
`12/2001 Kauffman et al.
`6,345.330 B2
`2/2002 Chu
`6,366,951 B1
`4, 2002 Schmidt
`6,378,009 B1
`4/2002 Pinkston, II et al.
`6,401,124 B1
`6/2002 Yang et al.
`6,452,790 B1
`9/2002 Chu
`6,453,344 B1
`9, 2002 Ellsworth et al.
`6,460,106 B1
`10/2002 Stufflebeam
`6,477.593 B1
`1 1/2002 Khosrowpour et al.
`6,487.614 B2 11/2002 Nobutani et al.
`6,549,966 B1
`4/2003 Dickens et al.
`6,643,777 B1 1 1/2003 Chu
`6,718,415 B1
`4/2004 Chu
`7,099,981 B2
`8/2006 Chu
`7,146,446 B2 12/2006 Chu
`7,328.297 B2
`2/2008 Chu
`7,363,415 B2
`4/2008 Chu
`7,363.416 B2
`4/2008 Chu
`7,376,779 B2
`5/2008 Chu
`RE41,076 E
`1, 2010 Chu
`RE41,092 E
`1, 2010 Chu
`7,676,624 B2
`3/2010 Chu
`RE41,294 E
`4/2010 Chu
`7,818,487 B2 10/2010 Chu
`RE41,961 E
`11/2010 Chu
`RE42,814 E
`10/2011 Chu
`8,041,873 B2 10/2011 Chu
`RE42.984 E
`11/2011 Chu
`RE43,119 E
`1/2012 Chu
`RE43,171 E
`2, 2012 Chu
`8,234,436 B2
`7/2012 Chu
`RE44,468 E
`8, 2013 Chu
`2001 0011312 A1
`8, 2001 Chu
`2004/0177200 A1
`9, 2004 Chu
`2005/0174729 A1
`8, 2005 Chu
`2005, 0182882 A1
`8, 2005 Chu
`2005/O1955.75 A1
`9, 2005 Chu
`2005/0204083 A1
`9, 2005 Chu
`2.93. A
`3.
`A
`2008/0244149 A1 10, 2008 Ch
`2009. O157939 A1
`6, 2009 Chu
`2010/0174844 A1
`7, 2010 Chu
`2011/0208893 A1
`8, 2011 Chu
`
`FOREIGN PATENT DOCUMENTS
`
`WO
`WO
`WO
`
`WO92, 18924
`WO94/OO970
`WO95/13640
`
`10, 1992
`1, 1994
`5, 1995
`
`* cited by examiner
`
`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 4 of 54
`
`U.S. Patent
`
`US 8,626,977 B2
`
`
`
`WOW(jeuo?do)
`
`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 5 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 2 of 31
`
`US 8,626,977 B2
`
`
`
`
`
`
`
`
`
`
`
`
`
`-
`
`1st ACM Subsystem (Primary)
`
`2O3
`
`Shared Peripheral System
`
`RGB
`..
`O control
`Ethernet Hub
`t
`Controller
`
`NS
`
`e
`
`- 20
`
`‘’’ \| 1st Monitor
`Tzonio
`(Optional)
`24
`
`PC
`Device
`
`I-243
`External
`Ethernet
`235
`- 247
`
`
`
`22EIOController
`Ethernet -
`perhea Controller
`Controller
`
`CDROM DE BUS
`
`
`
`
`
`s".
`
`Bridge
`2 9
`
`Graphics
`ubsystem
`Ethernet
`Controller
`N
`Peripheral iO Controle
`Controller
`Flash
`HDD
`
`
`
`FIGURE 2
`
`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 6 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 3 of 31
`
`US 8,626,977 B2
`
`1st ACM Subsystem (Primary)
`
`Shared Peripheral System
`
`to
`
`
`
`
`
`O Control
`
`s
`
`20
`
`St Monitor
`
`2nd Monitor
`(Optional)
`
`OS
`
`Keyboard
`Mouse
`2nd set
`(Optional)
`
`2nd ACM Subsystem
`209
`2O7
`
`
`
`a. 2 I
`Memory
`AGS, 223
`Graphi
`North
`;S.
`Bridge
`x
`
`Receptacle
`board
`
`Cable
`Connection
`between
`Receptacle
`board & Peripheral
`board
`
`Lo Controller
`PC
`225
`Flash Peripheral
`/BIOST Controller
`2 3
`217 /
`HDD -25
`
`Con
`Cntr
`
`3O7
`3 IO
`
`39
`
`FIGURE 3
`
`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 7 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 4 of 31
`
`US 8,626,977 B2
`
`f00
`TN
`
`429
`
`NO
`
`Alert user of
`missing computer
`module
`
`4O
`
`User selects
`certain file for
`auto backup
`
`
`
`4O3
`
`Other comp.
`Module
`available?
`
`YES
`
`ASK Other module to
`create backup file
`
`405
`
`43 or
`
`User tries
`Eater
`
`433
`
`Tell user backup
`storage full
`
`NO
`
`427
`
`iO7
`
`is storage
`available?
`
`YES
`Backup file and
`set backup timer
`
`4.09
`
`re- 4 II
`423
`
`<G>
`
`
`
`42
`
`- 42
`
`Check for modification
`to selected files
`
`
`
`File changed?
`
`419
`
`1
`
`FIGURE 4
`
`Auto backup
`changed files
`
`4 7
`
`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 8 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 5 of 31
`
`US 8.626,977 B2
`
`Notebook PC
`
`Graphics
`Subsystern
`
`
`
`
`
`
`
`Keyboard
`
`--
`
`- - - ---- r
`
`- or ------
`
`
`
`A- - - - - - - - - -
`
`rr
`
`ury mr- m me we m- ul
`
`PC Bride ge
`Secondary FC Estis
`
`500
`
`:
`igh Pin Count
`(sectOfS
`
`550
`
`PC
`Device
`
`PC Ad
`on Board 2
`
`FIGURE 5
`
`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 9 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 6 of 31
`
`US 8,626,977 B2
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`[29
`
`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 10 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 7 of 31
`
`US 8,626,977 B2
`
`Computing System
`
`
`
`CPU/NB
`Signals
`
`North Bridge S. Primar
`PC Bus Bridge
`A? with
`interface Dev.
`Pair Ard FBus
`
`Host
`Interface
`Controller
`
`Peripheral Systern
`
`Big
`
`CPU/NB
`Bridge signals
`
`El
`
`Interface
`Controller
`
`Secondary PC Bus
`
`PC
`Device
`
`PC Add
`or Board 2
`
`FGURE 7
`
`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 11 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 8 of 31
`
`US 8,626,977 B2
`
`Computing System
`
`
`
`Integrated
`Host
`interface
`H Cntir. &
`North Bridge
`
`Graphics
`Subsystem
`
`Peripheral System
`
`Other Bus
`
`integrated
`Peripheral
`interface
`Critr &
`S. Bridge
`PC Bus -----
`
`805
`
`8 O
`
`FIGURE 8
`
`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 12 of 54
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`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 13 of 54
`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 13 of 54
`
`U.S. Patent
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`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 14 of 54
`
`U.S. Patent
`
`
`
`626,977 B2
`
`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 15 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 12 of 31
`
`US 8,626,977 B2
`
`93O
`Primary PCI Bus
`
`
`
`
`
`Asynchronous
`
`PC Bus
`Controller
`
`iO Control
`
`Host
`Interface
`Controller
`
`XPBUS
`Controller
`
`
`
`92.5
`
`92O
`
`505
`
`
`
`Eosi-PDR3:o), PCNR
`RESETh:
`-- 994
`
`
`
`---
`D.
`XP BS
`Controller
`
`
`
`Peripheral
`Interface
`Controller
`
`955
`
`915
`XP Bus---992
`990 --
`PD3:0), PCN -
`
`
`
`Asynchronous
`
`K.
`
`
`
`Secondary
`
`Device
`
`98O
`
`FIGURE 9
`
`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 16 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 13 of 31
`
`US 8,626,977 B2
`
`
`
`Flash Memory
`BOS
`Configuration
`
`XP BUS
`
`Parallel to H
`
`Serial i Parallel to Serial
`
`PCN
`
`Reset Cit
`Serial to Parallel l PCN
`Converter
`
`Seri
`alto
`BE
`e
`COW
`
`eter s
`
`Serial to
`Parallef
`Converter
`
`- - -, m-m-------- -
`Bus Controller
`
`Merge
`Data Path
`translato AD31:0 in
`
`Controller
`
`Wideo Port Control
`
`FIGURE 1 O
`
`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 17 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 14 of 31
`
`US 8,626,977 B2
`
`
`
`()
`
`Flash Memory
`(Optional)
`
`XPBUS
`
`Parallel to
`
`Serial i Parallel to Serial
`
`p C N R
`
`I 14 3
`
`Converter
`Transmitter
`Reset Cnt.
`1. RE
`p C pon
`Sega to Parallel -
`al
`E. E.
`Serial to
`Parallel B
`less
`
`Paralei
`to Serial
`Converter
`
`I 182 -
`
`I 189
`
`Clock II, f
`Doubler
`2X Video Clock
`
`is
`
`Secondary
`PC
`
`BuS
`
`South
`Bridge
`RESETI-L
`Video
`Capture
`Circuit
`
`Video
`Cock
`
`Video Port Control
`
`FIGURE 11
`
`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 18 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 15 of 31
`
`US 8,626,977 B2
`
`
`
`
`
`
`
`
`
`
`
`symbol
`1 TPDO RTN
`PD0-
`PD1 RTN
`PD-
`PD2 RTN
`
`6
`7
`8
`
`signal
`
`Data Rate
`
`Synch. To PCK 10x clock rate
`
`Synch. To PCK 10 x clock rate
`
`
`
`Description
`
`GN)
`Computer to Peripheral LVDs Data 0.
`
`Computer to Peripheral LVDS Data 1+
`Computer to Peripheral LVDS Data 1
`GND
`Computer to Peripheral LVDS Data2+
`Computer to Peripheral LVDS Data2
`GNO
`
`ENEE Computer to Peripheral LVDS Data 3
`G
`PCKRTN
`NO
`Computer to Peripheral LVDS Clock +
`PCK
`Computer to Peripheral LVDS Clock
`15
`16 PCNRTN
`GND
`10x clock rate
`Synch. To PCK 10x clock rate Computer to Peripheral LVDS Control+
`Computer to Peripheral LVDS Control
`GND
`Peripheral to Computer LVDS Data 0+
`Peripheral to Computer LVDS Data 0
`GNO
`
`PDRO RTN
`PDRO Synch. To PCKR 10x clock rate
`
`PDR1 RTN
`
`
`
`
`
`
`
`
`
`
`
`PDR2 RTN
`PDR2+ synch. To PCKR 10x clock rate
`26
`PDR2-
`28 PDR3 RTN
`
`Synch. To PCKR 10x clock rate
`
`PDR3
`
`Peripheral to Computer LVDS Data2
`GNO
`Peripheral to Computer LVDS Data 3+
`Peripheral to Computer LVDS Data 3
`GND
`Peripheral to Computer LVDS Clock +
`Peripheral to Computer LVDS Clock -
`GND
`PCNR+ Synch. To PCKR 10x clock rate Peripheral to Computer LVDS Control+
`PCNR-
`Peripheral to Computer LVDS Control
`RESETH |
`Asynchronous
`FIGURE 12
`
`PCKRt Reverse Dir Clock Clock rate
`
`
`
`
`
`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 19 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 16 of 31
`
`US 8,626,977 B2
`
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`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 20 of 54
`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 20 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 17 of 31
`
`US 8,626,977 B2
`
`
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`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 21 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 18 of 31
`
`US 8,626,977 B2
`
`PCK
`
`Ed D
`
`-
`
`( : Receiver
`
`PCK
`
`PDO
`
`
`
`PD1
`
`PD2
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`PCN
`
`FIGURE 15
`
`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 22 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 19 of 31
`
`US 8,626,977 B2
`
`FRAME.
`ROY
`TROY
`DEVSELi
`
`SOP
`
`Type Pins Description
`Name
`TS 32 Multiplexed Address/Data. AD is driven to a valid state when GNT# is asserted.
`AD(31:0
`CIBE3:Oil TS
`4 Multiplexed Command/Byte Enables. For a two-address transaction, 1st
`address phase carries the Command, and the 2nd address phase carries the
`transaction type CIBE is driven to a valid state when GNT# is asserted.
`STS 1 indicates beginning and duration of a PCI transaction. When the bus is idle.
`FRAMEli is driven to High for 1 cycle. A pull-up resistor sustains STS signal.
`STS 1 initiator Ready. RDY# is driven High for 1 cycle if bus is idle, and the state is
`Sustained by a pull-up resistor.
`STS 1 Target Ready. When bus is idle, TRDY# is driven High for cycle if bus is idle.
`An external pull-up resistor Sustains STS signal,
`STS 1 Device Select. DEVSELi is asserted by target to indicate it is ready to accept
`the transaction. HC decodes address of a transaction to decide the need to
`assert DEVSELi. As an initiator, HIC waits for 5 cycles to detect assertion of
`DEVSEL# by the target; otherwise HiC terminates with a master abort.
`DEVSEL# is driven High for 1 cycle when bus is idle, and the state is sustained
`by a pull-up resistor,
`STS 1 Target request to stop transaction. There are 3 Cases.
`STOPi, RDYi & DEVSELi asserted: disconnect with data transfer
`Only SOPH & DEVSELi asserted: request initiator to retry later
`Only STOPi asserted: target abort
`STOPi is driven High for 1 cycle when bus is idle, and the state is sustained by
`a pull-up resistor.
`1 Even parity for 36 bits of AD & CIBEF, PAR is sent one cycle after address or
`data is valid. In write transaction, initiator sends PAR One cycle after write data
`is valid. In read transaction, target sends PAR One cycle after read data is valid.
`Input 1 Initiator request lock on target downstream. LOCK# is asserted 1 clock cycle
`after address phase by an initiator wanting to perform an atomic operation that
`take more than ore transaction to Complete, HC passes the LOCK request to
`the Edary PC bus, HIC does not drive LOCKH or propagate LOCK
`upstream.
`input 1 Chip Select for Type 0 configuration access. During a Type 0 configuration
`transaction, the initiator asserts IDSEL# during the address phase to select HIC.
`HIC responds by asserting DEVSEL#.
`STS 1 Data Parity Error on all transactions except Special Cycle, PERRH is driven one
`clock cycle after PAR. PERRii is asserted by target during write transactions,
`and by initiator during read transactions.
`OD 1 System Error. HCasseris SERRii under the following conditions:
`Address parity error. Secondary bus SERRii asserted.
`Posted write transaction: data parity error on target bus. Posted write transaction discarded.
`Master abort. Target abort
`Delayed read of write transaction discarded, and
`Delayed transaction master timeout.
`1 Request for bus, if a target retry or disconnect is received in response to
`initiating a transaction, HIC deasserts REQ# for at least 2 cycles before
`asserting it again.
`Input 1 Bus is granted to HIC. HIC can initiate transaction if GNTi is asserted and the
`bus is idle. When HIC is not requesting bus and GNTH is asserted, HIC must
`drive AD, CBE, and PAR to valid logic levels.
`CLKRUN# I/OD 1 input indicating clock status. HIC can request the central clock resource to start,
`speed up or maintain the PC clock. There are 3 clocking states:
`Clock running, Clock about to stop/slow down, and Clock stopped slowed.
`Input 1 PC Clock, All inputs are sampled on the rising edge of PCICK Frequency
`FIGURE 16
`
`PAR
`
`TS
`
`LOCKi
`
`IDSE it
`
`PERR:
`
`SERRi
`
`REOil
`
`TS
`
`GNT
`
`PCCK
`
`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 23 of 54
`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 23 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 20 of 31
`
`US 8,626,977 132
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`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 24 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 21 of 31
`
`US 8,626,977 B2
`
`
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`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 25 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 22 of 31
`
`US 8,626,977 B2
`
`
`
`FIGURE 19
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`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 26 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 23 of 31
`
`US 8,626,977 B2
`
`
`
`FIGURE 198
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`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 27 of 54
`
`U.S. Patent
`
`US 8,626,977 B2
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`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 28 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 25 Of 31
`
`US 8,626,977 B2
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`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 29 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 26 of 31
`
`US 8,626,977 B2
`
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`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 30 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 27 Of 31
`
`US 8,626,977 B2
`
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`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 31 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 28 of 31
`
`US 8,626,977 B2
`
`AC Power
`
`Supply
`
`Attached
`Computer
`Module (ACM)
`
`
`
`Plug & Display Port
`(Front)
`
`Monitor
`
`USB Port
`
`
`
`USB Keyboard/Mouse
`
`Attached Computer Module with a “Plug & Display' port and direct power connection.
`
`FIGURE 24
`
`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 32 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 29 of 31
`
`US 8,626,977 B2
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`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 33 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 30 of 31
`
`US 8,626,977 B2
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`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 34 of 54
`
`U.S. Patent
`
`Jan. 7, 2014
`
`Sheet 31 of 31
`
`US 8,626,977 B2
`
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`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 35 of 54
`
`US 8,626,977 B2
`
`1.
`COMPUTER SYSTEM INCLUDING CPU OR
`PERIPHERAL BRIDGE TO COMMUNCATE
`SERIAL BITS OF PERPHERAL
`COMPONENT INTERCONNECT BUS
`TRANSACTION AND LOW VOLTAGE
`DIFFERENTIAL SIGNAL CHANNEL TO
`CONVEY THE SERIAL BITS
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`
`This application is a continuation of U.S. patent applica
`tion Ser. No. 13/087,912, filed Apr. 15, 2011, which is a
`continuation of U.S. patent application Ser. No. 12/504,534,
`filed Jul. 16, 2009 (Now U.S. Pat. No. 8,041,873), which is a
`continuation of U.S. patent application Ser. No. 12/077.503,
`filed Mar. 18, 2008 (Now U.S. Pat. No. 7,676,624), which is
`a continuation of U.S. patent application Ser. No. 1 1/166,656,
`filed Jun. 24, 2005 (Now U.S. Pat. No. 7,376,779), which is a
`continuation of U.S. patent application Ser. No. 11/097.694,
`filed Mar. 31, 2005 (Now U.S. Pat. No. 7,363,415), which is
`a continuation of U.S. patent application Ser. No. 10/772.214.
`filed Feb. 3, 2004 (Now U.S. Pat. No. 7,099,981), which is a
`continuation of U.S. patent application Ser. No. 09/569,758,
`filed May 12, 2000 (Now U.S. Pat. No. 6,718,415), and which
`claimed priority to U.S. Provisional Patent Application No.
`60/134,122, filed May 14, 1999. These applications are
`hereby incorporated by reference in their entirety.
`
`10
`
`15
`
`25
`
`BACKGROUND OF THE INVENTION
`
`30
`
`2
`a typewriter format. The keyboard also has the length and
`width for easily inputting information by way of keys to the
`computer. The mouse also has a Sufficient size and shape to
`easily move a curser on the display from one location to
`another location.
`Other types of computing devices include portable com
`puting devices such as "laptop' computers and the like.
`Although somewhat Successful, laptop computers have many
`limitations. These computing devices have poor display tech
`nology. In fact, these devices often have a smaller flat panel
`display that has poor viewing characteristics. Additionally,
`these devices also have poor input devices such as Smaller
`keyboards and the like. Furthermore, these devices have lim
`ited common platforms to transfer information to and from
`these devices and other devices such as PCs.
`Up to now, there has been little common ground between
`these platforms including the PCs and laptops in terms of
`upgrading, ease-of-use, cost, performance, and the like.
`Many differences between these platforms, probably some
`what intentional, have benefited computer manufacturers at
`the cost of consumers. A drawback to having two separate
`computers is that the user must often purchase both the desk
`top and laptop to have “total computing power, where the
`desktop serves as a “regular computer and the laptop serves
`as a “portable' computer. Purchasing both computers is often
`costly and runs “thousands of dollars. The user also wastes a
`significant amount of time transferring software and data
`between the two types of computers. For example, the user
`must often couple the portable computer to a local area net
`work (i.e., LAN), to a serial port with a modem, and then
`manually transfer over files and data between the desktop and
`the portable computer. Alternatively, the user often must use
`floppy disks to "Zip' up files and programs that exceed the
`storage capacity of conventional floppy disks, and transfer the
`floppy disk data manually.
`Another drawback with the current model of separate por
`table and desktop computer is that the user has to spend
`money to buy components and peripherals which are dupli
`cated in at least one of these computers. For example, both the
`desktop and portable computers typically include hard disk
`drives, floppy drives, CD-ROMs, computer memory, host
`processors, graphics accelerators, and the like. Because pro
`gram Software and Supporting programs generally must be
`installed upon both hard drives in order for the user to operate
`programs on the road and in the office, hard disk space is often
`wasted.
`One approach to reduce some of these drawbacks has been
`the use of a docking station with a portable computer. Here,
`the user has the portable computer for “on the road use and
`a docking station that houses the portable computer for office
`SC.
`Similar to separate desktop and portable computers, there
`is no commonality between two desktop computers. To date,
`most personal computers are constructed with a single moth
`erboard that provides connection for CPU and other compo
`nents in the computer. Dual CPU systems have been available
`through Intel's slot 1 architecture. For example, two Pentium
`II cartridges can be plugged into two 'slot 1' card slots on a
`motherboard to form a Dual-processor system. The two
`CPU's share a common hostbus that connects to the rest of
`the system, e.g. main memory, hard disk drive, graphics Sub
`system, and others. Dual CPU systems have the advantage of
`increased CPU performance for the whole system. Adding a
`CPU cartridge requires no change in operating systems and
`application software. However, dual CPU systems may suffer
`limited performance improvement if memory or disk drive
`bandwidth becomes the limiting factor. Also, dual CPU sys
`
`35
`
`45
`
`The present invention relates to computing devices. More
`particularly, the present invention provides a system includ
`ing a plurality of computer modules that can independently
`operate to provide backup capability, dual processing, and the
`like. Merely by way of example, the present invention is
`applied to a modular computing environment for desktop
`computers, but it will be recognized that the invention has a
`much widerrange of applicability. It can be applied to a server
`as well as other portable or modular computing applications.
`40
`Many desktop or personal computers, which are com
`monly termed PCs, have been around and used for over ten
`years. The PCs often come with state-of-art microprocessors
`such as the Intel PentiumTM microprocessor chips. They also
`include a hard or fixed disk drive such as memory in the
`giga-bit range. Additionally, the PCs often include a random
`access memory integrated circuit device Such as a dynamic
`random access memory device, which is commonly termed
`DRAM. The DRAM devices now provide up to millions of
`memory cells (i.e., mega-bit) on a single slice of silicon. PCs
`also include a high resolution display Such as cathode ray
`tubes or CRTs. In most cases, the CRTs are at least 15 inches
`or 17 inches or 20 inches in diameter. High resolution flat
`panel displays are also used with PCs.
`Many external or peripheral devices can be used with the
`PCs. Among others, these peripheral devices include mass
`storage devices such as a ZipTM Drive product sold by Iomega
`Corporation of Utah. Other storage devices include external
`hard drives, tape drives, and others. Additional devices
`include communication devices Such as a modem, which can
`be used to link the PC to a wide area network of computers
`such as the Internet. Furthermore, the PC can include output
`devices such as a printer and other output means. Moreover,
`the PC can include special audio output devices such as
`speakers the like.
`PCs also have easy to use keyboards, mouse input devices,
`and the like. The keyboard is generally configured similar to
`
`50
`
`55
`
`60
`
`65
`
`

`

`Case 6:20-cv-00967 Document 1-4 Filed 10/15/20 Page 36 of 54
`
`US 8,626,977 B2
`
`3
`tems have to time-share the processing unit in running mul
`tiple applications. CPU performance improvement efficiency
`also depends on software coding structure. Dual CPU sys
`tems provide no hardware redundancy to help fault tolerance.
`In running multiple applications, memory and disk drive data
`throughput will become the limiting factor in improving per
`formance with multi-processor systems.
`The present invention generally relates to computer inter
`faces. More specifically, the present invention relates to an
`interface channel that interfaces two computerinterface buses
`that operate under protocols that are different from that used
`by the interface channel.
`Interfaces coupling two independent computer buses are
`well known in the art. A block diagram of a computer system
`utilizing such a prior art interface is shown in FIG. 5. In FIG.
`5, a primary peripheral component interconnect (PCI) bus
`505 of a notebook PC 500 is coupled to a secondary PCI bus
`555 in a docking system 550 (also referred to as docking
`station 550) through high pin count connectors 501 and 502,
`which are normally mating connectors. The high pin count
`connectors 501 and 502 contain a sufficiently large number of
`pins so as to carry PCI bus signals between the two PCI buses
`without any translation. The main purpose for interfacing the
`two independent PCI buses is to allow transactions to occur
`between a master on one PCI bus and a target on the other PCI
`bus. The interface between these two independent PCI buses
`additionally includes an optional PCI to PCI bridge 560,
`located in the docking station 550, to expand the add on
`capability in docking station 550. The bridge 560 creates a
`new bus number for devices behind the bridge 560 so that they
`are not on the same bus number as other devices in the system
`thus increasing the add on capability in the docking station
`550.
`An interface such as that shown in FIG. 5 provides an
`adequate interface between the primary and secondary PCI
`buses. However, the interface is