Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 1 of 55
`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 1 of 55
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`(cid:40)(cid:91)(cid:75)(cid:76)(cid:69)(cid:76)(cid:87)(cid:3)6(cid:3)
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`

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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 2 of 55
`
`US0089.77797B2
`
`(12) United States Patent
`Chu
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8,977,797 B2
`*Mar. 10, 2015
`
`(54)
`
`(71)
`(72)
`(73)
`(*)
`
`(21)
`(22)
`(65)
`
`(63)
`
`METHOD OF IMPROVING PERPHERAL
`COMPONENT INTERFACE
`COMMUNICATIONS UTILIZING ALOW
`VOLTAGE DIFFERENTIAL SIGNAL
`CHANNEL
`
`Applicant: ACQIS LLC, McKinney, TX (US)
`
`Inventor: William W.Y. Chu, Los Altos, CA (US)
`Assignee: ACQIS LLC, McKinney, TX (US)
`Notice:
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 275 days.
`This patent is Subject to a terminal dis
`claimer.
`
`Appl. No.: 13/649,084
`
`Filed:
`
`Oct. 10, 2012
`
`Prior Publication Data
`US 2013/OO97352 A1
`Apr. 18, 2013
`
`Related U.S. Application Data
`Continuation of application No. 13/560,924, filed on
`Jul. 27, 2012, now Pat. No. 8,626,977, which is a
`continuation of application No. 13/087,912, filed on
`Apr. 15, 2011, now Pat. No. 8,234,436, which is a
`(Continued)
`
`(51)
`
`Int. C.
`G06F I3/20
`G06F L/08
`
`(2006.01)
`(2006.01)
`(Continued)
`
`(52)
`
`U.S. C.
`CPC. G06F I/08 (2013.01); G06F 1/12 (2013.01);
`G06F 13/385 (2013.01); G06F 13/4068
`(2013.01); G06F 13/42 (2013.01)
`USPC .......................................................... 710/313
`
`(58) Field of Classification Search
`CPC ................................................... GO6F 13f4081
`USPC ......... 710/300-304,313 315, 62-64, 72-74;
`709/214 21, 226 227; 726/2-9,
`726/16–21, 34, 36; 713/182-183, 192-194
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`4,769,764 A
`4,799,258 A
`
`9, 1988 Levanon
`1/1989 Davies
`(Continued)
`
`FOREIGN PATENT DOCUMENTS
`
`EP
`JP
`
`T 1996
`O722138 A1
`10, 1994
`6-289953
`(Continued)
`OTHER PUBLICATIONS
`
`Boosten, “Transmission Overhead and Optimal Packet Size', Mar.
`11, 1998, printed on: Jan. 28, 2011, 2 pgs.
`Primary Examiner — Raymond Phan
`(74) Attorney, Agent, or Firm — Cooley LLP
`
`ABSTRACT
`(57)
`A computer system for multi-processing purposes. The com
`puter system has a console comprising a first coupling site and
`a second coupling site. Each coupling site comprises a con
`nector. The console is an enclosure that is capable of housing
`each coupling site. The system also has a plurality of com
`puter modules, where each of the computer modules is
`coupled to a connector. Each of the computer modules has a
`processing unit, a main memory coupled to the processing
`unit, a graphics controller coupled to the processing unit, and
`a mass storage device coupled to the processing unit. Each of
`the computer modules is Substantially similar in design to
`each other to provide independent processing of each of the
`computer modules in the computer system.
`
`38 Claims, 31 Drawing Sheets
`
`
`
`
`
`
`
`Secondary Cwsr Staggy
`
`
`
`Other
`Esvices
`season
`- T
`Prirary Power Supply
`
`i:S
`
`:
`
`1863
`
`7
`
`33
`
`

`

`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 3 of 55
`
`US 8,977,797 B2
`Page 2
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`(60)
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`(51)
`
`(56)
`
`Related U.S. Application Data
`continuation of application No. 12/504,534, filed on
`Jul. 16, 2009, now Pat. No. 8,041,873, which is a
`continuation of application No. 12/077.503, filed on
`Mar. 18, 2008, now Pat. No. 7,676,624, which is a
`continuation of application No. 1 1/166,656, filed on
`Jun. 24, 2005, now Pat. No. 7,376,779, which is a
`continuation of application No. 1 1/097.694, filed on
`Mar. 31, 2005, now Pat. No. 7,363,415, which is a
`continuation of application No. 10/772.214, filed on
`Feb. 3, 2004, now Pat. No. 7,099,981, which is a con
`tinuation of application No. 09/569,758, filed on May
`12, 2000, now Pat. No. 6,718,415.
`Provisional application No. 60/134,122, filed on May
`14, 1999.
`
`Int. C.
`G06F L/2
`G06F I3/38
`G06F 3/40
`G06F 3/42
`
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`2f1992 Mutone
`5,086,499 A
`4, 1992 Fischer
`5,103,446 A
`3/1993 Woodbury et al.
`5, 191581 A
`3, 1993 Lord
`5,198.806 A
`6, 1994 Takeda
`5,319,771 A
`5,463,742 A 10/1995 Kobayashi
`5,519,843. A
`5, 1996 Moran et al.
`5,539,616 A
`7, 1996 Kikinis
`5,546.463. A
`8/1996 Caputo et al.
`5,550,861 A
`8, 1996 Chan et al.
`5,572,441 A 11/1996 Boie
`5,590,377 A 12, 1996 Smith
`5,608,608 A
`3, 1997 Flint et al.
`5,623,637 A
`4/1997 Jones et al.
`5,638,521 A
`6, 1997 Buchala et al.
`5,640,302 A
`6, 1997 Kikinis
`5,648,762 A
`7, 1997 Ichimura et al.
`5,689,654 A 11/1997 Kikinis et al.
`5,721,842 A
`2/1998 Beasley et al.
`5,751,711 A
`5, 1998 Sakaue
`5,751,950 A
`5, 1998 Crisan
`5,764,924 A
`6/1998 Hong
`5,774,704 A
`6, 1998 Williams
`5,815,681 A
`9, 1998 Kikinis
`5,819,053 A 10, 1998 Goodrum et al.
`5,838,932 A 11/1998 Alzien
`5,857,085 A
`1/1999 Zhang et al.
`5,862,381 A
`1/1999 Advani et al.
`5,878,211 A
`3/1999 Delagrange et al.
`5,884,049 A
`3, 1999 Atkinson
`5,907,566 A
`5, 1999 Benson et al.
`5,909,559 A
`6, 1999 SO
`5,933,609 A
`8, 1999 Walker et al.
`5,935,226 A
`8, 1999 Klein
`5,941,965 A
`8, 1999 Moroz et al.
`5,941,968 A
`8/1999 Mergard et al.
`5,974,486 A 10/1999 Siddappa
`5,978,919 A 11/1999 Doi et al.
`5.991,833. A 11/1999 Wandler et al.
`5,999.476 A 12/1999 Dutton et al.
`5.999,952 A 12/1999 Jenkins et al.
`6,006,243 A 12/1999 Karidis
`6,012,145 A
`1/2000 Mathers et al.
`6,025,989 A
`2/2000 Ayd et al.
`6,029, 183 A
`2, 2000 Jenkins et al.
`
`6,038,621
`6,046,571
`6,069,615
`6,070,214
`6,104,921
`6,157,534
`6,161,157
`6,161,524
`6,199,134 B1
`6,202,115 B1
`6,202,169 B1
`6,216,185 B1
`6,226,700 B1
`6.256,689 B1
`6,266,539 B1
`6,301,637 B1
`6,304,895 B1
`6,311,268 B1
`6,314,522 B1
`6,321,277 B1
`6,321,335 B1
`6,324,605 B1
`6,332,180 B1
`6,345,330
`6,366,951 B1
`6,378,009 B1
`6,401,124 B1
`6,452,790 B1
`6,453,344 B1
`6,460,106 B1
`6,477,593 B1
`6,487.614
`6,549,966 B1
`6,643,777 B1
`6,718,415 B1
`7,099.981
`7,146,446
`7,328.297
`7,363,415
`7,363.416
`7,376,779
`RE41,076 E
`RE41,092 E
`7,676,624
`RE41,294 E
`7,818,487
`RE41,961 E
`RE42,814 E
`8,041,873
`RE42.984 E
`RE43,119 E
`RE43,171 E
`8,234,436
`RE43,602 E
`RE44,468 E
`RE44,654 E *
`2001 0011312 A1
`2004/01772OO A1
`2005/0174729 A1
`2005, 0182882 A1
`2005/O1955.75 A1
`2005/0204083 A1
`2005.0246469 A1
`2006/0265361 A1
`2008/0244149 A1
`2009. O157939 A1
`2010/0174844 A1
`2011/0208893 A1
`
`3, 2000
`4, 2000
`5/2000
`5/2000
`8, 2000
`12, 2000
`12, 2000
`12, 2000
`3, 2001
`3, 2001
`3, 2001
`4, 2001
`5/2001
`T/2001
`T/2001
`10, 2001
`10, 2001
`10, 2001
`11, 2001
`11, 2001
`11, 2001
`11, 2001
`12, 2001
`2, 2002
`4, 2002
`4, 2002
`6, 2002
`9, 2002
`9, 2002
`10, 2002
`11, 2002
`11, 2002
`4/2003
`11/2003
`4, 2004
`8, 2006
`12, 2006
`2, 2008
`4/2008
`4/2008
`5/2008
`1, 2010
`1, 2010
`3, 2010
`4, 2010
`10, 2010
`11, 2010
`10, 2011
`10, 2011
`11, 2011
`1, 2012
`2, 2012
`T/2012
`8, 2012
`8, 2013
`12/2013
`8, 2001
`9, 2004
`8, 2005
`8, 2005
`9, 2005
`9, 2005
`11/2005
`11, 2006
`10, 2008
`6, 2009
`T/2010
`8, 2011
`
`FOREIGN PATENT DOCUMENTS
`
`WO
`WO92, 18924
`WO
`WO94/OO970
`WO
`WO95/13640
`* cited by examiner
`
`10, 1992
`1, 1994
`5, 1995
`
`Gale et al.
`Bovio et al.
`Abraham et al.
`Ahern
`Cosley et al.
`Gallagher et al.
`Tripathi
`Akbarian et al.
`Deschepper et al.
`Khosrowpour
`RaZZaghe-Ashrafi et al.
`Chu
`Wandler et al.
`Khosrowpour
`Pardo
`Krull et al.
`Schneider et al.
`Chu
`Chu
`Andresen et al.
`Chu
`Rafferty et al.
`Kauffman et al.
`Chu
`Schmidt
`Pinkston, II et al.
`Yang et al.
`Chu
`Ellsworth et al.
`Stufflebeam
`Khosrowpour et al.
`Nobutani et al.
`Dickens et al.
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
`Chu
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`. T26, 16
`
`

`

`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 4 of 55
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`U.S. Patent
`
`US 8,977,797 B2
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`
`
`
`
`

`

`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 5 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 2 of 31
`
`US 8,977,797 B2
`
`st ACM Subsystem (Primary) f-213
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`
`

`

`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 6 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 3 of 31
`
`US 8,977,797 B2
`
`
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`
`

`

`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 7 of 55
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`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 4 of 31
`
`US 8,977,797 B2
`
`400-
`
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`

`

`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 8 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 5 of 31
`
`US 8,977,797 B2
`
`Notes is
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`

`

`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 9 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 6 of 31
`
`US 8,977,797 B2
`
`009,
`
`
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`*********~
`
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`
`

`

`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 10 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 7 of 31
`
`US 8,977,797 B2
`
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`

`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 11 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 8 of 31
`
`US 8,977,797 B2
`
`Copa is g Syster
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`

`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 12 of 55
`
`U.S. Patent
`
`US 8,977,797 B2
`
`

`

`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 13 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 10 of 31
`
`US 8,977,797 B2
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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 14 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 11 of 31
`
`US 8,977,797 B2
`
`
`
`

`

`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 15 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 12 of 31
`
`US 8,977,797 B2
`
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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 16 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 13 of 31
`
`US 8,977,797 B2
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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 17 of 55
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`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 14 of 31
`
`US 8,977,797 B2
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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 18 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 15 of 31
`
`US 8,977,797 B2
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`Data Rate
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`Description
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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 19 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 16 of 31
`
`US 8,977,797 B2
`
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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 20 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 17 of 31
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`US 8,977,797 B2
`
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`

`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 21 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 18 of 31
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`US 8,977,797 B2
`
`K
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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 22 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 19 of 31
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`US 8,977,797 B2
`
`Nafis
`AD3i:0
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`FRA.E.
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`RY
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`Type Pins Description
`32 Multiplexes. Addressitata, Ai is driver to a waiti state when GN # is asserted.
`Ts s
`4. Multiplexed Cominanci? Ryte Enabies. For a two-address transaction, 1st
`s
`address phase carries the Cominand, and the 2nd address phase carries the
`transaction type CBE is driver to a valid state when GNii is asserted.
`indicates beginning and durater of a PC trassaction. When the bus is ide.
`FRAAEii is driven to tigh for cycle. A pit-up resistor sustains SS sigtai.
`initiatif Ready, REY# is driven High for 4 cycle if bus is idie, and the state is
`sustaired by a pus-tip resistor.
`Target Ready. Wher biasis ice, TRYi is driven High for cycle if bus is die.
`An exterial put-up fesistor sistains STS signat,
`Device Select. DEVSEii is asserted by target to indicate it is teady to accept
`the transaction. C decodes address of a transaction to decide the feed to
`assert DEVSEli. As at isitiator, Hit waits for 5 cycles to detect assertion of
`DEWSEiff by the target; otherwise iC terminates with a master abort,
`EWSEii is riven High for cycle when bus is die, aid the state is sustaired
`by a pisii-ig resistor.
`targe regiest to steg tiansaction, iere ar:3 cases,
`SQFi, RDYi & EWSEli asserted: disconnect with data transfer
`Oriy SOP. & DEWSE: asserted: seques: initiato? to fety later
`Oniy SiOPi asserted: target abort
`STOPi is driver high for cycie wheir biasis idis, and tie state is sustained by
`a pti-iip resistoi,
`Evergarity for 36 bits of AD & CBEii. PAR is sent one cycle after address or
`data is waii, in write transaction, initiato sentis PAR (fe cycle atte write data
`is valid in read transaction, arget sends PARge cycie after tead cata is waiti.
`initiator request lock on target downstream. OCK# is asserted clock cycle
`after address phase by a? initiatof wanting to performan atonic operation that
`take more that of 8 transation to Complete. HC passes the C-CK# request to
`the secondary PC bus. HiC does not drive OCK# or propagate OCK
`upsteai,
`Chip Select for type () configuration access. During a type () configuratic:
`transaction, the initiator asserts DSEii disting the address phase to selectiiC,
`HIC responds by asserting DEVSEff.
`tata arity Error of ai: transactions except Special Cycie. PERRii is driven one
`clock cycle after FAR. PERRii is asserted by target during write transactions,
`andy initiator ifing read transactic}{S,
`System Error. HiCasserts SERRif inder the following conditions:
`Address parity effor, Secondary bus SERRig asserted.
`Posted write transaction: data parity error on target bus. Posted write transaction discarded.
`siasteratisfi, Taigeiaisoft
`Delayed read or write trafsaction discarded, and
`Detayed transactia master tireout.
`Reguest for bus, if a target retry of discon?ect is received in Fesponse to
`initiating a transaction, C deasserts REQi for at teast 2 cycles before
`asserting it again.
`Bus is grated io iC, HiC cai initiate transaction if Shi'i is asserted and the
`bus is idle. When HC is not requesting bus and GNii is asserted, HC Yust
`drive AD, CIBE, and PAR to waiti is gig levels.
`ingiit indicating clock status. HiC car request the Central clock resource to start,
`spead up or maintain the PC clock. There are 3 clocking states:
`Clock running, Clock about to stopistow down, a?id Clock stopped slowed.
`PC cock, Ai inputs are sampted or the rising edge of PCCK Frequency
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`

`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 23 of 55
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`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 20 of 31
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`US 8,977,797 B2
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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 24 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 21 of 31
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`US 8,977,797 B2
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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 25 of 55
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`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 22 of 31
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`US 8,977,797 B2
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`
`
`

`

`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 26 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 23 of 31
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`US 8,977,797 B2
`
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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 27 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 24 of 31
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`US 8,977,797 B2
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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 28 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
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`Sheet 25 of 31
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`US 8,977,797 B2
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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 29 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 26 of 31
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`US 8,977,797 B2
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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 30 of 55
`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 30 of 55
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`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 27 of 31
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`US 8,977,797 B2
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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 31 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 28 of 31
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`US 8,977,797 B2
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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 32 of 55
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`U.S. Patent
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`Sheet 29 of 31
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`US 8,977,797 B2
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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 33 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 30 of 31
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`US 8,977,797 B2
`
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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 34 of 55
`
`U.S. Patent
`
`Mar. 10, 2015
`
`Sheet 31 of 31
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`US 8,977,797 B2
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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 35 of 55
`
`US 8,977,797 B2
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`1.
`METHOD OF IMPROVING PERPHERAL
`COMPONENT INTERFACE
`COMMUNICATIONS UTILIZING ALOW
`VOLTAGE DIFFERENTIAL SIGNAL
`CHANNEL
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`
`This application is a continuation of U.S. patent applica
`tion Ser. No. 13/560,924, filed Jul. 27, 2012, which is a
`continuation of U.S. patent application Ser. No. 13/087,912,
`filed Apr. 15, 2011 (Now U.S. Pat. No. 8,234,436), which is a
`continuation of U.S. patent application Ser. No. 12/504,534,
`filed Jul. 16, 2009 (Now U.S. Pat. No. 8,041,873), which is a
`continuation of U.S. patent application Ser. No. 12/077.503,
`filed Mar. 18, 2008 (Now U.S. Pat. No. 7,676,624), which is
`a continuation of U.S. patent application Ser. No. 1 1/166,656,
`filed Jun. 24, 2005 (Now U.S. Pat. No. 7,376,779), which is a
`continuation of U.S. patent application Ser. No. 11/097.694,
`filed Mar. 31, 2005 (Now U.S. Pat. No. 7,363,415), which is
`a continuation of U.S. patent application Ser. No. 10/772.214.
`filed Feb. 3, 2004 (Now U.S. Pat. No. 7,099,981), which is a
`continuation of U.S. patent application Ser. No. 09/569,758,
`filed May 12, 2000 (Now U.S. Pat. No. 6,718,415), and which
`claimed priority to U.S. Provisional Patent Application No.
`60/134,122, filed May 14, 1999. These applications are
`hereby incorporated by reference in their entirety.
`
`10
`
`15
`
`25
`
`BACKGROUND OF THE INVENTION
`
`30
`
`2
`a typewriter format. The keyboard also has the length and
`width for easily inputting information by way of keys to the
`computer. The mouse also has a Sufficient size and shape to
`easily move a curser on the display from one location to
`another location.
`Other types of computing devices include portable com
`puting devices such as "laptop' computers and the like.
`Although somewhat Successful, laptop computers have many
`limitations. These computing devices have poor display tech
`nology. In fact, these devices often have a smaller flat panel
`display that has poor viewing characteristics. Additionally,
`these devices also have poor input devices such as Smaller
`keyboards and the like. Furthermore, these devices have lim
`ited common platforms to transfer information to and from
`these devices and other devices such as PCs.
`Up to now, there has been little common ground between
`these platforms including the PCs and laptops in terms of
`upgrading, ease-of-use, cost, performance, and the like.
`Many differences between these platforms, probably some
`what intentional, have benefited computer manufacturers at
`the cost of consumers. A drawback to having two separate
`computers is that the user must often purchase both the desk
`top and laptop to have “total computing power, where the
`desktop serves as a “regular computer and the laptop serves
`as a “portable' computer. Purchasing both computers is often
`costly and runs “thousands of dollars. The user also wastes a
`significant amount of time transferring software and data
`between the two types of computers. For example, the user
`must often couple the portable computer to a local area net
`work (i.e., LAN), to a serial port with a modem, and then
`manually transfer over files and data between the desktop and
`the portable computer. Alternatively, the user often must use
`floppy disks to "Zip' up files and programs that exceed the
`storage capacity of conventional floppy disks, and transfer the
`floppy disk data manually.
`Another drawback with the current model of separate por
`table and desktop computer is that the user has to spend
`money to buy components and peripherals which are dupli
`cated in at least one of these computers. For example, both the
`desktop and portable computers typically include hard disk
`drives, floppy drives, CD-ROMs, computer memory, host
`processors, graphics accelerators, and the like. Because pro
`gram Software and Supporting programs generally must be
`installed upon both hard drives in order for the user to operate
`programs on the road and in the office, hard disk space is often
`wasted.
`One approach to reduce some of these drawbacks has been
`the use of a docking station with a portable computer. Here,
`the user has the portable computer for “on the road use and
`a docking station that houses the portable computer for office
`SC.
`Similar to separate desktop and portable computers, there
`is no commonality between two desktop computers. To date,
`most personal computers are constructed with a single moth
`erboard that provides connection for CPU and other compo
`nents in the computer. Dual CPU systems have been available
`through Intel's slot 1 architecture. For example, two Pentium
`II cartridges can be plugged into two 'slot 1' card slots on a
`motherboard to form a Dual-processor system. The two
`CPU's share a common hostbus that connects to the rest of
`the system, e.g. main memory, hard disk drive, graphics Sub
`system, and others. Dual CPU systems have the advantage of
`increased CPU performance for the whole system. Adding a
`CPU cartridge requires no change in operating systems and
`application software. However, dual CPU systems may suffer
`limited performance improvement if memory or disk drive
`bandwidth becomes the limiting factor. Also, dual CPU sys
`
`35
`
`45
`
`The present invention relates to computing devices. More
`particularly, the present invention provides a system includ
`ing a plurality of computer modules that can independently
`operate to provide backup capability, dual processing, and the
`like. Merely by way of example, the present invention is
`applied to a modular computing environment for desktop
`computers, but it will be recognized that the invention has a
`much widerrange of applicability. It can be applied to a server
`as well as other portable or modular computing applications.
`40
`Many desktop or personal computers, which are com
`monly termed PCs, have been around and used for over ten
`years. The PCs often come with state-of-art microprocessors
`such as the Intel PentiumTM microprocessor chips. They also
`include a hard or fixed disk drive such as memory in the
`giga-bit range. Additionally, the PCs often include a random
`access memory integrated circuit device Such as a dynamic
`random access memory device, which is commonly termed
`DRAM. The DRAM devices now provide up to millions of
`memory cells (i.e., mega-bit) on a single slice of silicon. PCs
`also include a high resolution display Such as cathode ray
`tubes or CRTs. In most cases, the CRTs are at least 15 inches
`or 17 inches or 20 inches in diameter. High resolution flat
`panel displays are also used with PCs.
`Many external or peripheral devices can be used with the
`PCs. Among others, these peripheral devices include mass
`storage devices such as a ZipTM Drive product sold by Iomega
`Corporation of Utah. Other storage devices include external
`hard drives, tape drives, and others. Additional devices
`include communication devices Such as a modem, which can
`be used to link the PC to a wide area network of computers
`such as the Internet. Furthermore, the PC can include output
`devices such as a printer and other output means. Moreover,
`the PC can include special audio output devices such as
`speakers the like.
`PCs also have easy to use keyboards, mouse input devices,
`and the like. The keyboard is generally configured similar to
`
`50
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`55
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`Case 6:20-cv-00967 Document 1-6 Filed 10/15/20 Page 36 of 55
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`US 8,977,797 B2
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`3
`tems have to time-share the processing unit in running mul
`tiple applications. CPU performance improvement efficiency
`also depends on software coding structure. Dual CPU sys
`tems provide no hardware redundancy to help fault tolerance.
`In running multiple applications, memory and disk drive data
`throughput will become the limiting factor in improving per
`formance with multi-processor systems.
`The present invention generally relates to computer inter
`faces. More specifically, the present invention relates to an
`interface channel that interfaces two computerinterface buses
`that operate under protocols that are different from that used
`by the interface channel.
`Interfaces coupling two independent computer buses are
`well known in the art. A block diagram of a computer system
`utilizing such a prior art interface is shown in FIG. 5. In FIG.
`5, a primary peripheral component interconnect (PCI) bus
`505 of a notebook PC 500 is coupled to a secondary PCI bus
`555 in a docking system 550 (also referred to as docking
`station 550) through high pin count connectors 501 and 502,
`which are normally mating connectors. The high pin count
`connectors 501 and 502 contain a sufficiently large number of
`pins so as to carry PCI bus signals between the two PCI buses
`without any translation. The main purpose for interfacing the
`two independent PCI buses is to allow transactions to occur
`between a master on one PCI bus and a target on the other PCI
`bus. The interface between these two independent PCI buses
`additionally includes an optional PCI to PCI bridge 560,
`located in the docking station 550, to expand the add on
`capability in docking station 550. The bridge 560 creates a
`new bus number for devices behind the bridge 560 so that they
`are not on the same bus number as other d