Case 6:20-cv-01042-ADA Document 1 Filed 11/11/20 Page 1 of 18
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`UNITED STATES DISTRICT COURT
`WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`
`The CALIFORNIA INSTITUTE OF
`TECHNOLOGY,
`
`
`Plaintiff,
`
`
`v.
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`DELL TECHNOLOGIES INC. and DELL
`INC.,
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`§
`§
`§
`§
`§
`§
`§
`§
`§
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`Defendants.
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`
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`Civil Action No.: 6:20-cv-1042
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`JURY TRIAL DEMANDED
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`COMPLAINT FOR PATENT INFRINGEMENT
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`Plaintiff the California Institute of Technology (“Caltech” or “Plaintiff”), by and through
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`its undersigned counsel, complains and alleges against Dell Technologies Inc. and Dell Inc.
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`(collectively “Dell” or “Defendants”) as follows:
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`NATURE OF THE ACTION
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`1.
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`This is a civil action for infringement of U.S. Patent No. 7,116,710, U.S. Patent No.
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`7,421,032, and U.S. Patent No. 7,916,781 (collectively, “the Asserted Patents”) arising under the
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`patent laws of the United States, 35 U.S.C. §§ 1 et seq.
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`2.
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` Earlier this year, a jury found that Apple Inc.’s (“Apple’s”) and Broadcom
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`Limited’s (“Broadcom’s”) Wi-Fi products infringed the Asserted Patents and awarded Caltech over
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`$1.1 billion in damages. Caltech v. Broadcom Limited, et al., No. 16-cv-3714-GW, Dkt. No. 2114
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`(C.D. Cal. Jan. 29, 2020). As in the case against Apple and Broadcom, Caltech seeks a reasonable
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`royalty from Dell as compensation for its infringement of the Asserted Patents.
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`THE PARTIES
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`3.
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`Caltech is a non-profit private university organized under the laws of the State of
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`California, with its principal place of business at 1200 East California Boulevard, Pasadena,
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`California 91125.
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`COMPLAINT
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`Page | 1
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`Case 6:20-cv-01042-ADA Document 1 Filed 11/11/20 Page 2 of 18
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`4.
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`Caltech is a world-renowned science and engineering research and education
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`institution, where extraordinary faculty and students seek answers to complex questions, discover
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`new knowledge, lead innovation, and transform our future. To date, 40 Caltech alumni and faculty
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`have won a total of 41 Nobel Prizes. The mission of Caltech is to expand human knowledge and
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`benefit society through research integrated with education. Caltech investigates the most
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`challenging, fundamental problems in science and technology in a singularly collegial,
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`interdisciplinary atmosphere, while educating outstanding students to become creative members of
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`society. Caltech’s investment in research has led Caltech to have more inventions disclosed and
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`patents granted per faculty member than any other university in the nation, and to be consistently
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`ranked as one of the top university patent portfolios in strength and number of patents issued.
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`5.
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`On information and belief, defendant Dell Technologies Inc. is a Delaware
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`corporation with its principal place of business at One Dell Way, Round Rock, Texas 78682.
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`6.
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`On information and belief, defendant Dell Inc. is a Delaware corporation with its
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`principal place of business at One Dell Way, Round Rock, Texas 78682. Dell. Inc. has additional
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`offices at 1404 Park Center Dr., Austin, Texas, 701 E. Parmer Lane, Bldg. PS2, Austin, Texas,
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`12500 Tech Ridge Road, Austin, Texas, 9715 Burnet Road, Austin, Texas, and 4309 Emma
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`Browning Avenue, Austin, Texas.
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`JURISDICTION AND VENUE
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`7.
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`This Court has jurisdiction over the subject matter of this action under 28 U.S.C.
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`§§ 1331 and 1338(a).
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`8.
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`This Court has personal jurisdiction over Dell pursuant to due process and/or the
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`Texas Long Arm Statute because Dell has committed and continues to commit acts of patent
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`infringement, including acts giving rise to this action, within the State of Texas and this District,
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`and because Dell recruits Texas residents, directly or through an intermediary located in this state,
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`for employment inside or outside this state. The Court’s exercise of jurisdiction over Dell would
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`not offend traditional notions of fair play and substantial justice because Dell has established
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`minimum contacts with the forum.
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`COMPLAINT
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`Case 6:20-cv-01042-ADA Document 1 Filed 11/11/20 Page 3 of 18
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`9.
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`Venue is proper in this judicial district pursuant to 28 U.S.C. §§ 1391 and 1400
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`because a substantial part of the events or omissions giving rise to the claims occurred in this
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`District, and Dell has committed acts of infringement and has a regular and established place of
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`business in this District.
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`10.
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`Dell has committed acts of infringement in this District, directly and/or through
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`intermediaries, by, among other things, making, using, offering to sell, selling, and/or importing
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`products and/or services that infringe the Asserted Patents, as alleged herein.
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`11.
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`Dell has a regular and established places of business in this District including a
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`shared corporate office at One Dell Way, Round Rock, Texas 78682. Dell is also registered to do
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`business in Texas.
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`CALTECH’S ASSERTED PATENTS
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`12.
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`On October 3, 2006, the United States Patent Office issued U.S. Patent No.
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`7,116,710, titled “Serial Concatenation of Interleaved Convolutional Codes Forming Turbo-Like
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`Codes” (the “’710 patent”). A true and correct copy of the ’710 patent is attached hereto as Exhibit
`
`A.
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`13.
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`On September 2, 2008, the United States Patent Office issued U.S. Patent No.
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`7,421,032, titled “Serial Concatenation of Interleaved Convolutional Codes Forming Turbo-Like
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`Codes” (the “’032 patent”). A true and correct copy of the ’032 patent is attached hereto as Exhibit
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`B. The ’032 patent is a continuation of the application that led to the ’710 patent.
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`14.
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`On March 29, 2011, the United States Patent Office issued U.S. Patent No.
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`7,916,781, titled “Serial Concatenation of Interleaved Convolutional Codes Forming Turbo-Like
`
`Codes” (the “’781 patent”). A true and correct copy of the ’781 patent is attached hereto as Exhibit
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`C. The ’781 patent is a continuation of the application that led to the ’032 patent, which is a
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`continuation of the application that led to the ’710 patent.
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`15.
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`The Asserted Patents identify Hui Jin, Aamod Khandekar, and Robert J. McEliece
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`as the inventors (the “Inventors”).
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`16.
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`Caltech is the owner of all right, title, and interest in and to each of the Asserted
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`Patents with full and exclusive right to bring suit to enforce the Asserted Patents, including the right
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`COMPLAINT
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`Case 6:20-cv-01042-ADA Document 1 Filed 11/11/20 Page 4 of 18
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`to recover for past damages and/or royalties prior to the expiration of the Asserted Patents on
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`August 18, 2020.
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`17.
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`The Asserted Patents are valid and enforceable.
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`BACKGROUND
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`Caltech’s IRA Code Patents
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`18.
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`The Asserted Patents disclose a seminal improvement to coding systems and
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`methods. The Asserted Patents introduce a new type of error correction codes, called “irregular
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`repeat and accumulate codes” (or “IRA codes”). The claimed methods and apparatuses are directed
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`to encoders and decoders. The claimed encoders generate an IRA codeword from message or
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`information bits reordering irregularly repeated instances of those bits in a randomized but known
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`way and performing other logical operations such as summing and accumulating bits. The claimed
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`decoders facilitate recovery of the message or information bits from the codewords even when the
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`codewords have been corrupted by noise such as the noise that is experienced when transmitting a
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`codeword over a wireless communications channel. These IRA codes are at least as effective at
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`correcting errors in transmissions as prior coding techniques, such as turbo codes, but use simpler
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`encoding and decoding circuitry and provide other technical and practical advantages, allowing for
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`improved transmission rates and performance. Indeed, the IRA codes disclosed in the Asserted
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`Patents enable a transmission rate close to the theoretical limit.
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`19.
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`The Asserted Patents implement these novel IRA codes using novel encoders and
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`decoders. The claims in the Asserted Patents enable a person of ordinary skill in the art to
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`implement IRA codes using simple circuitry, providing improved performance over prior art
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`encoders and decoders.
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`20.
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`In September 2000, the Inventors of the Asserted Patents published a paper
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`regarding their invention, titled “Irregular Repeat-Accumulate Codes” for the Second International
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`Conference on Turbo Codes attached hereto as Exhibit D. This paper has been widely cited by
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`experts in the field.
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`21.
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`The Inventors’ patents and publications describing IRA codes have been widely
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`recognized and cited by academics and experts in the field of digital communications for their
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`COMPLAINT
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`Case 6:20-cv-01042-ADA Document 1 Filed 11/11/20 Page 5 of 18
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`improvements over prior art error-correction codes. For example, a paper praising these IRA codes
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`was published in August 2004 by Aline Roumy, Souad Guemghar, Giuseppe Caire, and Sergio
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`Verdú in the IEEE Transactions on Information Theory. This paper, titled “Design Methods for
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`Irregular Repeat-Accumulate Codes,” and attached hereto as Exhibit E, states:
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`IRA codes are, in fact, special subclasses of both irregular LDPCs and
`irregular turbo codes. . . . IRA codes are an appealing choice because the
`encoder is extremely simple, their performance is quite competitive with
`that of turbo codes and LDPCs, and they can be decoded with a very-low-
`complexity iterative decoding scheme.
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`This paper also notes that, four years after publication of the Inventors’ September 2000 paper, the
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`Inventors were the only ones to propose a method to design IRA codes.
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`IEEE 802.11 Wi-Fi Standard
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`22.
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`The Institute of Electrical and Electronics Engineers (“IEEE”) has developed
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`standards for wireless communications over local area networks (also referred to as “Wi-Fi”). Wi-
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`Fi usage is widespread in modern electronic products, including smartphones, laptops, routers,
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`televisions, cameras, cars and other devices that have wireless connections.
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`23.
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`The IEEE standard upon which Wi-Fi is based is IEEE 802.11. The 802.11
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`standardization process began in the 1990s and the first version of 802.11 was referred to as IEEE
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`802.11-1997. In the following years, subsequent versions of the 802.11 standard were adopted.
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`24.
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`One of the key improvements to the 802.11n version of the standard involved a
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`“High Throughput (HT)” mode that is implemented using specific LDPC (Low-Density Parity
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`Check) error correction codes. The same LDPC error correction codes introduced in the 802.11n
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`version of the standard are also implemented in the subsequent 802.11ac version (finalized by IEEE
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`in 2013 and basis for Wi-Fi 5) and 802.11ax version (nearing finalization and basis for Wi-Fi 6) of
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`the standard. The LDPC codes specified by the 802.11n, 802.11ac, and 802.11ax standards may
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`be implemented using Caltech’s patented IRA/LDPC encoders and decoder technology.
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`Caltech’s Case Against Apple and Broadcom
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`25.
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`In May 2016, Caltech filed a patent infringement action against Apple and
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`Broadcom in the Central District of California involving the Asserted Patents. On January 29,
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`2020, a jury rendered a verdict finding that Apple’s and Broadcom’s Wi-Fi products infringed the
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`COMPLAINT
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`Asserted Patents and awarded Caltech over $1.1 billion in damages. Caltech v. Broadcom et al.,
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`No. 16-cv-3714-GW, Dkt. No. 2114 (C.D. Cal. Jan. 29, 2020).
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`26.
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`The trial followed over three years of litigation during which the Court dismissed
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`the vast majority of Apple’s and Broadcom’s defenses and counter-claims. For example, the Court
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`denied Apple’s and Broadcom’s motion for summary judgment seeking to invalidate Caltech’s ’781
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`Patent under 35 U.S.C. § 101, and granted Caltech’s motion for summary judgment of validity of
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`Caltech’s ’710 and ’032 Patents under 35 U.S.C. § 101. The Court also denied Apple and
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`Broadcom’s motions for summary judgment of non-infringement.
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`27.
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`In addition, Apple filed ten inter partes review (“IPRs”) petitions with the United
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`States Patent and Trademark Office’s Patent Trial and Appeal Board (“PTAB”) seeking to
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`invalidate Caltech’s patents, and the PTAB either denied institution or upheld the patentability of
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`the claims in all ten petitions.
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`Dell
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`28.
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`Dell manufactures, uses, imports, offers for sale, and/or sells Wi-Fi products that
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`incorporate IRA/LDPC encoders and/or decoders Asserted Patents (“Accused Products”). The
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`Accused Products include, but are not limited to, laptops (e.g., Latitude, Vostro, Inspiron, XPS, G-
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`Series, Rugged, Chromebook Enterprise, Education, and Alienware), desktops and all-in-ones (e.g.,
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`OptiPlex, Precision, Vostro, Inspiron, and XPS), tablets and 2-in-1s (e.g., XPS, Latitude, Inspiron,
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`Rugged, Chromebook Enterprise, and Education), workstations (e.g., Precision), and thin clients.
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`Upon information and belief, the Accused Products are compliant with the 802.11n, 802.11ac,
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`and/or 802.11ax standards and the LDPC codes defined in those standards.
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`COUNT I
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`Infringement of the ’710 Patent
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`29.
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`Caltech re-alleges and incorporates by reference the allegations of the preceding
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`paragraphs of this Complaint as if fully set forth herein.
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`30.
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`In violation of 35 U.S.C. § 271(a), Dell has infringed the ’710 patent by making,
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`using, selling, offering for sale, and/or importing into the United States, without authority, the
`
`COMPLAINT
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`Accused Products which practice each and every limitation of at least claim 20 of the ’710 patent.
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`Dell has infringed literally and/or under the doctrine of equivalents.
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`31.
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`Upon information and belief, the Accused Products comply with the 802.11n,
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`802.11ac, and/or 802.11ax standards and the 12 LDPC error correction codes defined in those
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`standards. In addition, upon information and belief, the Accused Products are implemented in a
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`manner that not only complies with the 802.11n, 802.11ac, and/or 802.11ax standards, but also
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`infringes the Asserted Patents.
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`32.
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`The 12 LDPC codes were originally defined in the 802.11n version of the standard
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`and include three 1/2 rate, three 2/3 rate, three 3/4 rate, and three 5/6 rate LDPC codes as shown in
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`Table 20-14 of the standard below.1
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`
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`
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`1 See IEEE 802.11n-2009 at §20.3.11.6.2 (emphasis added); see also 802.11-2012 at §
`20.3.11.7.2.
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`COMPLAINT
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`33.
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`On information and belief, the Accused Products encode information or message
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`bits using an LDPC encoder that supports the 12 LDPC codes defined in the standards. The LDPC
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`encoder encodes the information or message bits to generate a codeword as described in Section
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`20.3.11.6.3 of the 802.11n standard shown below:2
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`34.
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`On information and belief, the LDPC encoders in the Accused Products encode
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`
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`information or message bits in accordance with the 12 parity-check matrices defined in the 802.11n
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`standard. A parity-check matrix H for each of the 12 block sizes and code rates is defined in Tables
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`R.1 to R.3 of the 802.11n. The parity-check matrix for one of the 12 LDPC codes is shown below.3
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`* * *
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`35.
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`Each parity-check matrix includes a left-hand side that corresponds to information
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`or message bits, and a right-hand side that corresponds to parity bits. In the parity-check matrix
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`shown above, the left-hand side that corresponds to information or message bits includes columns
`
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`2 See IEEE 802.11n-2009 at §20.3.11.6.3(emphasis added); see also IEEE 802.11-2012 at §
`20.3.11.7.3.
`3 See IEEE 802.11n-2009 at Annex R, Table R.1; see also IEEE 802.11-2012 at Annex F, Table
`F-1.
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`
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`COMPLAINT
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`1-18, and the right-hand side that corresponds to the parity bits includes columns 19-24. The left-
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`hand side is structured in a way that corresponds to the use of irregular repetition, scrambling and
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`summing in the encoding process, while the right-hand side is structured in a way that corresponds
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`to using accumulation in the encoding process. Further, the left-hand side is structured in a way
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`that corresponds to the use of a low-density generator matrix for performing operations of irregular
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`repetition, scrambling and summing.
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`36.
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`On information and belief, the LDPC encoders in the Accused Products are
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`implemented in a manner that meets each and every limitation of claim 20 of the ’710 patent. The
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`LDPC encoders in the Accused Products are coders. The LDPC encoders in the Accused Products
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`include first coders which are low-density generator matrix coders and correspond to the left-hand
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`sides of the parity-check matrices. The first coders have an input configured to receive a stream of
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`bits (e.g., information or message bits). The first coders repeat the stream of bits irregularly and
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`scramble the repeated bits. The irregular repetition and scrambling that occurs in the LDPC
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`encoders in the Accused Products corresponds to the irregular repetition and scrambling depicted
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`in the left-hand sides of the parity-check matrices.
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`37.
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`On information and belief, the LDPC encoders in the Accused Products include
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`second coders which correspond to the right-hand sides of the parity-check matrices. The second
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`coders encode bits output from the first coder at a rate within 10% of one. The encoding of output
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`bits at a rate within 10% of one that occurs in the LDPC encoders in the Accused Products
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`corresponds to the accumulation depicted in the right-hand sides of the parity-check matrices.
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`38.
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`39.
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`40.
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`Dell is not licensed or otherwise authorized to practice the claims of the ’710 patent.
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`By reason of Dell’s infringement, Caltech has suffered substantial damages.
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`Caltech is entitled to recover the damages sustained as a result of Dell’s wrongful
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`acts in an amount subject to proof at trial.
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`41.
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`Dell’s infringement of the ’710 patent is exceptional and entitles Caltech to
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`attorneys’ fees and costs incurred in prosecuting this action under 35 U.S.C. § 285.
`
`COUNT II
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`Infringement of the ’032 Patent
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`COMPLAINT
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`42.
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`Caltech re-alleges and incorporates by reference the allegations of the preceding
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`paragraphs of this Complaint as if fully set forth herein.
`
`43.
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`In violation of 35 U.S.C. § 271(a), Dell has infringed the ’032 patent by making,
`
`using, selling, offering for sale, and/or importing into the United States, without authority, the
`
`Accused Products which practice each and every limitation of at least claim 11 of the ’032 patent.
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`Dell has infringed literally and/or under the doctrine of equivalents.
`
`44.
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`Upon information and belief, the Accused Products comply with the 802.11n,
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`802.11ac, and/or 802.11ax standards and the 12 LDPC error correction codes defined in those
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`standards. In addition, upon information and belief, the Accused Products are implemented in a
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`manner that not only complies with the 802.11n, 802.11ac, and/or 802.11ax standards, but also
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`infringes the Asserted Patents.
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`45.
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`The 12 LDPC codes were originally defined in the 802.11n version of the standard
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`and include three 1/2 rate, three 2/3 rate, three 3/4 rate, and three 5/6 rate LDPC codes as shown in
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`Table 20-14 of the standard below.4
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`
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`4 See IEEE 802.11n-2009 at §20.3.11.6.2 (emphasis added); see also 802.11-2012 at §
`20.3.11.7.2.
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`COMPLAINT
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`46.
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`On information and belief, the Accused Products encode information or message
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`bits using an LDPC encoder that supports the 12 LDPC codes defined in the standards. The LDPC
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`encoder encodes the information or message bits to generate a codeword as described in Section
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`20.3.11.6.3 of the 802.11n standard shown below:5
`
`
`
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`
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`5 See IEEE 802.11n-2009 at §20.3.11.6.3(emphasis added); see also IEEE 802.11-2012 at §
`20.3.11.7.3.
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`COMPLAINT
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`47.
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`On information and belief, the LDPC encoders in the Accused Products encode
`
`information or message bits in accordance with the 12 parity-check matrices defined in the 802.11n
`
`standard. A parity-check matrix H for each of the 12 block sizes and code rates is defined in Tables
`
`R.1 to R.3 of the 802.11n. The parity-check matrix for one of the 12 LDPC codes is shown below.6
`
`* * *
`
`
`
`
`
`
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`48.
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`Each parity-check matrix includes a left-hand side that corresponds to information
`
`or message bits, and a right-hand side that corresponds to parity bits. In the parity-check matrix
`
`shown above, the left-hand side that corresponds to information or message bits includes columns
`
`1-18, and the right-hand side that corresponds to the parity bits includes columns 19-24. The left-
`
`hand side is structured in a way that corresponds to the use of irregular repetition, scrambling and
`
`summing in the encoding process, while the right-hand side is structured in a way that corresponds
`
`to using accumulation in the encoding process. Further, the left-hand side is structured in a way
`
`that corresponds to the use of a low-density generator matrix for performing operations of irregular
`
`repetition, scrambling and summing.
`
`49.
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`A Tanner graph can be constructed from any parity-check matrix. A unique and
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`valuable characteristic of IRA codes is apparent in the Tanner graphs for IRA codes. For example,
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`when constructing a Tanner graph from the 12 LDPC parity-check matrices in the 802.11 standard,
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`message bits are repeated, different subsets of the information bits are repeated different numbers
`
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`6 See IEEE 802.11n-2009 at Annex R, Table R.1; see also IEEE 802.11-2012 at Annex F, Table
`F-1.
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`
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`COMPLAINT
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`Case 6:20-cv-01042-ADA Document 1 Filed 11/11/20 Page 13 of 18
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`of times, check nodes are connected to information bits in a random but known pattern, parity bits
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`are connected to check nodes which enforce a constraint that facilitates the determination of parity
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`bits. While this is not true for a generic LDPC code, it is true for the 12 LDPC codes in the 802.11
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`standard.
`
`50.
`
`On information and belief, the LDPC encoders in the Accused Products are
`
`implemented in a manner that meets each and every limitation of claim 11 of the ’032 patent. The
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`Accused Products are devices that include LDPC encoders. The LDPC encoders receive a
`
`collection of message bits and encode the message bits to generate a collection of parity bits. The
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`LDPC encoders in the Accused Products encode the collection of message bits in accordance with
`
`the Tanner graph depicted in claim 11. The Tanner graph depicted in claim 11 is a graph
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`representing an IRA code as a set of parity-checks where every message bit is repeated, at least two
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`different subsets of message bits are repeated a different number of times, and check nodes,
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`randomly connected to the repeated message bits, enforce constraints that determine the parity bits.
`
`51.
`
`52.
`
`53.
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`Dell is not licensed or otherwise authorized to practice the claims of the ’032 patent.
`
`By reason of Dell’s infringement, Caltech has suffered substantial damages.
`
`Caltech is entitled to recover the damages sustained as a result of Dell’s wrongful
`
`acts in an amount subject to proof at trial.
`
`54.
`
`Dell’s infringement of the ’032 patent is exceptional and entitles Caltech to
`
`attorneys’ fees and costs incurred in prosecuting this action under 35 U.S.C. § 285.
`
`COUNT III
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`Infringement of the ’781 Patent
`
`55.
`
`Caltech re-alleges and incorporates by reference the allegations of the preceding
`
`paragraphs of this Complaint as if fully set forth herein.
`
`56.
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`In violation of 35 U.S.C. § 271(a), Dell has infringed the ’781 patent through its use
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`and testing of the Dell Accused Products. Through its use and testing of the Dell Accused Products,
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`Dell performs each and every limitation of at least claim 13 of the ’781 patent. Dell has infringed
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`literally and/or under the doctrine of equivalents..
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`COMPLAINT
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`Case 6:20-cv-01042-ADA Document 1 Filed 11/11/20 Page 14 of 18
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`57.
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`Upon information and belief, the Accused Products comply with the 802.11n,
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`802.11ac, and/or 802.11ax standards and the 12 LDPC error correction codes defined in those
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`standards. In addition, upon information and belief, the Accused Products are implemented in a
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`manner that not only complies with the 802.11n, 802.11ac, and/or 802.11ax standards, but also
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`infringes the Asserted Patents.
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`58.
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`The 12 LDPC codes were originally defined in the 802.11n version of the standard
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`and include three 1/2 rate, three 2/3 rate, three 3/4 rate, and three 5/6 rate LDPC codes as shown in
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`Table 20-14 of the standard below.7
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`
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`59.
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`On information and belief, the Accused Products encode information or message
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`
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`bits using an LDPC encoder that supports the 12 LDPC codes defined in the standards. The LDPC
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`
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`7 See IEEE 802.11n-2009 at §20.3.11.6.2 (emphasis added); see also 802.11-2012 at §
`20.3.11.7.2.
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`COMPLAINT
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`Page | 14
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`Case 6:20-cv-01042-ADA Document 1 Filed 11/11/20 Page 15 of 18
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`encoder encodes the information or message bits to generate a codeword as described in Section
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`20.3.11.6.3 of the 802.11n standard shown below:8
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`60.
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`On information and belief, the LDPC encoders in the Accused Products encode
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`
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`information or message bits in accordance with the 12 parity-check matrices defined in the 802.11n
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`standard. A parity-check matrix H for each of the 12 block sizes and code rates is defined in Tables
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`R.1 to R.3 of the 802.11n. The parity-check matrix for one of the 12 LDPC codes is shown below.9
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`* * *
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`61.
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`Each parity-check matrix includes a left-hand side that corresponds to information
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`or message bits, and a right-hand side that corresponds to parity bits. In the parity-check matrix
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`shown above, the left-hand side that corresponds to information or message bits includes columns
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`1-18, and the right-hand side that corresponds to the parity bits includes columns 19-24. The left-
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`hand side is structured in a way that corresponds to the use of irregular repetition, scrambling and
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`8 See IEEE 802.11n-2009 at §20.3.11.6.3(emphasis added); see also IEEE 802.11-2012 at §
`20.3.11.7.3.
`9 See IEEE 802.11n-2009 at Annex R, Table R.1; see also IEEE 802.11-2012 at Annex F, Table
`F-1.
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`COMPLAINT
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`Case 6:20-cv-01042-ADA Document 1 Filed 11/11/20 Page 16 of 18
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`summing in the encoding process, while the right-hand side is structured in a way that corresponds
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`to using accumulation in the encoding process. Further, the left-hand side is structured in a way
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`that corresponds to the use of a low-density generator matrix for performing operations of irregular
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`repetition, scrambling and summing.
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`62.
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`On information and belief, the LDPC encoders in the Accused Products are
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`implemented in a manner that meets each and every limitation of claim 13 of the ’781 patent. The
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`LDPC encoders perform a method of encoding a signal. The LDPC encoders receive a block of
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`data in the signal to be encoded. The block of data includes information bits. The LDPC encoders
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`perform an encoding operation using the information bits as an input. The encoding operation
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`includes an accumulation of mod-2 or exclusive-OR sums of bits in subsets of the information bits.
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`The non-null values in each row in the left-hand side of the parity-check matrices correspond to the
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`subsets of information bits that are summed.10 The accumulation of the sums of bits in subsets of
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`the information bits corresponds to the accumulation operations depicted in the left-hand side of
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`the parity-check matrices.
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`63.
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`64.
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`65.
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`Dell is not licensed or otherwise authorized to practice the claims of the ’781 patent.
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`By reason of Dell’s infringement, Caltech has suffered substantial damages.
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`Caltech is entitled to recover the damages sustained as a result of Dell’s wrongful
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`acts in an amount subject to proof at trial.
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`66.
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`Dell’s infringement of the ’781 patent is exceptional and entitles Caltech to
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`attorneys’ fees and costs incurred in prosecuting this action under 35 U.S.C. § 285.
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`DEMAND FOR JURY TRIAL
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`Pursuant to Rule 38 of the Federal Rules of Civil Procedure, Plaintiff hereby demands a
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`trial by jury as to all issues so triable.
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`PRAYER FOR RELIEF
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`WHEREFORE, Plaintiff respectfully prays for the following relief:
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`
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`10 The null values are represented by “-” in the parity-check matrices. The non-null values are
`represented by numbers.
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`COMPLAINT
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`Page | 16
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`Case 6:20-cv-01042-ADA Document 1 Filed 11/11/20 Page 17 of 18
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`(a)
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`A judgment that Defendants have infringed each and every one of the Asserted
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`Patents;
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`(b)
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`Damages adequate to compensate Caltech for Defendants’ infringement of the
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`Asserted Patents pursuant to 35 U.S.C. § 284;
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`(c)
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`Prejudgment interest;
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`(d)
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`Post-judgment interest;
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`(e)
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`A declaration that this action is exceptional pursuant to 35 U.S.C. § 285, and an
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`award to Caltech of its attorneys’ fees, costs and expenses incurred in connection with this action;
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`and
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`(f)
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`Such other relief as the Court deems just and equitable.
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`COMPLAINT
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`Page | 17
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`Case 6:20-cv-01042-ADA Document 1 Filed 11/11/20 Page 18 of 18
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`
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`DATED: November 11, 2020
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`Respectfully submitted,
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`
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`
`
`COMPLAINT
`
`
`By /s/ J. Mark Mann
`J. Mark Mann
`State Bar No. 12926150
`mark@themannfirm.com
`G. Blake Thompson
`State Bar No. 24042033
`blake@themannfirm.com
`MANN TINDEL THOMPSON
`300 West Main Street
`Henderson, Texas 75652
`Telephone: (903) 657-8540
`Facsimile: (903) 657-6003
`
`James R. Asperger (pro hac vice pending)
`QUINN EMANUEL URQUHART & SULLIVAN, LLP
`865 S. Figueroa Street, 10th Floor
`Los Angeles, CA 90017-2543
`Telephone: (213) 443-3000
`Facsimile: (213) 443 3100
`jimasperger@quinnemanuel.com
`
`Kevin Johnson
`Todd Briggs (pro hac vice pending)
`QUINN EMANUEL URQUHART &
`SULLIVAN, LLP
`555 Twin Dolphin Drive, 5th Floor
`Redwood Shores, California 94065-2139
`Telephone: (650) 801 5000
`Facsimile: (650) 801 5100
`kevinjohnson@quinnemanuel.com
`toddbriggs@quinnemanuel.com
`
`Brian Biddinger (pro hac vice pending)
`QUINN EMANUEL URQUHART &
`SULLIVAN, LLP
`51 Madison Avenue, 22nd Floor
`New York, New York 10010-1601
`Telephone: (212) 849 7000
`Facsimile: (212) 849 7100
`brianbiddinger@quinnemanuel.com
`
`Attorneys for Plaintiff California Institute of Technology
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`Page | 18
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