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Inventors

Ziyad E. Hanna Per Anders M. Franzen Ross M. Weber Habeeb A. Farah Rajeev K. Ranjan

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FORMAL VERIFICATION COVERAGE METRICS FOR CIRCUIT DESIGN PROPERTIES

14/474,280 | U.S. Patent Application

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Filed Sept. 1, 2014

Examiner Brian Ngo

Class 716

Art Group 2851

Patent No. 9,177,089

Case Type Utility

Status Patented Case

Last Updated: 15 hours ago

Date	#	Transaction
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FORMAL VERIFICATION COVERAGE METRICS FOR CIRCUIT DESIGN PROPERTIES

14/474,280 | U.S. Patent Application

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