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KONINKLIJKE PHILIPS ELECTRONICS N V

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Andrei Radulescu Kees Gerard Goossens

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INTEGRATED CIRCUIT AND METHOD FOR BUFFERING TO OPTIMIZE BURST LENGTH IN NETWORKS ON CHIPS

11/569,083 | U.S. Patent Application

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Location ELECTRONIC

Filed Nov. 14, 2006

Examiner MICHAEL ALSIP

Class 711

Art Group 2186

Patent No. 8,086,800

Case Type Utility - 711/118000

Status Patented Case

Parent PCT/IB05/51580 -

Child 04102189.0

Last Updated: 2 years, 4 months ago

Date	#	Transaction
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INTEGRATED CIRCUIT AND METHOD FOR BUFFERING TO OPTIMIZE BURST LENGTH IN NETWORKS ON CHIPS

11/569,083 | U.S. Patent Application

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