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METHODS FOR DEFINING AND USING CO-OPTIMIZED NANOPATTERNS FOR INTEGRATED CIRCUIT DESIGN AND APPARATUS IMPLEMENTING SAME

12/484,130 | U.S. Patent Application

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Location ELECTRONIC
Filed June 12, 2009
Examiner LEIGH M GARBOWSKI
Class 716
Art Group 2825
Patent No. 8,245,180
Case Type Utility - 716/021000
Status Patented Case
Parent 61/75,711 Expired
Parent 12/13,342 Patented
Parent 60/963,364 Expired
Parent 60/972,394 Expired
Parent 12/212,562 Patented
Parent 11/683,402 Patented
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Last Updated: 6 years, 2 months ago
Date # Transaction