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INTEGRATED CIRCUIT AND ASSOCIATED LAYOUT WITH GATE ELECTRODE LEVEL PORTION INCLUDING AT LEAST TWO COMPLIMENTARY TRANSISTOR FORMING LINEAR CONDUCTIVE SEGMENTS AND AT LEAST ONE NON-GATE LINEAR CONDUCTIVE SEGMENT

12/561,229 | U.S. Patent Application

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Location ELECTRONIC
Filed Sept. 16, 2009
Examiner QUOC DINH HOANG
Class 257
Art Group 2892
Patent No. 7,943,966
Case Type Utility - 257/390000
Status Application Involved in Court Proceedings
Parent 12/212,562 Patented
Parent 11/683,402 Patented
Parent 60/781,288 Expired
Last Updated: 4 years, 11 months ago
Date # Transaction