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INTEGRATED CIRCUIT DEVICE WITH GATE LEVEL REGION INCLUDING AT LEAST THREE LINEAR-SHAPED CONDUCTIVE SEGMENTS HAVING OFFSET LINE ENDS AND FORMING THREE TRANSISTORS OF FIRST TYPE AND ONE TRANSISTOR OF SECOND TYPE

12/567,609 | U.S. Patent Application

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Location ELECTRONIC
Filed Sept. 25, 2009
Examiner QUOC DINH HOANG
Class 257
Art Group 2892
Patent No. 8,089,103
Case Type Utility - 257/206000
Status Patented Case
Parent 12/212,562 Patented
Parent 11/683,402 Patented
Parent 60/781,288 Expired
Last Updated: 3 years, 9 months ago
Date # Transaction