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METHODS OF FABRICATING AND CREATING LAYOUT FOR INTEGRATED CIRCUIT INCLUDING AT LEAST SIX LINEAR-SHAPED CONDUCTIVE STRUCTURES FORMING GATE ELECTRODES OF TRANSISTORS WITH AT LEAST TWO LINEAR-SHAPED CONDUCTIVE STRUCTURES OF DIFFERENT LENGTH

12/567,623 | U.S. Patent Application

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Location ELECTRONIC
Filed Sept. 25, 2009
Examiner QUOC DINH HOANG
Class 257
Art Group 2892
Patent No. 8,207,053
Case Type Utility - 257/390000
Status Patent Expired Due to NonPayment of Maintenance Fees Under 37 CFR 1.362
Parent 12/212,562 Patented
Parent 11/683,402 Patented
Parent 60/781,288 Expired
Last Updated: 1 year, 4 months ago
Date # Transaction