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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS WITH SHARED DIFFUSION REGIONS ON OPPOSITE SIDES OF TWO-TRANSISTOR-FORMING GATE LEVEL FEATURE

12/753,798 | U.S. Patent Application

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Location ELECTRONIC
Filed April 2, 2010
Examiner WENSING W KUO
Class 257
Art Group 2826
Patent No. 8,405,163
Case Type Utility - 257/393000
Status Patented Case
Parent 12/402,465 Patented
Parent 61/36,460 Expired
Parent 61/42,709 Expired
Parent 61/45,953 Expired
Parent 61/50,136 Expired
Child 13/741,305 Patented
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Last Updated: 6 years, 2 months ago
Date # Transaction