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INTEGRATED CIRCUIT INCLUDING CROSS-COUPLED TRANSISTORS HAVING GATE ELECTRODES FORMED WITHIN GATE LEVEL FEATURE LAYOUT CHANNELS

12/754,050 | U.S. Patent Application

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Location ELECTRONIC
Filed April 5, 2010
Examiner ORI NADAV
Class 257
Art Group 2811
Patent No. 8,729,606
Case Type Utility - 257/393000
Status Patent Expired Due to NonPayment of Maintenance Fees Under 37 CFR 1.362
Parent 12/402,465 Patented
Parent 61/36,460 Expired
Parent 61/42,709 Expired
Parent 61/45,953 Expired
Parent 61/50,136 Expired
Last Updated: 1 year, 4 months ago
Date # Transaction