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Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Shared Diffusion Regions on Opposite Sides of Two-Transistor-Forming Gate Level Feature

13/741,305 | U.S. Patent Application

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Location ELECTRONIC
Filed Jan. 14, 2013
Examiner WENSING W KUO
Class 257
Art Group 2826
Patent No. 8,872,283
Case Type Utility - 257/401000
Status Patented Case
Parent 12/753,798 Patented
Parent 12/402,465 Patented
Parent 61/36,460 Expired
Parent 61/42,709 Expired
Parent 61/45,953 Expired
Parent 61/50,136 Expired
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Last Updated: 6 years ago
Date # Transaction