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SEMICONDUCTOR CHIP INCLUDING A CHIP LEVEL BASED ON A LAYOUT THAT INCLUDES BOTH REGULAR AND IRREGULAR WIRES

13/898,155 | U.S. Patent Application

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Location ELECTRONIC
Filed May 20, 2013
Examiner VUTHE SIEK
Class 716
Art Group 2851
Patent No. 9,754,878
Case Type Utility - 716/055000
Status Patent Expired Due to NonPayment of Maintenance Fees Under 37 CFR 1.362
Parent 12/481,445 Patented
Parent 61/60,090 Expired
Parent 12/13,342 Patented
Parent 60/963,364 Expired
Parent 60/972,394 Expired
Parent 12/212,562 Patented
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Last Updated: 1 year, 6 months ago
Date # Transaction