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SEMICONDUCTOR CHIP INCLUDING REGION HAVING CROSS-COUPLED TRANSISTOR CONFIGURATION WITH OFFSET ELECTRICAL CONNECTION AREAS ON GATE ELECTRODE FORMING CONDUCTIVE STRUCTURES AND AT LEAST TWO DIFFERENT INNER EXTENSION DISTANCES OF GATE ELECTRODE FORMING CONDUCTIVE STRUC

14/273,483 | U.S. Patent Application

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Location ELECTRONIC
Filed May 8, 2014
Examiner WENSING W KUO
Class 257
Art Group 2826
Patent No. 8,847,331
Case Type Utility - 257/401000
Status Patented Case
Parent 13/741,305 Patented
Parent 12/753,798 Patented
Parent 12/402,465 Patented
Parent 61/36,460 Expired
Parent 61/42,709 Expired
Parent 61/45,953 Expired
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Last Updated: 6 years, 6 months ago
Date # Transaction