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Inventors

MIKAKO MIYAMA GOICHI YOKOMIZO CHIKAKO YOSHIDA

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HITACHI, LTD., A CORP OF JAPAN

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CIRCUIT SIMULATION METHOD FOR A CIRCUIT REALIZED BY AN LSI LAYOUT PATTERN BASED UPON A CIRCUIT OF A LOGIC GATE LEVEL REALIZED BY THE LAYOUT PATTERN

07/577,434 | U.S. Patent Application

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Location FILE REPOSITORY (FRANCONIA)

Filed Sept. 4, 1990

Examiner VINCENT N TRANS

Class 364

Art Group 2304

Patent No. 5,416,717

Case Type Utility - 364/488000

Status Patent Expired Due to NonPayment of Maintenance Fees Under 37 CFR 1.362

Child 01-229150

Child 01-237050

Last Updated: 4 years, 11 months ago

Date	#	Transaction
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CIRCUIT SIMULATION METHOD FOR A CIRCUIT REALIZED BY AN LSI LAYOUT PATTERN BASED UPON A CIRCUIT OF A LOGIC GATE LEVEL REALIZED BY THE LAYOUT PATTERN

07/577,434 | U.S. Patent Application

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