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Inventor

KAZUKI ASAO

Assignee

NEC ELECTRONICS CORPORATION

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NEC CORPORATION, Assignor RENESAS ELECTRONICS CORPORATION, Assignor

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METHOD OF CALCULATING A PARASITIC LOAD IN A SEMICONDUCTOR INTEGRATED CIRCUIT

08/688,736 | U.S. Patent Application

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Location FILE REPOSITORY (FRANCONIA)

Filed July 31, 1996

Examiner ANDREW S ROBERTS

Class 364

Art Group 2763

Patent No. 5,847,967

Case Type Utility - 364/489000

Status Patented Case

Child 195046/1995

Last Updated: 4 years, 6 months ago

Date	#	Transaction
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METHOD OF CALCULATING A PARASITIC LOAD IN A SEMICONDUCTOR INTEGRATED CIRCUIT

08/688,736 | U.S. Patent Application

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