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Displaying 144-158 of
819 results
CIRCUIT CONFIGURATION HAVING A FLOW CONTROLLER, INTEGRATED MEMO...
Docket
10/446,995,
U.S. Patent Application
(May 27, 2003)
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METHOD FOR CHECKING THE REFRESH FUNCTION OF AN INFORMATION MEM...
Docket
10/607,518,
U.S. Patent Application
(June 26, 2003)
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Cite Docket
TEST CIRCUIT AND METHOD FOR TESTING AN INTEGRATED MEMORY CIRCUIT
Docket
10/613,367,
U.S. Patent Application
(July 3, 2003)
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Cite Docket
SEMICONDUCTOR CONFIGURATION AND PROCESS FOR ETCHING A LAYER O...
Docket
10/454,518,
U.S. Patent Application
(June 4, 2003)
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Cite Docket
SEMICONDUCTOR PRODUCT CONTAINER AND SYSTEM FOR HANDLING A SEM...
Docket
10/601,639,
U.S. Patent Application
(June 23, 2003)
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Cite Docket
CIRCUIT CONFIGURATION FOR DRIVING A PROGRAMMABLE LINK
Docket
10/600,911,
U.S. Patent Application
(June 20, 2003)
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Cite Docket
METHOD FOR CLASSIFYING ERRORS IN THE LAYOUT OF A SEMICONDUCTOR...
Docket
10/447,386,
U.S. Patent Application
(May 29, 2003)
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Cite Docket
CIRCUIT CONFIGURATION FOR SETTING THE INPUT RESISTANCE AND THE INP...
Docket
10/452,477,
U.S. Patent Application
(June 2, 2003)
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Cite Docket
INTEGRATED CIRCUIT WITH VOLTAGE DIVIDER AND BUFFERED CAPACITOR
Docket
10/460,714,
U.S. Patent Application
(June 12, 2003)
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Cite Docket
CIRCUIT FOR NON-DESTRUCTIVE, SELF-NORMALIZING READING-OUT OF MRA...
Docket
10/447,358,
U.S. Patent Application
(May 29, 2003)
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Cite Docket
METHOD FOR INCREASING THE INPUT VOLTAGE OF AN INTEGRATED CIRCUIT...
Docket
10/600,961,
U.S. Patent Application
(June 20, 2003)
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Cite Docket
CIRCUIT CONFIGURATION FOR DRIVING A PROGRAMMABLE LINK
Docket
10/601,236,
U.S. Patent Application
(June 20, 2003)
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Cite Docket
METHOD FOR PATTERNING A LAYER OF SILICON, AND METHOD FOR FABRICA...
Docket
10/462,512,
U.S. Patent Application
(June 16, 2003)
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Cite Docket
METHOD AND AUXILIARY DEVICE FOR TESTING A RAM MEMORY CIRCUIT
Docket
10/429,579,
U.S. Patent Application
(May 5, 2003)
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Cite Docket
RAM MEMORY CIRCUIT AND METHOD FOR CONTROLLING THE SAME
Docket
10/425,280,
U.S. Patent Application
(April 29, 2003)
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Cite Docket
