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Displaying 159-173 of
819 results
METHOD FOR ELIMINATING PHASE CONFLICT CENTERS IN ALTERNATING PHA...
Docket
10/455,764,
U.S. Patent Application
(June 5, 2003)
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Cite Docket
INSTALLATION FOR PROCESSING A SEMICONDUCTOR WAFER AND METHOD F...
Docket
10/401,185,
U.S. Patent Application
(March 27, 2003)
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Cite Docket
MEMORY CIRCUIT, METHOD FOR MANUFACTURING AND METHOD FOR OPERA...
Docket
10/431,422,
U.S. Patent Application
(May 7, 2003)
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Cite Docket
PHOTOLITHOGRAPHIC MASK AND METHODS FOR PRODUCING A STRUCTURE...
Docket
10/438,370,
U.S. Patent Application
(May 14, 2003)
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Cite Docket
SEMICONDUCTOR MEMORY CELL AND SEMICONDUCTOR MEMORY DEVICE
Docket
10/395,457,
U.S. Patent Application
(March 24, 2003)
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Cite Docket
SEMICONDUCTOR CIRCUIT AND INITIALIZATION METHOD
Docket
10/419,596,
U.S. Patent Application
(April 21, 2003)
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Cite Docket
MEMORY MODULE WITH TEST STRUCTURE
Docket
10/452,482,
U.S. Patent Application
(June 2, 2003)
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Cite Docket
INTEGRATED MEMORY USING PREFETCH ARCHITECTURE AND METHOD FOR O...
Docket
10/446,601,
U.S. Patent Application
(May 28, 2003)
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Cite Docket
CIRCUIT CONFIGURATION FOR GENERATING A CONTROLLABLE OUTPUT VOL...
Docket
10/438,362,
U.S. Patent Application
(May 14, 2003)
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Cite Docket
PHOTOLITHOGRAPHIC MASK HAVING A STRUCTURE REGION COVERED BY A...
Docket
10/442,739,
U.S. Patent Application
(May 21, 2003)
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Cite Docket
METHOD FOR FABRICATING A PATTERNED LAYER ON A SEMICONDUCTOR SU...
Docket
10/424,507,
U.S. Patent Application
(April 28, 2003)
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Cite Docket
METHOD AND CONFIGURATION FOR REINFORCEMENT OF A DIELECTRIC LAYE...
Docket
10/413,812,
U.S. Patent Application
(April 15, 2003)
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Cite Docket
PROCESS FOR PRODUCING HARD MASKS
Docket
10/425,233,
U.S. Patent Application
(April 29, 2003)
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Cite Docket
METHOD FOR NUMERICALLY SIMULATING AN ELECTRICAL CIRCUIT
Docket
10/422,580,
U.S. Patent Application
(April 24, 2003)
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Cite Docket
