- All Courts
- Federal Courts
- Bankruptcies
- PTAB
- ITC
Filters
Like full text docket searches?
Get docket alerts, perform legal research, get updates of major decisions and orders, use our advanced analytics, and more. Request a Demo or create your account.
Date Filed
Dollars
Find cases based on dollar amount with searches like:
$100k-$10M.
Read the details here.
Displaying 24-38 of
819 results
1-18-US-106215350IP1
Document
METHOD FOR CORRECTING LOCAL LOADING EFFECTS IN THE ETCHING OF PHOTOMASKS, 10/621,535, No. 1-18-US-106215350IP1 (U.S. Pat. App. Jul. 26, 2017)
|
|
Cite Document
1-18-US-1067576109P1
Document
INTEGRATED SEMICONDUCTOR CIRCUIT CONFIGURATION, 10/675,761, No. 1-18-US-1067576109P1 (U.S. Pat. App. Jul. 26, 2017)
|
|
Cite Document
1-18-US-104524770JP1
Document
CIRCUIT CONFIGURATION FOR SETTING THE INPUT RESISTANCE AND THE INPUT CAPACITANCE OF AN INTEGRATED SEMICONDUCTOR CIRCUIT CHIP, 10/452,477, No. 1-18-US-104524...
|
|
Cite Document
1-18-US-104291580BP1
Document
STORAGE CIRCUIT, 10/429,158, No. 1-18-US-104291580BP1 (U.S. Pat. App. Jul. 26, 2017)
|
|
Cite Document
1-18-US-106596930AP1
Document
SYNCHRONIZATION DEVICE FOR A SEMICONDUCTOR MEMORY DEVICE, 10/659,693, No. 1-18-US-106596930AP1 (U.S. Pat. App. Jul. 26, 2017)
|
|
Cite Document
1-18-US-106094550BP1
Document
CONFIGURATION FOR TESTING SEMICONDUCTOR DEVICES, 10/609,455, No. 1-18-US-106094550BP1 (U.S. Pat. App. Jul. 26, 2017)
|
|
Cite Document
1-18-US-104243760MP1
Document
METHODS FOR PRODUCING A DIELECTRIC, DIELECTRIC HAVING SELF-GENERATING PORES, MONOMER FOR POROUS DIELECTRICS, PROCESS FOR PREPARING POLY-O-HYDROXY...
|
|
Cite Document
1-18-US-106535370EP1
Document
MASK FOR PROJECTING A STRUCTURE PATTERN ONTO A SEMICONDUCTOR SUBSTRATE, 10/653,537, No. 1-18-US-106535370EP1 (U.S. Pat. App. Jul. 26, 2017)
|
|
Cite Document
1-18-US-104148370BP1
Document
SEMICONDUCTOR ASSEMBLY WITH A SEMICONDUCTOR MODULE, 10/414,837, No. 1-18-US-104148370BP1 (U.S. Pat. App. Jul. 26, 2017)
|
|
Cite Document
1-18-US-106098730FP1
Document
METHOD, ADAPTER CARD AND CONFIGURATION FOR AN INSTALLATION OF MEMORY MODULES, 10/609,873, No. 1-18-US-106098730FP1 (U.S. Pat. App. Jul. 26, 2017)
|
|
Cite Document
1-18-US-106075180FP1
Document
METHOD FOR CHECKING THE REFRESH FUNCTION OF AN INFORMATION MEMORY, 10/607,518, No. 1-18-US-106075180FP1 (U.S. Pat. App. Jul. 26, 2017)
|
|
Cite Document
1-18-US-104607150GP1
Document
ZIPPER CONNECTOR, 10/460,715, No. 1-18-US-104607150GP1 (U.S. Pat. App. Jul. 26, 2017)
|
|
Cite Document
1-18-US-106269570BP1
Document
SEMICONDUCTOR CIRCUIT STRUCTURE AND METHOD FOR FABRICATING THE SEMICONDUCTOR CIRCUIT STRUCTURE, 10/626,957, No. 1-18-US-106269570BP1 (U.S. Pat. App. Jul. 26, 2...
|
|
Cite Document
1-18-US-106269550BP1
Document
INTEGRATED SYNCHRONOUS MEMORY AND MEMORY CONFIGURATION HAVING A MEMORY MODULE WITH AT LEAST ONE SYNCHRONOUS MEMORY, 10/626,955, No. 1-18-US-106269...
|
|
Cite Document
1-18-US-106739640JP1
Document
PHOTOSENSITIVE COATING MATERIAL FOR A SUBSTRATE AND PROCESS FOR EXPOSING THE COATED SUBSTRATE, 10/673,964, No. 1-18-US-106739640JP1 (U.S. Pat. App. Jul. 26, 20...
|
|
Cite Document
