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METHOD FOR PATTERNING A LAYER OF SILICON, AND METHOD FOR FABRICATING AN INTEGRATED SEMICONDUCTOR CIRCUIT, 10/462,512, No. 1-18-US-104625120FP1 (U.S. Pat. App. Jul. 26, 2017)
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INTEGRATED MEMORY USING PREFETCH ARCHITECTURE AND METHOD FOR OPERATING AN INTEGRATED MEMORY, 10/446,601, No. 1-18-US-1044660108P1 (U.S. Pat. App. Jul. 26, 2017)
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INTEGRATED MEMORY AND METHOD FOR CHECKING THE FUNCTIONING OF AN INTEGRATED MEMORY, 10/633,996, No. 1-18-US-106339960CP1 (U.S. Pat. App. Jul. 26, 2017)
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TEST CIRCUIT AND METHOD FOR TESTING AN INTEGRATED MEMORY CIRCUIT, 10/613,367, No. 1-18-US-106133670IP1 (U.S. Pat. App. Jul. 26, 2017)
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TEST DEVICE, TEST SYSTEM AND METHOD FOR TESTING A MEMORY CIRCUIT, 10/452,485, No. 1-18-US-104524850FP1 (U.S. Pat. App. Jul. 26, 2017)
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INTEGRATED MEMORY AND METHOD FOR TESTING THE MEMORY, 10/619,157, No. 1-18-US-106191570CP1 (U.S. Pat. App. Jul. 26, 2017)
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CIRCUIT CONFIGURATION FOR READING OUT A PROGRAMMABLE LINK, 10/627,841, No. 1-18-US-1062784109P1 (U.S. Pat. App. Jul. 26, 2017)
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METHOD AND APPARATUS FOR INTERNALLY TRIMMING OUTPUT DRIVERS AND TERMINATIONS IN SEMICONDUCTOR DEVICES, 10/680,782, No. 1-31-US-106807820FP1 (U.S. Pat. App. ...
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METHOD AND APPARATUS FOR INTERNALLY TRIMMING OUTPUT DRIVERS AND TERMINATIONS IN SEMICONDUCTOR DEVICES, 10/680,782, No. 1-31-US-106807820FP1 (U.S. Pat. App. Jun. 23, 2017)
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METHOD FOR CLASSIFYING ERRORS IN THE LAYOUT OF A SEMICONDUCTOR CIRCUIT, 10/447,386, No. 1-18-US-104473860PP1 (U.S. Pat. App. Jul. 26, 2017)
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MEMORY CIRCUIT AND METHOD FOR READING OUT DATA, 10/676,596, No. 1-18-US-1067659609P1 (U.S. Pat. App. Jul. 26, 2017)
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REFLECTIVE MIRROR FOR LITHOGRAPHIC EXPOSURE AND PRODUCTION METHOD, 10/632,752, No. 1-18-US-106327520VP1 (U.S. Pat. App. Jul. 26, 2017)
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ELECTRONIC PRINTED CIRCUIT BOARD HAVING A PLURALITY OF IDENTICALLY DESIGNED, HOUSING-ENCAPSULATED SEMICONDUCTOR MEMORIES, 10/187,763, No. 1-2-US-1018776...
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ELECTRONIC PRINTED CIRCUIT BOARD HAVING A PLURALITY OF IDENTICALLY DESIGNED, HOUSING-ENCAPSULATED SEMICONDUCTOR MEMORIES, 10/187,763, No. 1-2-US-101877630GP1 (U.S. Pat. App. Sep. 12, 2016)
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ELECTRONIC PRINTED CIRCUIT BOARD HAVING A PLURALITY OF IDENTICALLY DESIGNED, HOUSING-ENCAPSULATED SEMICONDUCTOR MEMORIES, 10/187,763, No. 1-24-US-101877...
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ELECTRONIC PRINTED CIRCUIT BOARD HAVING A PLURALITY OF IDENTICALLY DESIGNED, HOUSING-ENCAPSULATED SEMICONDUCTOR MEMORIES, 10/187,763, No. 1-24-US-101877630HP1 (U.S. Pat. App. Feb. 15, 2017)
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ELECTRONIC PRINTED CIRCUIT BOARD HAVING A PLURALITY OF IDENTICALLY DESIGNED, HOUSING-ENCAPSULATED SEMICONDUCTOR MEMORIES, 10/187,763, No. 1-2-US-1018776...
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ELECTRONIC PRINTED CIRCUIT BOARD HAVING A PLURALITY OF IDENTICALLY DESIGNED, HOUSING-ENCAPSULATED SEMICONDUCTOR MEMORIES, 10/187,763, No. 1-2-US-101877630EP1 (U.S. Pat. App. May. 9, 2016)
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ELECTRONIC PRINTED CIRCUIT BOARD HAVING A PLURALITY OF IDENTICALLY DESIGNED, HOUSING-ENCAPSULATED SEMICONDUCTOR MEMORIES, 10/187,763, No. 3-2-US-1018776...
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ELECTRONIC PRINTED CIRCUIT BOARD HAVING A PLURALITY OF IDENTICALLY DESIGNED, HOUSING-ENCAPSULATED SEMICONDUCTOR MEMORIES, 10/187,763, No. 3-2-US-101877630GP1 (U.S. Pat. App. Sep. 12, 2016)
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