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Displaying 609-623 of 819 results

Integrated memory and method for checking the operation of memory cells in an int...

Docket 09/826,233, U.S. Patent Application (April 4, 2001)

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Circuit configuration for generating a reference voltage for reading a ferroelectric m...

Docket 09/817,578, U.S. Patent Application (March 26, 2001)

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CIRCUIT CONFIGURATION FOR READING A MEMORY CELL HAVING A FERROE...

Docket 09/838,750, U.S. Patent Application (April 19, 2001)

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SEMICONDUCTOR MEMORY HAVING A MEMORY CELL ARRAY

Docket 09/820,234, U.S. Patent Application (March 28, 2001)

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SUBSTRATE ASSEMBLY HAVING A DEPRESSION SUITABLE FOR AN INTEGRAT...

Docket 09/821,853, U.S. Patent Application (March 30, 2001)

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TEST CONFIGURATION FOR THE FUNCTIONAL TESTING OF A SEMICONDUCTO...

Docket 09/826,594, U.S. Patent Application (April 5, 2001)

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ELECTRONIC DEVICE HAVING A MULTIPLICITY OF CONTACT BUMPS

Docket 09/816,928, U.S. Patent Application (March 23, 2001)

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Magnetoresistive memory having elevated interference immunity

Docket 09/821,964, U.S. Patent Application (March 30, 2001)

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Integrated memory having a differential sense amplifier

Docket 09/820,235, U.S. Patent Application (March 28, 2001)

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HOUSING FOR SEMICONDUCTOR CHIPS

Docket 09/832,246, U.S. Patent Application (April 10, 2001)

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MAGNETORESISTIVE ELEMENT AND USE THEREOF AS A MEMORY ELEMENT ...

Docket 09/801,210, U.S. Patent Application (March 7, 2001)

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TEST STRUCTURE IN AN INTEGRATED SEMICONDUCTOR

Docket 09/793,353, U.S. Patent Application (Feb. 26, 2001)

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READ/WRITE AMPLIFIER HAVING VERTICAL TRANSISTORS FOR A DRAM MEMO...

Docket 09/796,207, U.S. Patent Application (Feb. 28, 2001)

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METHOD FOR READING NONVOLATILE SEMICONDUCTOR MEMORY CONFIGU...

Docket 09/805,297, U.S. Patent Application (March 13, 2001)

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SELECTIVELY DEACTIVATING A FIRST CONTROL LOOP IN A DUAL CONTROL L...

Docket 09/811,881, U.S. Patent Application (March 19, 2001)

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