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Displaying 654-668 of 819 results

METHOD FOR FABRICATING A FIELD-EFFECT TRANSISTOR HAVING AN ANTI-P...

Docket 09/726,960, U.S. Patent Application (Nov. 30, 2000)

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CONFIGURATION FOR TESTING CHIPS USING A PRINTED CIRCUIT BOARD

Docket 09/745,567, U.S. Patent Application (Dec. 21, 2000)

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CIRCUIT FOR DETERMINING THE TIME DIFFERENCE BETWEEN EDGES OF A FIR...

Docket 09/756,084, U.S. Patent Application (Jan. 8, 2001)

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CONFIGURATION FOR TRIMMING REFERENCE VOLTAGES IN SEMICONDUCTO...

Docket 09/737,057, U.S. Patent Application (Dec. 14, 2000)

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METHOD OF PRODUCING A SEMICONDUCTOR DEVICE COMPRISING A CLEAN...

Docket 09/737,056, U.S. Patent Application (Dec. 14, 2000)

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STORAGE CAPACITOR FOR A DRAM

Docket 09/734,466, U.S. Patent Application (Dec. 11, 2000)

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CONFIGURATION FOR MEASUREMENT OF INTERNAL VOLTAGES OF AN INTEG...

Docket 09/740,633, U.S. Patent Application (Dec. 18, 2000)

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SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME

Docket 09/708,279, U.S. Patent Application (Nov. 8, 2000)

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Method for carrying out auto refresh sequences on a DRAM

Docket 09/716,871, U.S. Patent Application (Nov. 20, 2000)

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Integrated dynamic semiconductor memory having redundant units of memory cells...

Docket 09/677,357, U.S. Patent Application (Oct. 2, 2000)

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STANDBY VOLTAGE CONTROLLER AND VOLTAGE DIVIDER IN A CONFIGURAT...

Docket 09/716,901, U.S. Patent Application (Nov. 20, 2000)

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Integrated memory

Docket 09/699,982, U.S. Patent Application (Oct. 30, 2000)

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controlling transistor threshold potentials using substrate potentials

Docket 09/693,769, U.S. Patent Application (Oct. 20, 2000)

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Segmented word line architecture for dividing up a word line into a plurality of banks...

Docket 09/663,583, U.S. Patent Application (Sept. 18, 2000)

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INTEGRATED MEMORY HAVING MEMORY CELLS AND REFERENCE CELLS

Docket 09/718,937, U.S. Patent Application (Nov. 22, 2000)

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