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Displaying 669-683 of 819 results

INTEGRATED CIRCUIT CONFIGURATION WITH AT LEAST ONE CAPACITOR AND...

Docket 09/677,433, U.S. Patent Application (Oct. 2, 2000)

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CONFIGURATION AND METHOD FOR CONNECTING CONDUCTOR TRACKS

Docket 09/685,659, U.S. Patent Application (Oct. 10, 2000)

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Integrated memory having cells of the two-transistor/two-capacitor type

Docket 09/699,983, U.S. Patent Application (Oct. 30, 2000)

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METHOD FOR PRODUCING AN ELECTRICAL CONNECTION BETWEEN THE FRO...

Docket 09/658,713, U.S. Patent Application (Sept. 11, 2000)

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Integrated memory with at least two plate segments

Docket 09/662,257, U.S. Patent Application (Sept. 14, 2000)

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Integrated memory with two burst operation types

Docket 09/662,255, U.S. Patent Application (Sept. 14, 2000)

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DEPOSITION OF VARIOUS BASE LAYERS FOR SELECTIVE LAYER GROWTH IN...

Docket 09/666,526, U.S. Patent Application (Sept. 18, 2000)

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CONFIGURATION FOR VOLTAGE BUFFERING IN A DYNAMIC MEMORY USING C...

Docket 09/671,452, U.S. Patent Application (Sept. 27, 2000)

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Memory cell configuration and method for fabricating it

Docket 09/668,485, U.S. Patent Application (Sept. 25, 2000)

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PATTERNING OF CONTACT AREAS IN MULTILAYER METALIZATION CONFIGUR...

Docket 09/663,569, U.S. Patent Application (Sept. 15, 2000)

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Epitaxy layer and method for its production

Docket 09/651,492, U.S. Patent Application (Aug. 30, 2000)

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Integrated memory

Docket 09/618,124, U.S. Patent Application (July 17, 2000)

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Test circuit for testing a digital semiconductor circuit configuration

Docket 09/642,734, U.S. Patent Application (Aug. 17, 2000)

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CONFIGURATION AND METHOD FOR PRODUCING TEST SIGNALS FOR TESTING...

Docket 09/642,326, U.S. Patent Application (Aug. 21, 2000)

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METHOD FOR FABRICATING A MEMORY CELL HAVING A MOS TRANSISTOR

Docket 09/642,328, U.S. Patent Application (Aug. 21, 2000)

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