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Displaying 54-68 of
819 results
1-11-US-0979378902P1
Document
METHOD OF REPAIRING DEFECTIVE MEMORY CELLS OF AN INTEGRATED MEMORY, 09/793,789, No. 1-11-US-0979378902P1 (U.S. Pat. App. Aug. 7, 2015)
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1-11-US-0982201902P1
Document
MAGNETORESISTIVE MEMORY WITH A LOW CURRENT DENSITY, 09/822,019, No. 1-11-US-0982201902P1 (U.S. Pat. App. Aug. 7, 2015)
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1-11-US-0975196102P1
Document
METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS, 09/751,961, No. 1-11-US-0975196102P1 (U.S. Pat. App. Aug. 7, 2015)
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1-11-US-0980121002P1
Document
MAGNETORESISTIVE ELEMENT AND USE THEREOF AS A MEMORY ELEMENT IN A MEMORY CELL CONFIGURATION, 09/801,210, No. 1-11-US-0980121002P1 (U.S. Pat. App. Aug. 7, 2015...
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1-11-US-0982023502P1
Document
Integrated memory having a differential sense amplifier, 09/820,235, No. 1-11-US-0982023502P1 (U.S. Pat. App. Aug. 7, 2015)
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1-11-US-0977167508P1
Document
INTEGRATED COMPONENT, COMPOSITE ELEMENT COMPRISING AN INTEGRATED COMPONENT AND A CONDUCTOR STRUCTURE, CHIP CARD, AND METHOD OF PRODUCING THE INTE...
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1-11-US-0981188103P1
Document
SELECTIVELY DEACTIVATING A FIRST CONTROL LOOP IN A DUAL CONTROL LOOP CIRCUIT DURING DATA TRANSMISSION, 09/811,881, No. 1-11-US-0981188103P1 (U.S. Pat. App. Aug...
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1-11-US-0976180102P1
Document
MEMORY CELL CONFIGURATION IN WHICH AN ELECTRICAL RESISTANCE OF A MEMORY ELEMENT REPRESENTS AN INFORMATION ITEM AND CAN BE INFLUENCED BY A MAGNETIC FI...
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PLACEMENT SYSTEM FOR POPULATING A SUBSTRATE WITH ELECTRONIC CO...
Docket
11/348,762,
U.S. Patent Application
(Feb. 7, 2006)
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METHOD OF PRODUCING AN ELECTRONIC COMPONENT
Docket
11/30,799,
U.S. Patent Application
(Jan. 7, 2005)
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METHOD OF PRODUCING AN ELECTRONIC COMPONENT AND A PANEL WITH A...
Docket
10/989,650,
U.S. Patent Application
(Nov. 16, 2004)
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METHOD FOR PRODUCING AN ELECTRONIC DEVICE CONNECTED TO A PRINTE...
Docket
11/8,081,
U.S. Patent Application
(Dec. 9, 2004)
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ELECTRONIC COMPONENT WITH FLEXIBLE CONTACTING PADS AND METHOD...
Docket
10/963,434,
U.S. Patent Application
(Oct. 12, 2004)
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METHOD FOR DETERMINING THE OPTIMUM ACCESS STRATEGY
Docket
10/717,337,
U.S. Patent Application
(Nov. 19, 2003)
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METHOD FOR ALIGNING AND EXPOSING A SEMICONDUCTOR WAFER
Docket
10/686,848,
U.S. Patent Application
(Oct. 16, 2003)
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