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Displaying 804-818 of 819 results

1-1-US-101908140AP1

Document EVALUATION CIRCUIT FOR A DRAM, 10/190,814, No. 1-1-US-101908140AP1 (U.S. Pat. App. Dec. 20, 2004)

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1-1-US-099624110CP1

Document INTEGRATED MEMORY HAVING MEMORY CELLS AND REFERENCE CELLS, AND OPERATING METHOD FOR SUCH A MEMORY, 09/962,411, No. 1-1-US-099624110CP1 (U.S. Pat. App. Jan...

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1-1-US-102988340DP1

Document VERTICAL TRANSISTOR AND TRANSISTOR FABRICATION METHOD, 10/298,834, No. 1-1-US-102988340DP1 (U.S. Pat. App. Dec. 17, 2004)

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1-1-US-103954570DP1

Document SEMICONDUCTOR MEMORY CELL AND SEMICONDUCTOR MEMORY DEVICE, 10/395,457, No. 1-1-US-103954570DP1 (U.S. Pat. App. Dec. 16, 2004)

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1-1-US-101966980EP1

Document PROCESS FOR DEPOSITING WSIX LAYERS ON A HIGH TOPOGRAPHY WITH A DEFINED STOICHIOMETRY, 10/196,698, No. 1-1-US-101966980EP1 (U.S. Pat. App. Dec. 16, 2004)

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1-1-US-102848060CP1

Document METHOD AND APPARATUS FOR REFRESHING MEMORY CELLS, 10/284,806, No. 1-1-US-102848060CP1 (U.S. Pat. App. Dec. 17, 2004)

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1-1-US-102340790AP1

Document APPARATUS FOR MEASURING PARASITIC CAPACITANCES ON AN INTEGRATED CIRCUIT, 10/234,079, No. 1-1-US-102340790AP1 (U.S. Pat. App. Dec. 20, 2004)

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1-3-US-099304090DP1

Document SEMICONDUCTOR STRUCTURE HAVING AN INTERCONNECT AND METHOD OF PRODUCING THE SEMICONDUCTOR STRUCTURE, 09/930,409, No. 1-3-US-099304090DP1 (U.S. Pat. App. M...

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1-1-US-1032534909P1

Document INTEGRATED MEMORY HAVING A PRECHARGE CIRCUIT FOR PRECHARGING A BIT LINE, 10/325,349, No. 1-1-US-1032534909P1 (U.S. Pat. App. Dec. 20, 2004)

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1-3-US-101341040HP1

Document PROCESS FOR STRUCTURING A PHOTORESIST LAYER, 10/134,104, No. 1-3-US-101341040HP1 (U.S. Pat. App. Dec. 7, 2004)

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1-3-US-101341040EP1

Document PROCESS FOR STRUCTURING A PHOTORESIST LAYER, 10/134,104, No. 1-3-US-101341040EP1 (U.S. Pat. App. Aug. 10, 2004)

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1-8-US-101341040FP1

Document PROCESS FOR STRUCTURING A PHOTORESIST LAYER, 10/134,104, No. 1-8-US-101341040FP1 (U.S. Pat. App. Aug. 10, 2004)

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1-1-US-104383620EP1

Document CIRCUIT CONFIGURATION FOR GENERATING A CONTROLLABLE OUTPUT VOLTAGE, 10/438,362, No. 1-1-US-104383620EP1 (U.S. Pat. App. Aug. 31, 2004)

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1-3-US-1064761408P1

Document METHOD FOR ETCHING A HARD MASK LAYER AND A METAL LAYER, 10/647,614, No. 1-3-US-1064761408P1 (U.S. Pat. App. Jul. 9, 2004)

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26-7-US-1068078201P1

Document METHOD AND APPARATUS FOR INTERNALLY TRIMMING OUTPUT DRIVERS AND TERMINATIONS IN SEMICONDUCTOR DEVICES, 10/680,782, No. 26-7-US-1068078201P1 (U.S. Pat. App. ...

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