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Displaying 99-113 of
819 results
METHOD AND CONFIGURATION FOR COMPENSATING FOR UNEVENNESS IN TH...
Docket
10/652,291,
U.S. Patent Application
(Aug. 29, 2003)
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INTEGRATED MEMORY AND METHOD FOR SETTING THE LATENCY IN THE INTE...
Docket
10/649,408,
U.S. Patent Application
(Aug. 27, 2003)
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Cite Docket
METHOD FOR ETCHING A HARD MASK LAYER AND A METAL LAYER
Docket
10/647,614,
U.S. Patent Application
(Aug. 25, 2003)
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Cite Docket
METHOD FOR PATTERNING A MASK LAYER AND SEMICONDUCTOR PRODUCT
Docket
10/653,589,
U.S. Patent Application
(Sept. 2, 2003)
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Cite Docket
CONFIGURATION AND METHOD FOR MAKING CONTACT WITH THE BACK SURF...
Docket
10/661,340,
U.S. Patent Application
(Sept. 12, 2003)
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Cite Docket
MASK FOR PROJECTING A STRUCTURE PATTERN ONTO A SEMICONDUCTOR S...
Docket
10/653,537,
U.S. Patent Application
(Sept. 2, 2003)
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Cite Docket
METHOD FOR EXPOSING AT LEAST ONE OR AT LEAST TWO SEMICONDUCTOR...
Docket
10/635,583,
U.S. Patent Application
(Aug. 6, 2003)
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Cite Docket
METHOD FOR TESTING A SEMICONDUCTOR MEMORY HAVING A PLURALITY O...
Docket
10/631,356,
U.S. Patent Application
(July 31, 2003)
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Cite Docket
CIRCUIT AND METHOD FOR WRITING AND READING DATA FROM A DYNAMIC M...
Docket
10/623,831,
U.S. Patent Application
(July 21, 2003)
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SELECTION DEVICE FOR A SEMICONDUCTOR MEMORY DEVICE
Docket
10/623,824,
U.S. Patent Application
(July 21, 2003)
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Cite Docket
SEMICONDUCTOR COMPONENT WITH ESD PROTECTION
Docket
10/623,815,
U.S. Patent Application
(July 21, 2003)
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Cite Docket
CIRCUIT CONFIGURATION FOR THE BIT-PARALLEL OUTPUTTING OF A DATA W...
Docket
10/619,290,
U.S. Patent Application
(July 15, 2003)
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VERTICAL TRANSISTOR, AND A METHOD FOR PRODUCING A VERTICAL TRANS...
Docket
10/615,567,
U.S. Patent Application
(July 8, 2003)
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Cite Docket
INTEGRATED SEMICONDUCTOR MEMORY AND FABRICATION METHOD
Docket
10/619,970,
U.S. Patent Application
(July 15, 2003)
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Cite Docket
