`Tel: 571-272-7822
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`Paper 31
`Entered: August 6, 2014
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`
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`HEWLETT-PACKARD COMPANY,
`Petitioner,
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`v.
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`MCM PORTFOLIO, LLC,
`Patent Owner.
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`
`
`Case IPR2013-00217
`Patent 7,162,549
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`
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`Before JONI Y. CHANG, GLENN J. PERRY, and JENNIFER S. BISK,
`Administrative Patent Judges.
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`BISK, Administrative Patent Judge.
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`FINAL WRITTEN DECISION
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`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
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`IPR2013-00217
`Patent 7,162,549
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`I. INTRODUCTION
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`A. Background
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`Petitioner Hewlett-Packard Company (“HP”) filed a Petition (Paper 2,
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`“Pet.”) to institute an inter partes review of claims 7, 11, 19, and 21 (the
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`“challenged claims”) of U.S. Patent No. 7,162,549 (Exhibit 1001, “the ’549
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`patent”) under 35 U.S.C. §§ 311-319. Patent Owner MCM Portfolio, LLC
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`(“MCM”) filed a Preliminary Response. Paper 9. On September 10, 2013,
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`we instituted trial (Paper 10; “Decision”), concluding that Petitioner had
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`demonstrated a reasonable likelihood of showing that the challenged claims
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`are unpatentable under 35 U.S.C. § 103 over U.S. Patent No. 6,199,122 (Ex.
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`1005) (“Kobayashi”) combined with WO 98/03915 (Ex. 1007) (“Kikuchi”).
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`Decision 3, 16.
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`We have jurisdiction under 35 U.S.C. § 6(c). This final written
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`decision is issued pursuant to 35 U.S.C. § 318(a) and 37 C.F.R. § 42.73.
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`Petitioner has shown by a preponderance of evidence that claims 7,
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`11, 19, and 21 are unpatentable.
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`B. Related Proceedings
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`The parties list several cases pending in the Eastern District of Texas
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`that would affect or be affected by the decision in this proceeding, including
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`Technology Properties Limited, LLC v. Hewlett-Packard Co., No. 6:12-cv-
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`208 (E.D. Tex. Mar. 28, 2012), in which the ’549 patent is asserted against
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`Petitioner. See Pet. 1; Paper 6, 1. On February 11, 2014, after a finding of
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`No Violation of Section 337 in a concurrent proceeding at the International
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`Trade Commission (No. 337-TA-841), a stay of the 6:12-cv-208 case was
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`lifted and it was consolidated with Technology Properties Limited, LLC v.
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`Cannon, Inc. et al., No. 6:12-cv-202 (E.D. Tex. Mar. 28, 2012). A
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`IPR2013-00217
`Patent 7,162,549
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`Markman Hearing is currently scheduled in that case for October 8, 2014.
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`Technology Properties Limited, LLC v. Cannon, Inc. et al., No. 6:12-cv-202
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`(E.D. Tex. Mar. 14, 2014).
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`In addition, the ’549 patent is the subject of a pending reissue
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`proceeding, US Application 12/351,691. We ordered a stay of that
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`examination pending the termination or completion of this proceeding.
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`Paper 8.
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`C. The ’549 Patent
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`The ’549 patent relates to controllers for flash-memory cards.
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`Ex. 1001, 1:21-22. As described in the “Background of the Invention,” at
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`the time of the invention, removable flash-memory cards were commonly
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`used with digital cameras to allow for convenient transfer of images from a
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`camera to a personal computer. Id. at 1:26-56. These prior art flash-
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`memory cards were available in several formats, including CompactFlash,
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`SmartMedia, MultiMediaCard (MMC), Secure Digital Card (SD), and
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`Memory Stick card. Id. at 2:28-55. Each of the card formats required a
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`different interface adapter to work with a personal computer. Id. at 3:9-25.
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`The Specification describes a need for a flash-memory card reader
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`that accepts flash-memory cards of several different formats using a
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`universal adapter. Id. at 3:52-63. In response to this need, the ’549 patent
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`describes various improvements to flash-memory card readers, including by
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`determining whether a particular flash-memory card includes a controller
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`and, if not, performing operations to manage error correction for the flash-
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`memory card. Id. at 3:24-65.
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`IPR2013-00217
`Patent 7,162,549
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`D. Illustrative Claim
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`Claim 7, reproduced below, is illustrative of the claimed subject
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`matter:
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`7. A method comprising:
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`using a controller chip to interface a flash storage system with
`or without a controller to a computing device, the controller
`chip comprising a flash adapter, wherein the flash storage
`system comprises a flash section and at least a medium ID;
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`determining whether the flash storage system includes a
`controller for error correction; and
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`in an event where the flash storage system does not have a
`controller for error correction, using firmware in the flash
`adapter to perform operations to manage error correction of
`the flash section, including bad block mapping of the flash
`section in the flash storage system that is coupled to the
`flash adapter section.
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`II. ANALYSIS
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`A. Seventh Amendment
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`As a preliminary matter, MCM argues that inter partes review
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`proceedings violate the Seventh Amendment. PO Resp. 2-13. The U.S.
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`Court of Appeals for the Federal Circuit, however, has previously rejected
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`this argument in the context of reexaminations. Patlex Corp. v. Mossinghoff,
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`758 F.2d 594, 603-05 (Fed. Cir. 1985) (holding that even when applied
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`retroactively, the reexamination statute does not violate the jury trial
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`guarantee of the Seventh Amendment); see also Joy Techs., Inc. v. Manbeck,
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`959 F.2d 226, 228-29 (Fed. Cir. 1992) (affirming the holding in Patlex),
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`other grounds superseded by statute, 35 U.S.C. § 145, as recognized in In re
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`Teles AG Informationstechnologien, 747 F.3d 1357 (Fed. Cir. 2014). Inter
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`partes review proceedings continue the basic functions of the reexamination
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`proceedings at issue in Patlex—authorizing the Office to reexamine the
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`IPR2013-00217
`Patent 7,162,549
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`validity of an issued patent and to cancel any claims the Office concludes
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`should not have been issued. Patent Owner does not identify any
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`constitutionally-significant distinction between reexamination proceedings
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`and inter partes review proceedings. Thus, for the reasons articulated in
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`Patlex, we conclude that inter partes reviews, like reexaminations, comply
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`with the Seventh Amendment.
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`B. Claim Construction
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`We construe all terms, whether or not expressly discussed here, using
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`the broadest reasonable construction in light of the ’549 patent specification.
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`37 C.F.R. § 42.100(b). For the purposes of the decision to institute we
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`expressly construed the following terms: (1) “flash adapter” and “flash
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`adapter section” as “a section of the controller chip that enables
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`communication with the flash storage system” and (2) “bad block mapping”
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`as a type of error correction. Decision 5-6. In the post-institution briefs, the
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`parties do not dispute these constructions. See Paper 23 (“PO Resp.”); Paper
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`24 (“Reply”). For purposes of this decision, we continue to apply these
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`constructions.
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`C. Overview of Kobayashi
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`Kobayashi describes a memory device for a computer with a converter
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`that converts serial commands of the computer to parallel commands that are
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`then used to control a storage medium (which can be a flash-memory card).
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`Ex. 1005, 2:55-64, 3:63-65. This configuration is shown in Figure 1, which
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`is reproduced below.
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`IPR2013-00217
`Patent 7,162,549
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`Figure 1 is a block diagram of computer 11 with reader/writer 12 and flash-
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`memory card 13. Id. at 5:54-58. The reader/writer includes conversion
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`controller 122, ATA controller 124, and a connector 125 for reading a flash-
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`memory card 13. Id. at 6:5-9.
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`One of the several embodiments described by Kobayashi is shown in
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`Figure 11, reproduced below.
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`Patent 7,162,549
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`Figure 11 depicts an embodiment described by Kobayashi. In the
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`embodiment depicted in Figure 11, flash-memory cards 13 both with and
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`without controllers may be used. Id. at 12:59-65. Sensor 133 determines the
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`type of flash-memory card 13 mounted on connector 125. Id. at 12:59-13: 2.
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`When a flash-memory card with no controller is detected, selector 134
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`connects ATA controller 124 and connector 125. Id. at 13:2-5. When a
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`flash-memory card with a controller is detected, selector 134 connects
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`conversion controller 122 and connector 125.
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`D. Overview of Kikuchi
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`Kikuchi describes a flash-memory card and controller 10 having an
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`interface connected to host computer 14. Ex. 1007, Abstract. Figure 1 of
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`Kikuchi is reproduced below.
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`Patent 7,162,549
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`Figure 1 shows the flash memory card with “one-chip controller” 10 on the
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`flash-memory card. Id. at 9:10-151. Figure 2 of Kikuchi is reproduced
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`below.
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`Figure 2 is a block diagram showing the functional arrangement of controller
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`10, including error controller 32, that performs error control for read and
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`write operations. Id. at 11:14-20; 13:17-19. Error controller 32 also
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`“performs a block substituting process or the like in the event of a failure or
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`error.” Id. at 13:17-21. In a separate embodiment, controller 10 “refers to
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`the block quality flag contained in the block status information of the
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`redundant portion of the readout information . . . to check whether the head
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`block BL0 is non-defective or not” and “detects a non-defective block BLj
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`having the highest address rank.” Id. at 20:20-21:5.
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`E. Obviousness over Kobayashi and Kikuchi
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`HP asserts that a person of ordinary skill in the art would have found
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`the challenged claims obvious over the combination of Kobayashi and
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`1 In this opinion, page numbers for this exhibit refer to the number at the
`right hand bottom of the page, not the number in the top middle of the page.
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`Patent 7,162,549
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`Kikuchi. Pet. 42-57 (citing Ex. 1008 (Declaration of Dr. Sanjay Banerjee)
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`¶¶ 102-122). In particular, HP asserts that Kobayashi discloses every
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`limitation of the challenged claims except the details of error correction. Id.
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`at 47-48. HP relies on Kikuchi as describing the recited error correction. Id.
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`at 48-49. In addition, HP asserts that it would have been obvious to one of
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`ordinary skill in the art at the time of the invention to combine the teachings
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`of the two references, which both describe ATA controllers that work with
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`flash-memory cards with, or without, on-card controllers, in order to
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`“reliably retain stored data.” Pet. 50 (citing Ex. 1008 ¶ 121 (quoting Ex.
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`1007 (Kikuchi), 4:1-3)).
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`We are persuaded that a preponderance of the evidence demonstrates
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`that the combination of Kobayashi and Kikuchi discloses each of the
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`limitations of the challenged claims, as presented in HP’s Petition. See Pet.
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`42-57; Ex. 1008 ¶¶ 102-122. We are also persuaded that a preponderance of
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`the evidence demonstrates that a person of ordinary skill in the art would
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`have combined the Kobayashi and Kikuchi references. See Pet. 50; Ex.
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`1008 ¶ 121.
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`MCM explicitly addresses only the requirement of “a controller chip,”
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`arguing that Kobayashi does not disclose using a single chip with the
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`claimed functionality, but instead has “multiple chips that perform distinct
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`functions.” PO Resp. 14. Specifically, MCM argues that Kobayashi
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`discloses two controllers as separate chips: 122 that exclusively interfaces
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`with cards having controllers, and 124 that exclusively interfaces with cards
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`that do not have controllers. PO Resp. 22. Based on this assertion, MCM
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`argues (1) that the Petition should be dismissed because HP did not point out
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`the single chip requirement explicitly in the Petition (id. at 14-21), and
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`(2) that the combination of Kobayashi and Kikuchi would not yield the
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`claimed invention, which requires a single chip (id. at 21-24). We do not
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`find either argument persuasive.
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`First, we are persuaded that HP sufficiently discussed the single-chip
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`limitation in its Petition. The Petition explicitly points to Kikuchi’s
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`disclosure of “controller 10 as a single chip controller.” Pet. 49 (citing
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`Ex. 1007, 7:10-22, 9:11-19); see also Pet. 48, 53, 55; Ex. 1008 ¶¶ 114-117.
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`Moreover, Petitioner also asserts that “Kobayashi’s controller 122 is a ‘one-
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`chip microprocessor.’” Pet. 44 (quoting Ex. 1006, 5:66-6:4, 6:12-22); see
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`also Pet. 53, 55. These statements, combined with HP’s assertion that
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`combining the teachings of the two references is merely “a combination of
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`prior art elements according to known methods to yield predictable results”
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`(Pet. 50-51), were sufficient for us to determine that Petitioner had a
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`reasonable likelihood of showing unpatentability of the challenged claims.
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`Decision 14-16. We are not persuaded otherwise by Patent Owner’s post-
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`institution arguments.
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`Second, this evidence supports a determination that one of ordinary
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`skill in the art would have had both the knowledge and the inclination to
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`place the functionality taught by Kobayashi and Kikuchi on a single chip.
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`See Ex. 1007, 7:12-15 (“This flash memory card has a one-chip
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`controller. . . .”); Ex. 1008 ¶¶ 122-23. In fact, MCM conceded at the oral
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`hearing that it was not beyond the skill of one of ordinary skill at the time of
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`the invention to put multiple functions into a single chip and that, in fact, it
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`is common practice to do so.
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`JUDGE PERRY: Counsel, are you saying that it is beyond the skill of
`one of ordinary skill at the time of this invention to put multiple
`functions integrated into a single chip?
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`MR. HELLER: Not at all.
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`JUDGE PERRY: You are not saying that?
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`MR. HELLER: Not at all when you have a motivation to do so.
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`JUDGE PERRY: Isn’t it kind of a common practice for those who
`design integrated circuits to put multiple functions into those circuits?
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`MR. HELLER: It probably is common practice, but they have to have
`a motivation to do so.
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`JUDGE BISK: Is there some reason not to put them on a single chip?
`It seems like it is just a design choice, whether it is one chip, two
`chips, 10 chips. Is there a particular reason why the number of chips
`matters?
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`MR. HELLER: It is not that. It is, why would you do that? Why
`would you put all that functionality into a single chip?
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`Paper 30 (“Tr.”), 30:17-31:4.
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`MCM’s assertion—that even if Kikuchi’s error correction is
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`incorporated into Kobayashi’s ATA controller 124 the result would not yield
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`the claimed invention—misses the point. PO Resp. 20. The relevant inquiry
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`is whether the claimed subject matter would have been obvious to those of
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`ordinary skill in the art in light of the combined teachings of the references.
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`See In re Keller, 642 F.2d 413, 425 (CCPA 1981). “Combining the
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`teachings of references does not involve an ability to combine their specific
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`structures.” In re Nievelt, 482 F.2d 965, 968 (CCPA 1973). Patent Owner
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`does not argue that applying the teachings of Kikuchi and Kobayashi so that
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`the claimed functionality is on a single chip would have been “uniquely
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`challenging or difficult for one of ordinary skill in the art” at the time of the
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`invention. Leapfrog Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162
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`(Fed. Cir. 2007) (citing KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418
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`(2007)).
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`Patent 7,162,549
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`We conclude that a preponderance of the evidence demonstrates that
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`claims 7, 11, 19, and 21 are unpatentable based on the combination of
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`Kobayashi and Kikuchi.
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`III. CONCLUSION
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`Petitioner has shown, by a preponderance of the evidence, that the
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`challenged claims would have been obvious over the combination of
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`Kobayashi and Kikuchi.
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`Accordingly, it is
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`ORDERED that claims 7, 11, 19, and 21 of the ’549 patent are
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`determined to be unpatentable;
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`FURTHER ORDERED that because this is a final written decision,
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`parties to the proceeding seeking judicial review of the decision must
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`comply with the notice and service requirements of 37 C.F.R. § 90.2.
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`IPR2013-00217
`Patent 7,162,549
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`PETITIONER:
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`ROBERT L. HAILS, JR.
`T. CY WALKER
`KENYON & KENYON LLP
`HP549IPR@kenyon.com
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`PATENT OWNER:
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`EDWARD P. HELLER III
`CHRISTOPHER BRITTAIN
`ALLIACENSE LIMITED LLC
`ned@alliacense.com
`chris@alliacense.com
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