Trials@uspto.gov
`571.272.7822
`
`
`Paper 31
`Entered: June 11, 2015
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`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`MENTOR GRAPHICS CORPORATION,
`Petitioner,
`
`v.
`
`SYNOPSYS, INC.,
`Patent Owner.
`____________
`
`Case IPR2014-00287
`Patent 6,836,420 B1
`____________
`
`
`
`
`
`Before JENNIFER S. BISK, SCOTT A. DANIELS, and
`PHILIP J. HOFFMANN, Administrative Patent Judges.
`
`DANIELS, Administrative Patent Judge.
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`571.272.7822
`
`
`Paper 31
`Entered: June 11, 2015
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`MENTOR GRAPHICS CORPORATION,
`Petitioner,
`
`v.
`
`SYNOPSYS, INC.,
`Patent Owner.
`____________
`
`Case IPR2014-00287
`Patent 6,836,420 B1
`____________
`
`
`
`
`
`Before JENNIFER S. BISK, SCOTT A. DANIELS, and
`PHILIP J. HOFFMANN, Administrative Patent Judges.
`
`DANIELS, Administrative Patent Judge.
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`IPR2014-00287
`Patent 6,836,420
`
`
`I. INTRODUCTION
`A. Background
`Mentor Graphics Corporation (“Petitioner”) filed a Petition to institute
`an inter partes review of claims 1–3, 10–13, and 20 of U.S. Patent No.
`6,836,420 B1 (“the ’420 patent”). Paper 6 (“Pet.”).1 We instituted trial for
`claims 1–3, 10–13, and 20 of the ’420 patent on certain grounds of
`unpatentability alleged in the Petition. Paper 9 (“Decision to Institute” or
`“Inst. Dec.”).
`After institution of trial, on September 17, 2014, Patent Owner,
`Synopsys, Inc., (“Patent Owner”), filed a Patent Owner Response (“PO
`Resp.”), along with a Declaration by Patent Owner’s Declarant, Dr. Brad
`Hutchings (“Hutchings Declaration”). Subsequently, Petitioner filed a
`Reply (“Reply”) on December 12, 2014 and a Declaration in support of the
`Reply by Petitioner’s Declarant, Mr. Edward Detjens (“Reply Declaration”).
`Paper 22.
`A hearing for IPR2014-00287 was held on March 10, 2015. The
`transcript of the hearing has been entered into the record. Paper 30 (“Tr.”).
`We have jurisdiction under 35 U.S.C. § 6(c). This final written
`decision is issued pursuant to 35 U.S.C. § 318(a).
`Petitioner has shown by a preponderance of the evidence that claims
`1–3, 10–13, and 20 of the ’420 patent are unpatentable based on the
`combination of Vander Zanden and Shand. Petitioner has not shown that the
`challenged claims are unpatentable over any of the other proposed grounds.
`
`
`1 We refer to the corrected Petition filed January 15, 2014.
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`B. The ’420 Patent
`The ’420 patent (Ex. 1001) generally relates to memory circuit design
`and specifically, a method and corresponding digital circuit design for
`resetable memory. Ex. 1001, 1:7–10. The ’420 patent states, as a matter of
`background, that the circuitry for a conventional resetable memory unit is
`complicated and expensive because “each n wide storage cell is
`implemented with resetable flip-flops that are individually accessed via
`complicated multiplexing and control circuitry.” Id. at 1:65–67. According
`to the patent, such a resetable memory unit is relatively slow and consumes
`more silicone surface area than a non-resetable memory unit. Id. at 2:3–6.
`A solution to these challenges, proposed by the ’420 patent, is
`designing resetable memory 220 as a combination of memory unit without
`reset 201, and memory unit with reset 205. Id. at 1:61–2:2, Fig. 2A. Figure
`2A of the ’420 patent, illustrating resetable memory 220, is reproduced
`below.
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`As depicted by Figure 2A, above, both memory unit without reset 201
`and memory unit with reset 205 are connected to data out line 209 via
`multiplexor 207. Memory unit without reset 201 is larger in that it has a
`greater data width than memory unit with reset 205. Id. at 3:3–10. The ’420
`patent describes the smaller resetable memory having a cell word size less
`than the cell word size of the non-resetable memory. For example, the cell
`word size of the resetable memory is only one bit wide, so that the memory
`output from a cell is either a “1” or “0.” Id. at 3:8–10. As explained below,
`the purpose of the combination is that the smaller memory with reset 205
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`“cost effectively disguises the inability of the larger memory 201 to reset its
`cells.” Id. at 3:12–13.
`Resetable memory 220 operates generally as follows: data is provided
`through data in line 203 to memory without reset 201, and is stored in a
`particular cell within the memory. See id.at Fig. 2A. The ’420 patent refers
`to data called from memory without reset 201 as “actual memory unit data
`output 206.” Id. at 3:26–30. Memory unit with reset 205 has a
`corresponding cell, in which a “1” from data in 214 is stored whenever write
`enable (WE) 204 of resetable memory 220 is activated. Id. at 4:1–3. The
`“1” from the memory unit with reset 205 instructs multiplexer 207 to output
`the actual memory unit data output 206 from memory 201 to data out line
`209. Id. at 4:30–35. If memory unit with reset 205 is reset, a reset value, for
`example “0,” is stored in memory unit 205, output to data out 210, and
`received by Multiplexer 207. In this circumstance, reset value 208 is output
`to data out line 209. Id. at 3:51–54. If no new data has been written to the
`particular cell in memory unit without reset 201 since its last reset, the
`multiplexer will continue to output the reset value “0,”2 which remains in its
`storage cell until WE 204 line is activated again. Id. at 4:1–3. Accordingly,
`when a new value is written to the particular cell in memory unit without
`reset 201, the “0” will be over written with a “1” and the new value will be
`output by multiplexer 207 to data out line 209. Id. at 4:30–35. The ’420
`patent explains that “[i]n this manner, the circuit of FIG. 2[A] emulates the
`
`2 The reset may be a value besides “0,” for instance FIG. 2B discloses an
`embodiment in which “a reset value function circuit 230 may be inserted
`between (and coupled to) the reset value 208 input of the multiplexer 207
`and the address input 202 of the resetable memory 220.” Ex. 1001,
`4:67−5:3.
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`behavior of a memory unit having the storage capacity of memory unit 201
`but also having reset capability.” Id. at 4:46–48.
`In other words, the memory unit with reset 205 effectively replicates
`the behavior of a resetable memory by providing “0” or another reset value,
`if there has been a reset of a corresponding cell in memory unit with reset
`205, unless and until new data is written to memory 201. See id. at 4:46–54.
`In addition to the resetable memory circuit embodiment of Figure 2A
`discussed above, the ’420 patent describes a circuit design methodology
`inferring the use of a resetable memory from the behavioral level, or RTL
`(register-transfer level) description of the memory. Id. at 5:32–34. Rather
`than describe the specific circuit hardware, RTL level description describes
`the memory circuit in terms of its function, or operational flow, including
`the characteristic of the memory that it is resetable. Id. at 5:36–44. A
`software design tool, by way of example, which facilitates circuit design,
`infers from the RTL level description that a reset condition is being applied
`to at least one specific variable, and the software design tool can incorporate
`a resetable memory into the designer’s circuit design.3 Id. at 6:27–29; see
`Fig. 4.
`
`C. Illustrative Claims
`Of the challenged claims, the independent claims are 1 and 11. Each
`of dependent claims 2, 3, and 10 depends directly from claim 1. Each of
`
`
`3 The ’420 patent states that “[t]he automatic inference can be accomplished,
`for example, by configuring the design tool to recognize from the
`operational flow of the circuit that: 1) some type of reset is being applied to
`the stored data values within the circuit; and 2) the stored data values are
`being changed to some type of reset value in response.” Ex. 1001, 6:22–27.
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`dependent claims 12, 13, and 20 depends directly from claim 11. Claims 1
`and 11 illustrate the claimed subject matter and are reproduced below:
`
`1. A method, comprising:
`a) inferring the existence of a resetable memory from
` a behavioral or RTL level description of a semiconductor
` circuit; and
`b) incorporating a resetable memory design into a design
` for said semiconductor circuit.
`
`11. A machine readable medium having stored thereon a
` sequence of instructions which, when executed by a digital
` processing system, cause said system to perform a method,
` said method, comprising:
` a) inferring the existence of a resetable memory from a
` behavioral or RTL level description of a semiconductor
` circuit; and
` b) incorporating a resetable memory design into a design
` for said semiconductor circuit.
`
`
`
`D. The Prior Art References Supporting Alleged Unpatentability
`Petitioner relies upon the following prior art references:
`Shand, U.S. Patent No. 6,192,447 B1 (issued Feb. 20, 2001)
`(“Shand ’447,” Ex. 1006).
`Runaldue, U.S. Patent No. 5,067,110 (issued Nov. 19, 1991)
`(“Runaldue ’110,” Ex. 1007).
`Nels Vander Zanden, Synthesis of Memories From Behavioral HDLs,
`IEEE (1994) (“Vander Zanden,” Ex. 1003).
`Peter Wohl & John Waicukauski, Using Verilog Simulation Libraries
`For ATPG, IEEE (1999) (“Wohl,” Ex. 1004).
`XILINX SYNTHESIS TECHNOLOGY (XST) USER GUIDE, VERSION 3.1I,
`Xilinx, Inc. (2000) (“XST,” Ex. 1005).
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`E. The Pending Grounds of Unpatentability
`Reference(s)
`Basis
`Vander Zanden (Ex. 1003) § 102
`Wohl (Ex. 1004)
`§ 102
`Vander Zanden and Shand
`§ 103
`(Ex. 1006)
`Vander Zanden and
`Runaldue (Ex. 1007)
`
`
`§ 103
`
`Claims challenged
`1, 2, 10–12, and 20
`1, 2, 10–12, and 20
`1–3, 10–13, and 20
`
`1–3, 10–13, and 20
`
`Petitioner supports its challenge with a Declaration by Mr. Ewald
`Detjens A.B., M.S. (“Detjens Decl.,” Ex. 1002).
`
`II. CLAIM CONSTRUCTION
`A. Legal Standard
`Consistent with the statute and the legislative history of the Leahy-
`Smith America Invents Act (“AIA”), Public Law 112-29, 125 Stat. 284
`(September 16, 2011), the Board will interpret claims of an unexpired patent
`using the broadest reasonable construction in light of the specification of the
`patent. See Office Patent Trial Practice Guide, 77 Fed. Reg. 48,756, 48,766
`(Aug. 14, 2012); 37 C.F.R. § 42.100(b). Under the broadest reasonable
`construction standard, claims are to be given their broadest reasonable
`interpretation consistent with the specification, and the claim language
`should be read in light of the specification as it would be interpreted by one
`of ordinary skill in the art. In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d
`1359, 1364 (Fed. Cir. 2004), see In re Cuozzo Speed Techs., LLC, 778 F.3d
`1271, 1279–83 (Fed. Cir. 2015). Also, we must be careful not to read a
`particular embodiment appearing in the written description into the claim, if
`the claim language is broader than the embodiment. See In re Van Geuns,
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`988 F.2d 1181, 1184 (Fed. Cir. 1993) (“[L]imitations are not to be read into
`the claims from the specification.”).
`
`B. Overview of the Parties’ Positions
`1. Inferring and Incorporating
`In the Decision to Institute, we provided an interpretation for
`“inferring” in accordance with its plain meaning, including: concluding,
`deciding, deducing, deriving, extrapolating, gathering, judging, making out,
`reasoning, understanding, and recognizing. Inst. Dec. 9–10. We did not
`provide a construction for any other terms.
`Patent Owner’s position is that the word “deducing” comes closer to
`the meaning of “inferring” than the words “recognizing” or “identifying” as
`proposed by Petitioner. PO Resp. 24, see also Pet. 14. Our construction
`includes from its plain meaning, a variety of words (including: deducing
`recognizing, and identifying) that, depending on context, provide additional
`understanding of the word “inferring.” Inst. Dec. 9–10. A plain meaning of
`the word “incorporating” is “to unite or work into something already existent
`so as to form an indistinguishable whole.” Incorporate, Merriam-Webster
`Online Dictionary, http://www.merriam-webster.com/dictionary/incorporate
`(last visited May 28, 2015).
`For these words, we do not consider the proffered constructions to
`provide any clarity over the term itself. Consequently, we simply are not
`persuaded by either of the parties contentions and interpretations that under
`the broadest reasonable interpretation, in the context of the Specification and
`claims, that these words should be construed with respect to only the
`particular definitions or meanings ascribed to them by either party.
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`2. Memory
`Based on the parties’ positions and arguments in the Petition, Patent
`Owner’s Response, Petitioner’s Reply, as well as at the oral hearing, with
`respect to Vander Zanden, the base reference in each ground, we determine
`that the word “memory” should be construed explicitly.
`Neither party provides a construction for “memory,” however, the
`’420 patent describes a “memory unit” in the Background section of the
`Specification as,
`having a plurality of storage cells (or simply, “cells”).
`Associated with each cell is a unique address that provides
`access to the location of a particular storage cell. Each storage
`cell has the capacity to store “n” bits (where n is an integer
`greater than or equal to one). The n bits may be collectively
`referred to as a word of data.
`
`Ex. 1001, 1:15–20. The ’420 patent explains that for a memory, from an
`input perspective, a word of data (i.e. “n” bits of data) is written to a specific
`cell address in the memory unit, and from an output perspective, the word of
`data is retrieved from a provided cell address and “the word of data is
`presented at the data output bus.” Id. at 21–38. Thus, the ’420 patent
`provides certain structural and functional characteristics that provide a basis
`for defining “memory.” Moreover, a person of ordinary skill in the art at the
`time of the invention would have understood based on these characteristics
`that a memory unit in the ’420 patent either presents a word of data from a
`specified address at the output in a “read” command, or overwrites old data
`with a new word of data at a specified address in a “write” command.
`Hutchings Decl. ¶ 21. (“One or more inputs control whether the current
`contents of a memory word should be presented at the output (referred to as
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`a ‘read’) or whether the current contents should be overwritten and updated
`to contain a new value (referred to as a ‘write’).”) Based on the
`Specification and evidence before us, we construe “memory” as a device for
`storing data having a plurality of cells, each cell having a unique address for
`storing data, where data is written to a cell during a write function, and,
`during a read function data is retrieved from a cell and presented at a
`memory output.
`3. Resetable Memory
`Petitioner provides contentions regarding the broadest reasonable
`construction of “resetable memory.” Pet. 10–14. Specifically, Petitioner
`contends that because the ’420 patent describes that the memory unit’s cells
`are not actually reset, but only appear to be reset to downstream
`components, “resetable memory” is “a memory unit whose output value(s)
`can be cleared to a reset value, e.g., ‘0’, the memory unit comprising one or
`more storage cells.” Id. at 11 (emphasis added). Patent Owner argues that
`Petitioner’s construction is overly broad, and that the Specification of the
`’420 patent repeatedly describes that a “resetable memory” “must output a
`reset value for a given memory cell (following a reset) until new data is
`written into that cell.” PO Resp. 12–13 (emphasis added). Petitioner
`counters that the construction of this term should not be conditioned on
`future data writes. Reply 6–7.
`A claim construction analysis begins with, and is centered on, the
`claim language itself. See Interactive Gift Express, Inc. v. Compuserve, Inc.,
`256 F.3d 1323, 1331 (Fed. Cir. 2001). Nevertheless, claims must be read in
`view of the specification of which they are a part.` In re Translogic Tech.,
`Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007), Phillips v. AWH Corp., 415 F.3d
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`1303, 1315, (Fed.Cir. 2005) (en banc). The specification is the single best
`guide to the meaning of a disputed term. Id. Turning to the language of
`claim 1, the claimed method includes two steps “inferring the existence of a
`resetable memory,” and “incorporating a resetable memory design,” but the
`claim language does not, in any detail, explicate what the “resetable
`memory” itself, is, or does. Ex. 1001, claim 1.
`The Specification of the ’420 patent states from a structural standpoint
`that “a resetable memory is described that includes a memory without reset
`capability.” Ex. 1001, 2:51–52. The purpose of including a “memory
`without reset” in the overall resetable memory, the Specification explains, is
`to be less expensive and less complex then an actual “memory with reset”
`because “often, the integration of circuitry for resetting the cell word values
`of the memory unit 101 is too expensive and/or complicated to implement
`. . . having noticeably slower performance (and that consumes more silicon
`surface area).” Id. at 1:61–2:6. The “memory without reset” portion of the
`overall resetable memory is smaller and more efficient, but unable to reset
`its memory cells. Id. at 3:12–13.
`As discussed in further detail below, we are not apprised of a
`sufficient reason to read “memory without reset” into the claims. Though
`understanding the claim language may be aided by the explanations
`contained in the written description, it is important not to import into a claim
`limitations that are not a part of the claim. Superguide Corp. v. DirecTV
`Enters., Inc., 358 F.3d 870, 875 (Fed. Cir. 2004). Nevertheless, as described
`explicitly in the ’420 Specification, when reset, the overall “resetable
`memory” must be able to output a reset value, despite retention of what is
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`essentially stored, old data in a particular memory cell of the resetable
`memory. See Ex. 1001, 3:11–23.
`Patent Owner alleges that the Specification consistently discloses that
`“a ‘resetable memory’ must output a reset value for a given memory cell
`(following a reset) until new data is written into that cell.” PO Resp. 13–17
`(citing Ex. 1001, 3:40–58, 4:17–21, 47–54, 7:12–31, Figs. 2A, 2B, 3, 5, 6;
`Hutchings Decl. ¶¶ 31, 36–40). Dr. Hutchings testifies that a person of
`ordinary skill in the art reading the ’420 patent “would understand that one
`defining characteristic of a resetable memory is that, following a reset, it
`must output a reset value for a given memory cell until new data is written
`into that cell.” Hutchings Decl. ¶ 31. It is further stated by Dr. Hutchings
`that in observing the operating flow of the invention from Figure 3 of the
`’420 patent, the implementation of the described invention relies explicitly
`on the methodology that “a reset is asserted 301. This causes the reset value
`208 (in FIGS. 2A and 2B) to be provided 302 as the effective memory cell
`output-until the cell is written to.” Id. ¶ 35 (citing Ex. 1001, 4:56–61).
`Our review of the Specification indicates that the “resetable memory”
`is consistently defined as “reset” in each embodiment to output the reset
`value (as opposed to the stored, old, data in the memory without reset) until
`a new data value is written in a particular memory cell. Ex. 1001, 3:50–56
`(“That is, after the resetable memory 220 has been ‘reset’, any attempt to
`read a data word from a particular cell within the memory unit without reset
`201 will produce the reset value 208 at the memory unit data output 209.
`This functional behavior continues for each cell until a particular cell is
`written to.”) We are mindful that we should not ordinarily rely on the
`preferred embodiments alone as representing the entire scope of the claimed
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`invention. CCS Fitness, Inc. v. Brunswick Corp., 288 F.3d 1359, 1370 (Fed.
`Cir. 2002); see also Rexnord Corp. v. Laitram Corp., 274 F.3d 1336, 1344
`(Fed. Cir. 2001) (emphasizing that the scope of a claim term often covers
`more than the embodiments disclosed in the specification and that a patent
`applicant need not describe “in the specification every conceivable and
`possible future embodiment of his invention”). However, Patent Owner’s
`evidence from the ’420 patent unambiguously describes how all the
`embodiments include this functionality. To construe this term as Petitioner
`proposes as simply “a memory unit whose output value(s) can be cleared to
`a reset value, e.g., ‘0’,” ignores the explicit behavior and the methodology of
`a “resetable memory” as described in the Specification. Pet. 11. Moreover,
`Petitioner’s proposed construction relies in part on a statement from the
`Background of the ’420 patent explaining that in the context of known
`resetable memories “[a] reset function effectively ‘clears’ the memory unit’s
`cell word values to some ‘reset’ value.” Id. (citing Ex. 1001, 1:59–60.) This
`statement, however, relates to conventionally clearing the memory unit’s cell
`value, not the “effective” output discussed in context of the inventive
`resetable memory described later in the detailed description. See Ex. 1001,
`3:24–26.
`Petitioner’s apparent position that the word “effectively” ties this
`phrase discussing known circuitry for resetting cell word values in a memory
`unit, to the “‘effective’ memory unit output as observed by the downstream
`circuitry,” discussed later in the Specification is not persuasive. Id. at 3:32–
`34. Indeed, supported as it is by the Background of the invention,
`Petitioner’s incorrect construction would encompass the example described
`in the Background section of the Specification, i.e. the known method using
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`a resetable flip-flop for clearing each storage cell in the memory. See id. at
`1:63–2:6. This is not a reasonable interpretation owing to the detailed
`description and more specific characterization of the described “resetable
`memory,” contrasted against the known resetable memory described in the
`Background section of the ’420 patent. Thus, we are persuaded that one of
`ordinary skill in the art, would understand from the Specification of the ’420
`patent that a “resetable memory,” as claimed, is a memory, as construed
`above, that outputs a reset value until new data is written into the memory.
`4. Resetable Memory Design
`Claims 1 and 11, in paragraphs b), both recite a “resetable memory
`design.” In the context of both the method recited in claim 1, and the
`machine readable medium recited in claim 11, paragraph b) reads:
`b) incorporating a resetable memory design into a design
` for said semiconductor circuit.
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`On its face, the predicate in this clause uses the word “design” in the context
`of a circuit, i.e. a semiconductor circuit design. Reviewing the
`Specification, the term “design” is similarly used in almost every instance to
`refer to a circuit or semiconductor circuit. For example, the Specification
`explains the benefits of implementing the resetable memory in a circuit
`design, where:
`[a] further utility of the approaches discussed above is the ease
`at which a memory having reset may be incorporated into a
`designer’s circuit design . . .[f]or example, semiconductor
`circuits are typically designed with a particular semiconductor
`manufacturing process (i.e., a “foundry”) in mind. Usually, the
`foundry supplies models of basic building blocks (e.g., logic
`gates, memory units, etc.) from which a semiconductor chip
`design can be constructed.
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`Ex. 1001, 5:9–18 (emphasis added).
`From the plain meaning of the claims and the Specification, we
`understand that the word “design” in the context of “resetable memory”
`essentially means a circuit design. Moreover, understanding that paragraph
`b) in claims 1 and 11 is the implementation step relative to the preceding
`“inferring” step in paragraph a), this implementation step explains how the
`“resetable memory” is to be used in a semiconductor circuit. Accordingly,
`the broadest reasonable interpretation of “resetable memory design” in light
`of the Specification is a resetable memory as defined previously,
`implemented in a circuit design.
`
`III. ANALYSIS
`A. Alleged Anticipation of Claims 1–2, 10–12, and 20 by Vander
`Zanden
`
`For the reasons given below, despite the arguments provided in the
`Petition, and the evidence cited therein, Petitioner has not shown, by a
`preponderance of the evidence, that each of claims 1–2, 10–12, and 20 are
`unpatentable as anticipated by Vander Zanden.
`1. Vander Zanden
`Vander Zanden discloses a method of creating descriptions of small
`memory designs “such as multi-port register files” for use in computer
`emulation—synthesis—that differs from conventional techniques. Ex. 1003,
`71. The method synthesizes a description of a memory, specifically a two-
`dimensional array regFile, apart from other logic and datapath elements as a
`behavioral description. Id. at 72. “This allows the designer to include the
`behavioral description of the memory with the rest of the HDL [Hardware
`Description Language] code, yet offers multiple architectural
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`implementations for the memory without additional effort for the designer.”
`Id. at 71. Figure 3 of Vander Zanden is reproduced below:
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`Figure 3 of Vander Zanden illustrates an HDL model for a memory
`having an if-else statement that includes on one hand a data out, “out1”
`result of “0,” and on the other hand, a data out result of cell addresses,
`“addr1, 2, 3.” Ex. 1003, 73.
`Figure 4 of Vander Zanden, reproduced below, discloses a particular
`datapath circuit design based on the HDL description of Figure 3 including
`two registers, an adder (ADD1), and a multiplexor leading flip-flop DFF 6 to
`the data out line OUT1. Id.
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`Figure 4 of Vander Zanden illustrates a datapath design containing
`register file cell.
`According to Vander Zanden, the use of such a memory synthesis
`technique and datapath design reduces the size of the circuit design as well
`as operational delay. Id. at 74.
`2. Discussion
`i. Claims 1–2, and 10
`Petitioner argues that Vander Zanden anticipates claim 1, a method
`claim, because it discloses not only “inferring a resetable memory” but also
`“incorporating a resetable memory design into a design for said
`semiconductor circuit.” Pet. 15–16. Petitioner states that “[a] POSA would
`understand the synthesis process described by Vander Zanden to teach
`inferring the existence of a memory by the presence of a ‘two-dimensional
`array’ within the behavioral description.” Id. at 16 (citing Detjens Decl.
`¶ 36(a)). Petitioner asserts that a two-dimensional array of bits, such as
`regFile disclosed by the VHDL model in Vander Zanden’s Figure 3,
`constitutes a memory, and that resetable flip-flop DFF6 on the data out line
`as shown in the circuit design at Figure 4 makes the memory resetable. Id.
`(citing Ex. 1003, 72).
`Patent Owner argues that Vander Zanden does not disclose “a
`resetable memory design” as claimed “because, from the perspective of the
`downstream circuitry, the circuit shown in Vander Zanden Figure 4 is not a
`memory. This is due to the presence of an adder in the circuit.” PO Resp.
`26. In support, Patent Owner cites to Petitioner’s Declarant, Mr. Detjens’,
`deposition testimony:
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`Q. Would the average engineer understand [the circuit
`with an adder] to be a memory?
`
`. . .
`
`THE WITNESS: The average engineer would not expect
`an adder to be at that place in a memory.
`
`Id. (citing Ex. 2010, 41:3–16). Patent Owner alleges that Mr. Detjens, as
`well as Patent Owner’s Declarant, Dr. Hutchings, agree that the downstream
`circuitry from Vander Zanden’s output flip-flop DFF6 would, at times, see
`the sum of two memory locations due to adder ADD1, and not an actual
`memory value from the memory locations in RGF1. Id. at 28. Patent Owner
`contends that because of this a designer of ordinary skill in the art “could not
`(and would not) use the Vander Zanden Figure 4 circuit as a memory
`because in one state the circuit would output values [from ADD1]
`completely different from either a reset value or a value stored in the register
`file RGF1. Id. at 29.
`Petitioner’s Declarant, Mr. Detjens testifies that at the time of the
`filing of the patent, those of ordinary skill in the art would have understood
`Vander Zanden to disclose a memory, specifically by the steps of:
`[a]nalyzing the extracted logic equations to determine the
`characteristics, i.e., requirements, of the memory described in
`the behavioral description, e.g., whether the memory is written
`synchronously or asynchronously and how many read and write
`ports are required for the memory. (Id., Step 4.) A POSA
`would have understood another characteristic to be whether the
`memory is resettable.
`
`Ex. 1002 ¶ 36.e. Mr. Detjens states that one of ordinary skill in the art
`would consider Figures 3 and 4 in Vander Zanden to disclose a memory,
`even though there is an adder on one of the outputs of the circuit because the
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`“ADDER only affects the output of the circuit in one mode of the circuit,
`when the multiplexer selects the ADDER path.” Ex. 1024 ¶¶ 23–24 (citing
`Ex. 1003, 74, Fig. 4). In a mode of the circuit where the multiplexer does
`not select the ADDER, Mr. Detjens alleges that “a POSA would have
`understood the circuit of Fig. 4 to operate as memory, with the output value
`of RGF1 appearing on the output, unless the reset signal, ‘rst,’ has been
`applied.” Id. at 24. Thus, Mr. Detjens alleges that on one hand the circuit
`discloses a memory with a reset function, and on the other hand it discloses a
`memory output operated upon by ADDER.
`Petitioner’s evidence is persuasive that a person of ordinary skill in
`the art would consider the circuit shown in Vander Zanden’s Figure 4 to
`operate as a memory, as we have construed the term, with a reset capability.
`We construed “memory” as a device for storing data having a plurality of
`cells, each cell having a unique address for storing data, where data is
`written to a cell during a write function, and, during a read function data is
`retrieved from a cell and presented at a memory output. See section II.B.2.
`Although the additional circuitry of the ADDER is provided to perform an
`operation on values output from RGF1, in the mode where the ADDER is
`not selected, OUT1 will output a value from a register in RGF1, unless a
`reset signal is applied, as a memory would in accordance with our claim
`construction. At least in one state downstream circuitry would recognize the
`circuit of Figure 4 as a memory, thus “inferring” the circuit to be a memory
`with reset capability. Patent Owner’s argument that this does not occur
`when the ADDER mode is in effect, does not explain why the portion of the
`circuit without the ADDER circuitry does not operate and would not be
`recognized, as a memory having a reset function.
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`Patent Owner further asserts that Vander Zanden does not anticipate
`the claimed subject matter because it does not disclose a “resetable
`memory,” as properly construed, because Vander Zanden does not keep, i.e.
`remember, that the memory has been reset. PO Resp. 29–33. Patent Owner
`contends that the code in Vander Zanden’s Figure 3 includes well known “if
`then” statements which show that only when the reset signal is high, e.g.
`rst=1, is OUT1 a reset value “0.” Otherwise, when the signal goes low, “the
`output of the circuit (out1) is assigned the value stored in a particular
`memory address (see line 14) or the sum of two values stored in different
`memory addresses (see line 12).” PO Resp. 32 (citing Ex. 2011 ¶ 59).
`Based on our claim construction, we are persuaded that Vander
`Zanden does not disclose a “resetable memory” as recited in independent
`claim 1. We determined that a “resetable memory” me
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