Trials@uspto.gov
`Tel: 571-272-7822
`
`Paper 30
`Entered: July 9, 2015
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_______________
`
`TOSHIBA CORPORATION, TOSHIBA AMERICA, INC.;
`TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.; and
`TOSHIBA AMERICA INFORMATION SYSTEMS, INC.,
`Petitioner,
`
`v.
`
`INTELLECTUAL VENTURES I LLC,
`Patent Owner.
`_______________
`
`Case IPR2014-00310
`Patent 7,836,371
`_______________
`
`
`
`Before KEVIN F. TURNER, TREVOR M. JEFFERSON,
`and DAVID C. MCKONE, Administrative Patent Judges.
`
`TURNER, Administrative Patent Judge.
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`
`
`
`
`
`Tel: 571-272-7822
`
`Paper 30
`Entered: July 9, 2015
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_______________
`
`TOSHIBA CORPORATION, TOSHIBA AMERICA, INC.;
`TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.; and
`TOSHIBA AMERICA INFORMATION SYSTEMS, INC.,
`Petitioner,
`
`v.
`
`INTELLECTUAL VENTURES I LLC,
`Patent Owner.
`_______________
`
`Case IPR2014-00310
`Patent 7,836,371
`_______________
`
`
`
`Before KEVIN F. TURNER, TREVOR M. JEFFERSON,
`and DAVID C. MCKONE, Administrative Patent Judges.
`
`TURNER, Administrative Patent Judge.
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`
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`IPR2014-00310
`Patent 7,836,371
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`I. INTRODUCTION
`
`A. Background
`
`Toshiba Corporation, Toshiba America, Inc., Toshiba America
`
`Electronic Components, Inc., and Toshiba America Information
`
`Systems, Inc. (collectively, “Petitioner”) filed a Corrected Petition (Paper 6,
`
`“Pet.”) to institute an inter partes review of claims 1–10 of U.S. Patent
`
`No. 7,836,371 (Ex. 1001, “the ’371 Patent”). See 35 U.S.C. § 311.
`
`Intellectual Ventures I LLC (“Patent Owner”) filed a Preliminary Response
`
`(Paper 9, “Prelim. Resp.”). Pursuant to 35 U.S.C. § 314, in our Decision to
`
`Institute (Paper 12, “Dec.”), we instituted this proceeding as to claims 1–10.
`
`After the Decision to Institute, Patent Owner filed a Patent Owner
`
`Response (Paper 19, “PO Resp.”) and Petitioner filed a Reply to the Patent
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`Owner Response (Paper 21, “Reply”). An oral hearing (Paper 29, “Tr.”)
`
`was held on February 12, 2015.
`
`
`
`B. Related Cases
`
`Patent Owner has asserted the ’371 Patent against Petitioner in
`
`Intellectual Ventures I LLC and Intellectual Ventures II LLC v. Toshiba
`
`Corporation, Toshiba America Inc., Toshiba America Electrical
`
`Compenents, Inc. and Toshiba America Information Systems, Inc. ,
`
`Case No. 1:13-cv-00453 (D. Del.). Pet. 1; Paper 5, 2.
`
`
`
`C. References Relied Upon
`
`Petitioner relies upon the following prior art references with respect to
`
`the instituted grounds:
`
` 2
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`IPR2014-00310
`Patent 7,836,371
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`Levine
`Ex. 1004
`Ex. 1011 Whetsel
`
`D. The Instituted Grounds
`
`US 5,802,273
`US 5,623,500
`
`
`
`
`Sept. 1, 1998
`Apr. 22, 1997
`
`We instituted this proceeding based on the grounds of unpatentability
`
`set forth in the table below. Dec. 13.
`
`Reference(s)
`
`Basis
`
`Claim(s) Challenged
`
`Levine
`
`35 U.S.C. § 102 1–3 and 5–10
`
`Levine and Whetsel
`
`35 U.S.C. § 103 4
`
`
`
`E. The ’371 Patent
`
`The ’371 Patent is directed to on-chip circuits for the testing and
`
`diagnosis of problems in an integrated circuit, with the circuits used to
`
`observe the internal workings thereof. Ex. 1001, 1:24–27; 2:43–45.
`
`Figures 1b and 2, reproduced below, are illustrative:
`
`
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` 3
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`IPR2014-00310
`Patent 7,836,371
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`Figure 1b of the ’371 Patent shows integrated circuit 100 having
`
`service processor unit (“SPU”) 101 and various circuit blocks connected by
`
`system bus 105. Id. at 6:15–27. SPU 101 is shown in greater detail in
`
`Figure 2 and includes a control unit (e.g., microprocessor 211), buffer
`
`memory unit 218, analysis engine 215, and processor bus 219. Id. at 6:23–
`
`40. Interfaces 210, 216, 217 provide communication between SPU 101 and
`
`the “external world” and interrupt handler 221 receives signals from trigger
`
`event lines 204 or test bus 104, which capture the signals. Id. at 6:40–59.
`
`Operation signals are captured by the SPU, and operation signals are
`
`analyzed, on-chip, by the SPU to determine whether a triggering event has
`
`occurred. Id. at 10:64–11:2, 11:55–59.
`
`Claims 1, 2, and 7, reproduced below, are illustrative of the claimed
`
` 4
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`
`
`subject matter:
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`IPR2014-00310
`Patent 7,836,371
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`
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`1. An integrated circuit comprising:
`
`one or more logic blocks to generate one or more system-
`operation signals at one or more system-operation clock rates; and
`
`a service processor unit, said service processor unit comprising:
`
`a control unit;
`
`a buffer memory; and
`
`a multiplicity of selectable probes,
`
`wherein said service processor unit is adapted to perform
`capture and analysis of said system operation signals during normal
`system operation through said selectable probes.
`
`
`
`2. The integrated circuit according to claim 1, further
`comprising at least one port selected from the group consisting of:
`
`a parallel I/O (PIO) port,
`
`a serial I/O (SIO) port, and
`
`a JTAG port;
`
`wherein data and instructions are to be sent through at least one
`of said ports to said service processor unit from an external
`diagnostics console, and wherein result data is to be sent through at
`least one of said ports from said service processor unit to said external
`diagnostics console.
`
`
`
`7. An integrated circuit comprising:
`
`one or more logic blocks to generate one or more system-
`operation signals at one or more system-operation clock rates;
`
`a system bus; and
`
`a service processor unit, said service processor unit comprising:
`
` 5
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`
`
`a control unit;
`
`a buffer memory; and
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`IPR2014-00310
`Patent 7,836,371
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`a system bus interface,
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`wherein said service processor unit is adapted to perform
`capture and analysis of system operation signals on said system bus
`during normal system operation through said system bus interface.
`
`Ex. 1001, 14:64–15:22, 16:1–14.
`
`
`
`II. ANALYSIS
`
`A. Claim Construction
`
`The Board interprets claims of an unexpired patent using the broadest
`
`reasonable construction in light of the specification of the patent in which
`
`they appear. See 37 C.F.R. § 42.100(b); In re Cuozzo Speed Techs., LLC,
`
`778 F.3d 1271, 1279–81 (Fed. Cir. 2015). Claim terms generally are given
`
`their ordinary and customary meaning, as would be understood by one of
`
`ordinary skill in the art in the context of the entire disclosure. See In re
`
`Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).
`
`The parties do not disagree with our preliminary constructions for
`
`claim terms recited in the instant claims. See PO Resp. passim; Dec. 6–10.
`
`On the full record, we maintain our constructions for the construed claim
`
`terms. We repeat those specifically construed terms here for completeness:
`
`Claim term(s)
`
`Construction
`
`capture
`
`analysis
`
`the acquisition of data in a form that is
`capable of storage
`
`detection of events or states
`
`system operation signals . . .
`during normal system
`operation
`
`signals internal to the integrated circuit
`when the integrated circuit is in a
`normal operation mode
`
` 6
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`IPR2014-00310
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`B. Asserted Grounds of Unpatentability
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`1. Anticipation by Levine
`
`Petitioner contends that Levine anticipates claims 1–3 and 5–10, and
`
`we instituted on such a ground. We are persuaded that Petitioner has
`
`demonstrated by a preponderance of the evidence that claims 1, 3, 5, and 6
`
`are anticipated by Levine, but we are not persuaded that Petitioner has
`
`demonstrated by a preponderance of the evidence that claims 2 and 7–10 are
`
`anticipated by Levine.
`
`
`
`a. Claims 1, 3, 5, and 6
`
`With respect to claim 1, Levine describes a performance monitor
`
`having counters to count events within a processor 10 having logic
`
`blocks 14–38 therein that generate and receive signals. Ex. 1004, Abstract,
`
`5:46–6:21. Those signals are generated based on a clock from a time base
`
`facility, based on the system bus clock. Id. at 10:4–8. Levine also discloses
`
`a performance monitor, which is “a software-accessible mechanism intended
`
`to provide detailed information with significant granularity concerning the
`
`utilization of PowerPC instruction execution and storage control.” Id. at
`
`9:32–36. The performance monitor includes special purpose registers to
`
`record sample data through configuration by the performance monitor. Id. at
`
`11:4–13. System operation signals originate from various execution units
`
`and other units within the micro-processor and can be selected through
`
`multiplexers 72, 73. Id. at 13:29–43, Fig. 7.
`
`Levine details that the performance monitor is adapted to collect
`
`selected performance monitoring data from the logic blocks during normal
`
`system operation. Id. at 15:20–30, Fig. 5. Counters are monitored and when
`
`a predetermined number of events is reached, that predetermined number of
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`events indicates a stop point, based on the time period required. Id. at
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`11:14–29. Levine provides that “[i]t is also important that [the effect] the
`
`previous sample has on the sample being monitored is negligible to ensure
`
`the performance monitor does not affect the performance of the processor.”
`
`Id. at 2:45–48.
`
`With respect to claims 3, 5, and 6, Levine provides that “[w]ith the
`
`appropriate values, the PM facility is readily suitable for use in identifying
`
`system performance problems.” Id. at 12:14–16. Levine also provides that
`
`monitoring occurs for signals originating from various execution units and
`
`other units within the microprocessor. Id. at 13:36–39.
`
`Patent Owner argues that Levine fails to disclose all of the elements of
`
`claim 1 because Levine does not disclose 1) a service processor unit
`
`comprising a buffer memory or 2) a multiplicity of selectable probes.
`
`PO Resp. 3–10. We consider Patent Owner’s arguments in turn below.
`
`Patent Owner argues that special purpose registers 40 and system
`
`memory 58 are not part of the performance monitor because they are outside
`
`the performance monitor. PO Resp. 4–5. Patent Owner also argues that a
`
`component that exists in I/O space would be external to the performance
`
`monitor in Levine, and cites to its expert’s testimony. Id. at 6–7 (citing
`
`Ex. 2001 ¶¶ 26–29). We do not agree.
`
`Rather, we agree with Petitioner that a reference need not use the
`
`same naming conventions as found in an evaluated claim. Reply 1–3.
`
`Further, we agree with Petitioner that Levine makes clear that components
`
`that exist in I/O space can also exist in the performance monitor. Id. at 3.
`
`Levine provides that “included in performance monitor 50 are monitor mode
`
`control registers” and that “[i]n a different embodiment, these registers may
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` 8
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`be accessible by other mean such as addresses in I/O space.” Ex. 1004,
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`9:39–40, 51–53 (emphasis added). Levine also provides that “[t]hese special
`
`purpose registers are accessible for read or write,” such that they could be
`
`considered a buffer memory, per claim 1. Id. at 9:45–46. At oral hearing,
`
`Patent Owner’s counsel stated: “[a]nd there are technical reasons why these
`
`MMCR registers cannot be the buffer memory” (Tr. 48:22–23), but we have
`
`been unable to find a portion of Patent Owner’s Response, its expert’s
`
`testimony, or the oral hearing transcript where those technical reasons are
`
`elucidated. As such, we are not persuaded by Patent Owner’s arguments.
`
`Specifically, considering the testimony of Patent Owner’s expert
`
`Mr. Michael Barr, he stated that “based on the architecture of Levine, in my
`
`opinion, if the SIAR or SDAR registers are in I/O space, these registers
`
`would be external to both the performance monitor 50 and to the processor
`
`10.” Ex. 2001 ¶¶ 28–29. Although we credit his testimony, it does not
`
`consider the other sections of Levine discussed above, which are persuasive
`
`to demonstrate that Levine considered multiple embodiments, with some
`
`memory registers specifically inside the performance monitor. As such, we
`
`do not find Patent Owner’s argument to be persuasive.
`
`Patent Owner also argues that a multiplexer, like that disclosed in
`
`Levine, is always on and, therefore, is not selectable, such that Levine does
`
`not disclose “a multiplicity of selectable probes,” as recited in claim 1.
`
`PO Resp. 7–10. We do not agree.
`
`First, Patent Owner argues that Levine “teaches against using probes”
`
`(id. at 8), but we are not persuaded that Levine provides such a counter
`
`teaching in its disclosure. The fact that Levine provides that “[t]est
`
`instruments designed to probe the internal components of a processor are
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`typically considered prohibitively expensive because of the difficulty
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`associated with monitoring the many busses and probe points of complex
`
`processor systems” (Ex. 1004, 2:17–23), does not necessarily mean that
`
`Levine does not employ probes, as we understand “a multiplicity of
`
`selectable probes,” as described and claimed in the ’371 Patent. We take
`
`Levine’s comment to address the prior art systems and not to limit the use or
`
`function of the system described therein.
`
`Patent Owner argues that Levine never provides that its multiplexers
`
`can be individually selected. PO Resp. 9–10. Patent Owner continues that
`
`“[p]ersons of ordinary skill in the art understand that the multiplexers of
`
`FIG. 7 in Levine contain simple combinatorial logic that cannot be turned
`
`on/off when the host device is functioning.” Id. at 7 (citing Ex. 2001 ¶ 32).
`
`However, as noted by Petitioner, claim 1 does not require the capability to
`
`select and deselect individual multiplexers. Reply 4. Claim 1 requires
`
`selectable probes. The multiplexers of Levine achieve that by being
`
`controlled to select for output one input from a multiplicity of inputs being
`
`received. Id. Additionally, the ’371 Patent provides for a similar
`
`multiplexing function (Ex. 1001, Fig. 9a, 10:25–34), such that we are not
`
`persuaded by Patent’s Owner’s distinction. Depending on the inputs to a
`
`multiplexer, we are persuaded that such a multiplexer could switch between
`
`different signals to achieve the functionality.
`
`Patent Owner does not provide separate arguments with respect to
`
`claims 3, 5, and 6, which depend from claim 1. As such, we have
`
`considered the evidence presented by Petitioner and Patent Owner and, on
`
`the full record, we are persuaded that Petitioner has shown by a
`
`preponderance of the evidence that Levine anticipates claims 1, 3, 5, and 6.
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`IPR2014-00310
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`b. Claim 2
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`With respect to claim 2, Levine discloses that the processor has a bus
`
`interface unit 12 that interfaces with a system bus 11 that is external to the
`
`processor. Ex. 1004, Fig. 1. Petitioner indicates that the PowerPC 604
`
`User’s Manual (Ex. 1008) is incorporated by reference into Levine
`
`(Ex. 1004, 13:20–28). Pet. 33. The Manual discloses that a JTAG (Joint
`
`Test Action Group or IEEE 1149.1 Standard Test Access Port and
`
`Boundary-Scan Architecture) interface and common on-chip processor
`
`(“COP”) unit provides a serial interface to the system for monitoring and
`
`boundary tests. Ex. 1008, 7–2.
`
`Patent Owner argues that Petitioner’s argument about the JTAG
`
`interface relies on portions of the PowerPC manual that are not incorporated
`
`by reference into Levine, and that the processor of Levine need not include
`
`serial or parallel I/O ports. PO Resp. 14. We agree with Patent Owner.
`
`Levine does not incorporate the entire PowerPC manual (see Ex. 1004,
`
`13:20–24), but only chapter 9 thereof. Additionally, we agree that any
`
`interface with the processor in Levine need not be a serial or parallel I/O
`
`port; while a personal computer in the relevant time period would likely
`
`have had both types of ports, we are not persuaded that every “processor”
`
`would have been so equipped.
`
`Petitioner disputes this and argues that its position is that signals to
`
`and from circuits are serial and/or parallel, in form, thus forming a port
`
`therefrom. Reply 9. Petitioner argues that Patent Owner’s statement, that
`
`“not every interface to an integrated circuit is a port,” is unsupported. We
`
`agree with Petitioner that a “port” need not require a peripheral, but we are
`
`still persuaded by Patent Owner’s argument that an interface and a port are
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`11
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`not synonymous. We are persuaded that one of ordinary skill in the art
`
`would have identified a port as having a known configuration, such as used
`
`in the Specification (see Ex. 1001 6:41–49), as opposed to “interface,” that
`
`need not have a known configuration. See Exs. 2003; 3001. As such, we are
`
`not persuaded that Levine discloses serial or parallel I/O ports.
`
`We have considered the evidence presented by Petitioner and Patent
`
`Owner. On the full record, Petitioner has not shown by a preponderance of
`
`the evidence that Levine anticipates claim 2.
`
`c. Claims 7–10
`
`
`
`With respect to claim 7, Petitioner points out that logic blocks 14–38
`
`communicate with each other inside the processor, which is indicated by the
`
`double arrows illustrated in Figure 1. Pet. 38; Ex. 1004, Fig. 1. Petitioner
`
`also alleges that the connections to multiplexers 72, 73 from execution
`
`units 22, 24, 26, 28, 30 form a system bus interface. Ex. 1004, Fig. 7.
`
`Patent Owner argues that Levine fails to disclose a “system bus” or a
`
`“system bus interface,” per claim 7. PO Resp. 10. Patent Owner continues
`
`that Petitioner has identified “a set of unrelated signal paths that individually
`
`connect units 22, 26, 28, 30, and 32 to sequencer unit 18 and argue that these
`
`signal paths are claim 7’s ‘system bus.’” Id. at 11. Patent Owner also points
`
`out that Levine specifically discloses “system bus 11,” and that the other
`
`signal paths are not similarly identified. Id. We agree with Patent Owner.
`
`Petitioner disputes these arguments and contends that Patent Owner is
`
`applying an overly narrow definition of “bus,” and that “bus” should be
`
`defined as “a signal line or a set of lines used by an interface to connect a
`
`number of devices and to transfer data,” continuing that “an individual
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`connection can be a bus.” Reply 6 (citing Ex. 1016, 140–142; emphasis in
`
`original). We do not agree. Although Petitioner emphasizes that a bus can
`
`be comprised by “a signal line,” we are persuaded that the more pertinent
`
`part of the proffered definition is “to connect a number of devices.”
`
`Although possible for that number of devices to be limited to two devices,
`
`the definition suggests that more than two devices may be connected by a
`
`bus, and implies that the signal line or lines are “shared” between the
`
`devices, akin to the distinction raised by Patent Owner. PO Resp. 13. As
`
`such, we are not persuaded that any arbitrary group of signal lines is
`
`equivalent to a bus.
`
`Petitioner also argues that a bus should be identified by the kinds of
`
`signals that are carried by the bus and that, per our claim construction,
`
`should not “limit the signal paths to any particular structure.” Reply 7–8;
`
`Tr. 14–15. Reviewing our claim construction, we do not find that our
`
`construction addressed the structure of a “system bus,” or that we construed
`
`a system bus by the signal carried thereon. Dec. 9. Given that the element
`
`of claim 7, i.e. “a system bus,” is an element of an apparatus, we are
`
`concerned only with its structure and not the functions that it could
`
`implement, other than those specifically recited in the claims.
`
`Lastly, Petitioner argues that Patent Owner’s expert, Mr. Barr,
`
`previously espoused a broader definition of “bus” as “a set of electrical
`
`signals with a group function,” and this conflicts with Patent Owner’s instant
`
`definitions which require the sharing of a communication path and which
`
`differentiate busses from individual connections. Reply 7–8. Although we
`
`acknowledge the differences, we are persuaded that the instant definition of
`
`“bus,” provided by Petitioner (Ex. 1016), is more consistent with the use of
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`the term during the relevant period for the ’371 Patent, and emphasizes a
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`shared signal path between devices. We are persuaded that Levine does not
`
`disclose a system bus such that Levine’s performance monitor “is adapted to
`
`perform capture and analysis of system operation signals on said system bus
`
`during normal system operation through said system bus interface,” per
`
`claim 7.
`
`We have considered the evidence presented by Petitioner and Patent
`
`Owner. On the full record, Petitioner has not shown by a preponderance of
`
`the evidence that Levine anticipates claim 7, or claims 8–10 by dint of their
`
`dependencies on claim 7.
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`
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`2. Obviousness over Levine and Whetsel
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`Petitioner contends that Levine and Whetsel render claim 4 obvious.
`
`Pet. 36. Petitioner tacitly acknowledges that Levine does not disclose
`
`“selectable analog probes,” per claim 4, and cites to Whetsel for that
`
`teaching. Id. Whetsel describes an “analog signal monitor,” which
`
`comprises “TCR 14, TMEM 28, EQCs 24, EQM 22, TAP 12, analog
`
`multiplexer 396, and an analog-to-digital converter (ADC) 398.” Ex. 1011,
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`21:23–26. Whetsel also provides that “[a]fter the analog signal is converted
`
`into a digital form, the analog monitor operates exactly like the digital signal
`
`monitor.” Id. at 21:34–36.
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`Petitioner argues that both Levine and Whetsel are directed to circuits
`
`embedded in integrated circuits that capture and analyze signals therein, and
`
`that Whetsel illustrates that “observability and sampling of analog signals is
`
`among the functions of interest and is a design choice for designers in the
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`circuit testing art.” Pet. 36. Petitioner concludes that one of ordinary skill in
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`the art would have been motivated to include Whetsel’s “analog signal
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`monitor” in the performance monitor of Levine to “produce a more complete
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`testing capability for embedded testing of integrated circuits.” Id.
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`Patent Owner argues that Levine and Whetsel do not render claim 4
`
`obvious because neither Levine nor Whetsel discloses a selectable analog
`
`probe and because Petitioner’s combination of Levine and Whetsel lacks the
`
`rational underpinnings required. PO Resp. 25–29. We consider Patent
`
`Owner’s arguments in turn below.
`
`Patent Owner argues that like the multiplexers of Levine, as discussed
`
`above, the analog multiplexer of Whetsel is “always on and is therefore also
`
`not selectable.” Id. at 26. This argument hinges on the argument that
`
`multiplexers are not selectable probes, which we do not find persuasive, as
`
`discussed above.
`
`Additionally, Patent Owner argues that Petitioner provides only
`
`conclusory statements regarding why Levine and Whetsel would have been
`
`combined. Id. at 27–29. Patent Owner argues a) that Petitioner does not
`
`identify any circuits in Levine that could produce analog signals, b) that
`
`Petitioner fails to provide any rationale for equating “circuit testing” of
`
`Whetsel with the software performance monitoring of Levine, and c) that
`
`Petitioner provides no rational reason to incorporate Whetsel’s analog
`
`signals into the performance monitor of Levine. Id. We do not find these
`
`arguments to be persuasive.
`
`First, although Levine does not disclose circuits that produce analog
`
`signals, we are persuaded that the evaluation of analog signals would have
`
`been seen as useful in light of Whetsel. See Pet. 36. Additionally, we are
`
`persuaded that both provide embedded circuits that capture and analyze
`
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`15
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`IPR2014-00310
`Patent 7,836,371
`
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`signals, which is sufficient rationale to consider the combination of Levine
`
`and Whetsel. One of ordinary skill in the art need not consider circuit
`
`testing and software performance monitoring to be equivalent to consider the
`
`utility of applying Whetsel’s analog probes into the system of Levine.
`
`Lastly, we disagree with Patent Owner that “the temperature and voltage
`
`signals do not provide any useful information to improve the performance of
`
`processor execution and storage control.” PO Resp. 29. We are persuaded
`
`that measurements of temperature could be useful in determining processor
`
`performance.
`
`We have considered the evidence presented by Petitioner and Patent
`
`Owner. On the full record, Petitioner has shown by a preponderance of the
`
`evidence that Levine and Whetsel render claim 4 obvious.
`
`
`
`III. CONCLUSION
`
`Petitioner has demonstrated by a preponderance of the evidence that
`
`claims 1 and 3–6 are unpatentable based on the following grounds of
`
`unpatentability:
`
`(1) Claims 1, 3, 5, and 6 under 35 U.S.C. § 102 as anticipated by
`
`Levine; and
`
`(2) Claim 4 under 35 U.S.C. § 103 as obvious over Levine and
`
`Whetsel.
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`In addition, Petitioner has not demonstrated by a preponderance of the
`
`evidence that claims 2 and 7–10 are unpatentable.
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`16
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`IPR2014-00310
`Patent 7,836,371
`
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`IV. ORDER
`
`For the reasons given, it is
`
`ORDERED that, based on a preponderance of the evidence, claims 1
`
`and 3–6 of U.S. Patent No. 7,836,371 are held unpatentable; and
`
`FURTHER ORDERED that, because this is a Final Written Decision,
`
`parties to this proceeding seeking judicial review of our Decision must
`
`comply with the notice and service requirements of 37 C.F.R. § 90.2.
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`17
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`IPR2014-00310
`Patent 7,836,371
`
`
`For PETITIONER:
`
`Gerald T. Sekimura
`Alan A. Limbach
`DLA PIPER LLP
`gerald.sekimura@dlapiper.com
`alan.limbach@dlapiper.com
`
`
`
`
`
`For PATENT OWNER:
`
`Lori A. Gordon
`Michael D. Specht
`Donald Coulman
`Tim Seeley
`STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
`lgordon-PTAB@skgf.com
`mspecht-PTAB@skgf.com
`dcoulman@intven.com
`tim@intven.com
`
`
`
`
`
`
`
`
`18
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