trials@uspto.gov
`571-272-7822
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`IPR2014-00418, Paper No. 27
`June 2, 2015
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
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`TOSHIBA CORPORATION, TOSHIBA AMERICA, INC.,
`TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC., and
`TOSHIBA AMERICA INFORMATION SYSTEMS, INC.,
`Petitioner,
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`v.
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`INTELLECTUAL VENTURES II, LLC,
`Patent Owner.
`____________
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`Case IPR 2014-00418
`Patent 5,500,819
`____________
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`Held: May 6, 2015
`____________
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`
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`BEFORE: JACQUELINE WRIGHT BONILLA, TREVOR M.
`JEFFERSON, and DAVID C. McKONE, Administrative Patent
`Judges.
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`
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`The above-entitled matter came on for hearing on Wednesday, May 6,
`2015, commencing at 1:15 p.m., at the U.S. Patent and Trademark
`Office, 600 Dulany Street, Alexandria, Virginia.
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`571-272-7822
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`IPR2014-00418, Paper No. 27
`June 2, 2015
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`TOSHIBA CORPORATION, TOSHIBA AMERICA, INC.,
`TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC., and
`TOSHIBA AMERICA INFORMATION SYSTEMS, INC.,
`Petitioner,
`
`v.
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`INTELLECTUAL VENTURES II, LLC,
`Patent Owner.
`____________
`
`Case IPR 2014-00418
`Patent 5,500,819
`____________
`
`Held: May 6, 2015
`____________
`
`
`
`
`
`BEFORE: JACQUELINE WRIGHT BONILLA, TREVOR M.
`JEFFERSON, and DAVID C. McKONE, Administrative Patent
`Judges.
`
`
`
`The above-entitled matter came on for hearing on Wednesday, May 6,
`2015, commencing at 1:15 p.m., at the U.S. Patent and Trademark
`Office, 600 Dulany Street, Alexandria, Virginia.
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`
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`Case IPR 2014-00418
`Patent 5,500,819
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`APPEARANCES:
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`ON BEHALF OF THE PATENT OWNER:
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`LORI A. GORDON, ESQUIRE
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`CHRISTIAN CARMARCE, ESQUIRE
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`Sterne, Kessler, Goldstein, Fox
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`1100 New York Avenue, N.W.
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`Washington, D.C. 20005
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`ON BEHALF OF THE PETITIONER:
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`KEVIN HAMILTON, ESQUIRE
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`GIANNI MINUTOLI, ESQUIRE
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`GERALD T. SEKIMURA, ESQUIRE
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`DLA Piper LLP
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`One Fountain Square
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`11911 Freedom Drive
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`Suite 300
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`Reston, Virginia 20190
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`Case IPR 2014-00418
`Patent 5,500,819
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` P R O C E E D I N G S
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`JUDGE JEFFERSON: Good afternoon. We are here for
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`IP2014-00418 in the matter of Toshiba, et al., versus Intellectual
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`Ventures. I will quickly let you know that we have a new judge with
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`us on panel, Jacqueline Wright Bonilla is here with us today. Judge
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`Turner had a sudden illness and was unable to make the hearing, but
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`we will certainly proceed and go forward on all the issues. If you give
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`us a quick moment, I want to make sure I'm all up to speed here.
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`And the parties have an hour per side. You have been here
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`before. And so if you will reserve your time, petitioner, at the end for
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`rebuttal, please let us know and we'll let you know how close you are.
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`And I'll say that the patent owner has an hour reserved as well. I will
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`try to use the marker. If not, I will let you know. But I think we are
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`ready to start when you are.
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`MR. HAMILTON: Good afternoon, Your Honors. Would
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`you like a paper copy?
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`JUDGE JEFFERSON: I actually will take a paper copy.
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`MR. HAMILTON: May I approach?
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`JUDGE JEFFERSON: Yes, please.
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`MR. HAMILTON: Good afternoon. My name is Kevin
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`Hamilton from DLA Piper on behalf of petitioner, Toshiba
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`Corporation. With me is Gianni Minutoli, who is the lead counsel in
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`this matter, and also with me is Gerald Sekimura, both from DLA
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`Case IPR 2014-00418
`Patent 5,500,819
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`Piper. I would like to reserve 20 minutes of rebuttal time, if that's
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`okay.
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`JUDGE JEFFERSON: Okay. And you may begin.
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`MR. HAMILTON: So pulling up the slides here of the
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`petitioner's demonstratives and I want to look at slide number 2.
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`Slide 2 reminds us that the Board instituted this trial on the grounds
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`that the petitioner has a reasonable likelihood of showing claims 1
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`through 11 and 17 through 19 of the '819 patent are obvious over the
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`combination of three prior art references by the same inventor, the
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`Ogawa '577 reference, the Ogawa '045, and the Japanese Ogawa
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`application ending in '832.
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`Before I turn to slide 3, I want to give you an overview of
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`what I hope to do today. First, I would like to review the disclosure of
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`the '819 patent so that we all are talking about the same thing and to
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`briefly review some context building comments that were made
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`during the prosecution by the applicant. I would like to review the
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`claims of the patent, because as we all know, to determine the scope
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`of the patent, the court looks at the claims. I want to look at the patent
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`owner's argument which hinges completely upon convincing this
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`panel to read limitations of a preferred embodiment into the claim.
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`And finally, I would like to look at the Ogawa references to see how
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`their combination renders the challenged claims of the '819 patent
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`obvious.
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`Go ahead and turn to slide 3. Here in slide 3 we are looking
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`at a portion excerpts of the '819 patent specification. The '819 patent
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`Case IPR 2014-00418
`Patent 5,500,819
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`discloses "circuit systems and methods for improving page access and
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`blocked transfers in a memory system." It's the title of the patent. It's
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`also the first sentence of the specification. The specification discloses
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`circuitry intended to improve page accesses and blocked transfers.
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`As shown in the underlying sections on the left-hand side of
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`slide 3, the specification discloses some well-known circuit elements
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`such as an array of memory cells, address to code circuitry, sense
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`amplifiers and even though it's not shown here, also control circuitry.
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`The background section of the specification confirms that
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`memory arrays, address decoding circuity, sense amplifiers and
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`controllers were all well known in the art at the time the '819 patent
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`application was filed.
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`We turn to slide 4, in the underlying portion on the left-hand
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`side we have an excerpt from the '819 patent specification. The
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`underlying portion shows that the memory disclosed in the '819
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`specification also discloses -- also contains at least two sets of
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`latching circuitry that are coupled to the master sense amplifiers.
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`Each of the disclosed memory elements is shown in the embodiment
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`depicted in the Figure 2 of the '819 patent which is shown on slide 5.
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`Here on slide 5, we see Figure 2 from the '819 patent. We
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`see a conventional end-by-end array of memory cells, a conventional
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`row decoder 205 up on the top left, on the left of the memory array.
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`On the bottom we see a conventional column decoder labeled 213.
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`We see below the memory array are conventional sense amplifiers
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`Case IPR 2014-00418
`Patent 5,500,819
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`coupled with the bit lines and memory array. And we see a sort of
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`control circuitry scattered around the figure.
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`So Figure 2 also shows two banks of slave sense amplifiers,
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`and those are shown in Figure 5 within the red box annotations. And
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`one of the issues we are here to discuss today is whether or not those
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`two banks of slave sense amplifiers 210 and 211 were, in fact, novel.
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`The prosecution history shows that having banks of latching
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`circuits coupled with sense amplifiers are not novel and the examiner
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`rejected the claims as originally filed over the Kanbara reference that
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`discloses the same circuit elements.
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`However, in an office action that rejected the claims, the
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`examiner noted that, quote, the prior art does not disclose reading a
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`section of the cell array selected by a row decoder into a slave sense
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`amps through master sense amps and shifting and writing the same
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`data into another section of the array.
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`During prosecution, the applicant embraced the examiner's
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`words and actually repeated them in the applicant's response to the
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`office action, as we see on slide 6. Slide 6 shows an excerpt of the
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`applicant's remarks made during the prosecution. It's very important
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`to understand what is said here and what is not. The applicant
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`endorsed the examiner's assertion that the prior art of record in the
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`examination doesn't disclose two things. And those two things are
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`shown here in the underlying section of slide 6. The first two lines
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`show that the applicant and the examiner agreed that the prior art does
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`not disclose reading data from cell array into slave sense amps
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`Case IPR 2014-00418
`Patent 5,500,819
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`through the master sense amplifiers. And in the second portion
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`shifting and writing the same data into another section of the array
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`through the master sense amplifiers. That's it. That's what was
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`agreed.
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`Here what the examiner did was he signaled to the applicant
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`that the claims can be drafted relatively broadly because all they had
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`to recite to escape anticipation by the prior are record in the
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`examination was that the same data that is read from the array be
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`written back to the array through the same sense amplifiers, through
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`the master sense amplifiers.
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`As the underlying passage notes, data can be shifted before
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`sending it back to the array. To avoid the prior art, the applicant didn't
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`have to limit how the data was written back to memory, where it must
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`go or what path it must take on the way back to the array. The only
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`limitation is that the same data be written back to memory. That is
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`how the applicant drafted the claims, as we'll see in the next couple of
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`slides.
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`However, the point is if the applicant wanted the challenged
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`claims to include the limitation that data be transferred from the
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`master sense amplifiers to a specific slave sense amplifier and then
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`from that specific slave sense amplifier directly back to the array, the
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`applicant could have drafted the claims that way. They didn't. Instead
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`they chose to draft the challenged claims as broadly as the examiner
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`indicated would be allowable. Let's look at an example in claim 1 on
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`slide 7.
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`Patent 5,500,819
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`So on slide 7, claim 1 recites memory array, addressing
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`circuitry, master read/write circuity, first and second slave circuity,
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`control circuitry. Claim control circuitry is operable. The control
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`sensing by the master read/write circuitry. Control the transfer of
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`sense data when the master read/write circuitry to a selected one of the
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`first and second slave circuitry.
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`Most important is the last clause which is underlined here on
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`the bottom left of slide 7. This is the writing clause. The writing
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`clause uses the broad language that was endorsed by the examiner.
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`The writing clause requires only that the control circuitry, control
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`writing of said data through the master read/write circuitry to a second
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`row in the array.
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`I'll highlight for those of you that can see it, this portion here
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`on lines -- well, in the last clause. The writing clause of claim 1
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`where it says writing of said data, and my highlighting is not very
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`straight. But that's the portion that I have highlighted.
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`So this is the broad scope that was defined, that was
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`identified by the examiner. If we look back actually at claim 6 or
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`slide 6, excuse me, and we see here and I'll highlight here on the third
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`line that is underlined, the portion that says the same data, writing the
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`same data.
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`JUDGE JEFFERSON: So counsel, I don't think patent
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`owner disputes that it's the same data. The issue seems to be whether
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`it's the same or different slave/latch circuitry that's at issue. So
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`Case IPR 2014-00418
`Patent 5,500,819
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`turning to slide 7, is it your position that the same latch circuitry is not
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`required or cited as a limitation in the claim?
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`MR. HAMILTON: That's my position. The claim language
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`is clear. All that is required is that the writing of the data has to be
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`controlled so that it's written to the memory array through the master
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`slave -- the master sense amplifiers. That's all the claim requires. It
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`doesn't say anything about the data having to be written directly from
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`the same slave sense amplifiers back to the array.
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`JUDGE JEFFERSON: So if I look at the clause before the
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`control transfer of said data from said master read/write circuitry to a
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`selected one of said first and second slave circuitry, do you agree with
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`patent owner that that clause limitation requires it to be stored in this
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`particular location?
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`MR. HAMILTON: Yes. The control transfer of said data
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`clause requires a choice between first slave circuit or second slave
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`circuit and the data stored in one of those. But the next clause just
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`says the data, whatever that data was --
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`JUDGE JEFFERSON: The same data.
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`MR. HAMILTON: Has to be the same data, then that data,
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`that same data has to be written back to the array. But the claim says
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`nothing about the path that the data has to take on the way.
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`This claim, the way that it's written is broad enough so that
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`the data can be written to another slave sense amplifier and then
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`written back to the array through the master sense amplifier.
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`Case IPR 2014-00418
`Patent 5,500,819
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`JUDGE McKONE: Is there any disclosure in the
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`specification of that happening?
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`MR. HAMILTON: There is not.
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`JUDGE McKONE: So you agree that the only description --
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`MR. HAMILTON: I'm sorry. Let me take that back. So
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`what there is, and we are going to discuss this later with respect to
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`claim 17 and 18, claim 17 recites similar language even though it's a
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`little bit broader. But in claim 17, the data is written to a bank of
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`slave sense amplifiers. And then the data is then shifted to different
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`slave sense amplifiers through different sets, a different set of slave
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`sense amplifiers and then written from those slave sense amplifiers
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`back to the array through the master sense amplifier.
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`So, yes, there is a disclosure in the specification that the data
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`transfer does not have to be direct from the selected one of the pair of
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`slave sense amplifiers back to the array.
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`JUDGE McKONE: So this is disclosure that's in claim 17?
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`MR. HAMILTON: It's a combination of 17 and 18. The
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`shifting process is claimed in claim 18.
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`JUDGE McKONE: Is there any disclosure in the written
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`description portion of the specification?
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`MR. HAMILTON: So the written description portion of the
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`specification is a very detailed description of one transfer that does
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`something a little bit different where the data is transferred from
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`memory to the master sense amplifier, from the master sense amplifier
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`to one of the selected two, the selected one of the two slave sense
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`Case IPR 2014-00418
`Patent 5,500,819
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`amplifiers and then from the selected slave sense amplifiers back to
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`the memory through the master sense amplifiers. That is the
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`description of the data transfer that is in the specification. And this
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`JUDGE McKONE: There's only one example given?
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`There's not a second example? I just want to make sure I understand
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`the full scope of the specification.
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`MR. HAMILTON: So column 8 of the specification also
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`discloses the shifting operation. So there is an alternative that shows
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`shifting before data is moved back.
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`JUDGE McKONE: Okay.
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`MR. HAMILTON: So the patent owner, looking again here
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`at slide 7, wants you to read this writing clause to require an
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`additional circuitry. The patent owner wants you to read the last
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`clause to contain an additional limitation. After the controlling --
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`control writing of said data portion -- after the word "data" in the
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`final -- in the writing clause of claim 1, the patent owner wants you to
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`insert language so that the claim reads -- it's the same up there.
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`Control writing of said data, but then between data and through, the
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`patent owner wants you to insert from said selected one of said first
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`and second slave circuitry directly, and then it picks up, through said
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`master read/write circuitry to a second said row of said array. In other
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`words, the patent owner wants you to read a very specific limitation
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`that is simply not recited in the claims.
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`Patent 5,500,819
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`Independent claim 7 recites the same language as here in
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`claim 1 and the same argument applies. Let's go ahead and look at
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`claim 17 in slide 8. Claim 17 recites method steps that correspond to
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`the elements that were recited in claim 1, including selecting a row in
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`the array, sensing read data with master sense amplifiers, latching the
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`sense data in a bank of slave sense amplifiers and then writing the
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`data to different cells in the array through the master sense amplifier.
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`In the writing step, which is underlined here at the end of
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`claim 17 in the middle of the left-hand side of slide 8, the applicant
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`drafted the claims according to the broad language that was endorsed
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`by the examiner. But what we have to recognize is that claim 17 is
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`even broader than claims 1 and 7. Claims 1 and 7 recite separate first
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`and second banks of slave sense amplifiers. But here claim 17 only
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`recites a bank of slave sense amplifiers.
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`It's in the latching. The A bank of slave sense amplifiers
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`recitation is in the latching element which is the second-to-last
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`element of the claim. As we all know, a bank of slave sense
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`amplifiers should be interpreted to mean one or more banks of slave
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`sense amplifiers. In contrast, the embodiment shown in figure 2 and
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`described in the specification has two banks of slave sense amplifiers.
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`I'll point you back to slide 5, and here on slide 5 we are
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`looking at Figure 2 of the '819 patent specification. Here, clearly
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`shown and described in specification, are two banks of slave sense
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`amplifiers. So I'm going to go back to slide 8. This limitation of two
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`or more or of two slave sense amplifiers is not in claim 17. Claim 17
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`Patent 5,500,819
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`is demonstrably broader than the embodiment in the specification and
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`depicted in Figure 2 and therefore, claim 17 is not limited to the
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`disclosed embodiment.
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`The claim language of the claim requires that the data be
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`written to different cells in an array through the master sense
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`amplifiers. The claim as drafted allows the data latched and the slave
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`sense amplifiers to be written to a different set of slave sense
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`amplifiers and written from the different set of slave sense amplifiers
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`through the master sense amplifiers and to the array.
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`As I discussed before, this is exactly what happens in claim
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`18. Claim 18 as shown in the bottom left of slide 8 recites the method
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`of claim 17 wherein the writing step comprises shifting the data
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`within the slave sense amplifiers from the first selected set of slave
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`sense amplifiers to a second selected set of slave amplifiers and then
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`writing the data from the second set of slave amplifiers back to the
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`array. Therefore, claim 18 tells us that the data is latched in the bank
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`of slave sense amplifiers and the data can be moved before it is
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`written through the master slave sense amplifiers and back to the
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`array.
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`This is where Dr. Huber's argument falls apart. Dr. Huber
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`argues that the '819 patent improves page accesses and blocked
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`transfers using the same bank of slave sense amplifiers and he always
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`emphasized the word "same" because an intermediate transfer through
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`a different bank of slave sense amplifiers would cause unwanted
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`delay, thereby thwarting the purported advantages of the invention.
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`Case IPR 2014-00418
`Patent 5,500,819
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`Claim 18 tells us that putting another register or even more
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`than one register in the path that the data takes back to the array just
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`doesn't matter.
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`Let's turn to --
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`JUDGE JEFFERSON: Counsel, does the written
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`description describe the transfer, the latching shift transfer method
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`that is claimed in claim 18?
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`MR. HAMILTON: It does. It's in column 8, I think. Yes, it
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`describes an alternative -- it's on lines 1 through 13 of column 8.
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`There's an alternative transfer in which the data is shifted.
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`So looking at slide 9, slide 9 outlines the patent owner's
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`argument. The patent owner attempts to read the limitation -- a
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`limitation that was clearly disclosed in an embodiment into the claims.
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`Patent owners argues that the limitation is the very thing that gives the
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`patented invention its advantage even though neither that advantage or
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`the limitation is recited in the claims. Patent owner concludes that
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`this limitation must be read into the claims because the limitation is
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`the basis of the purported advantage.
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`Specifically, the patent owner argues the advantage of
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`efficient blocked move/copies provided by the patented invention is
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`provided "using the same bank of slave circuitry" to write the data
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`back to memory. And again, they emphasize same with bold and
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`italics.
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`Case IPR 2014-00418
`Patent 5,500,819
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`There's three issues with this. First, the specification never
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`credits the use of the same slave circuitry with providing any
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`advantage. That's just something that Dr. Huber cooked up.
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`Second, it's not even true. The patent owner's slides 4 and 5
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`help us to see why. Let me show you patent owner's slide 5. I have
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`brought up patent owner's slide 5. Are you looking at that, Judge
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`McKone?
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`JUDGE McKONE: Yes.
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`MR. HAMILTON: So patent owner's slide 5 recites -- sorry
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`about that. Technical difficulties. Patent owner's slide 5 cites a
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`portion of the '819 patent specification, in particular column 2, lines
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`40 through 80. So there's an underlying portion shown here and I'll
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`just read it. It says, In the speed of presently available bit block
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`transferring systems is limited by the fact that such systems move or
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`copy data from one address space to another address space in memory
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`on a byte or word basis.
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`So what the specification is saying here is that prior to the
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`'819 patent, you had -- to perform a bit block transfer, you had a
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`memory array and you had to perform full memory reads followed by
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`full memory writes and repeat those reads and writes successfully in
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`order to achieve a bit block transfer. Reading the data all the way out
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`of the array is time consuming.
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`And so the specification goes on. It says, thus, the need has
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`arisen for improved circuits, systems and methods for implementing
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`bit block transfers. In particular, such methods, systems and circuits
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`Case IPR 2014-00418
`Patent 5,500,819
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`should be applicable to the movement and/or copying of pixel data --
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`and here is the important part -- within the frame buffer of a display
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`system. Within the frame buffer, the data in order to achieve better bit
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`block transfers, you move the data within the system rather than pull
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`the data all the way back out and move it back in.
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`If we look at the previous slide, slide 4 of the patent owner's
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`demonstratives, we are looking here at the title page of the '819 patent
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`and there's a figure here that shows the frame buffer they are talking
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`about. The frame buffer is labeled 104.
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`Now, in the old methodology bit block transfers required
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`data to be moved all the way outside the frame buffer and all the way
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`back in, one byte or one word at a time.
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`The frame buffer shown here contains the memory array,
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`contains the master sense amplifiers, contains the slave sense
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`amplifiers and everything else. And so if I look back here at the next
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`page, at slide 5 of patent owner's demonstratives, really what they did
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`was they kept the transfer internal. It was within the same buffer.
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`There's no requirement here that moving the data within the same --
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`within the frame buffer requires the use of the same slave sense
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`amplifier circuitry.
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`So the third issue with the patent owner's argument is that
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`patent owner's advantage argument is simply irrelevant. I'm going to
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`slide back to slide 9 of the petitioner's demonstratives. So the federal
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`circuit has said that when analyzing the enabled scope of a claim, the
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`teachings of the specification must not be ignored because claims are
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`Case IPR 2014-00418
`Patent 5,500,819
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`to be given their broadest reasonable interpretation that is consistent
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`with the specification.
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`However, the federal circuit has also said that, quote, that
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`claims are interpreted in light of the specification does not mean that
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`everything in the specification must be read into the claims. The
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`federal circuit has held that it is improper to read limitations from a
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`preferred embodiment described in the specification, even if it is the
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`only embodiment, into the claims absent the clear indication in the
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`intrinsic record the patentee intended the claim to be so limited.
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`There's no evidence whatsoever in the record the patentee
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`intended to limit the claims, the challenged claims to the embodiment
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`shown in Figure 2 and described in the specification. Therefore, even
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`if the advantage is provided by using the same slave sense amplifiers,
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`the argument is irrelevant because the limitation is not recite in the
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`claims.
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`With all this in mind, let's go ahead and turn to slide 10 and
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`look at how the Ogawa references render the challenged claims
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`obvious.
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`Slide 10 shows Figure 2 of Ogawa '577 on the left and on
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`the right we see claims 1 and 17 recite having an array of volatile
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`memory cells organized in rows and columns, the rows associated
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`with word lines and the columns associated with the bit line. It's not
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`disputed that Ogawa '577 discloses the memory array as shown at the
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`intersections of the row and bit lines in Figure 2.
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`Case IPR 2014-00418
`Patent 5,500,819
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`In slide 11, slide 11 shows Figure 6 of Ogawa '577 on the
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`left and the addressing circuitry in selecting the row elements of
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`claims 1 and 17, respectively, on the right. I don't think there's any
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`argument Ogawa '577 does not disclose these elements.
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`Moving on to slide 12, slide 12 shows the master read/write
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`circuitry and sensing the bit lines elements of claims 1 through 17
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`respectively. Again, there's no controversy.
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`Slide 13. Slide 13 contains the first slave circuitry and
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`second slave circuitry elements that are unique to claim 1. The '819
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`patent refers to slave sense circuitry as latching circuits. I don't
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`believe there's any argument the Ogawa '577 reference does not
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`disclose first and second slave circuitry.
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`On slide 14 we see Figure 2 of Ogawa '577 on the left,
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`transfer gates 21 and 22 shown within the red rectangle annotation.
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`On the right we see the claim 1 element that reads, Control circuitry
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`for controlling exchange of data between said master read/write
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`circuitry and said first and second slave circuitry.
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`Transfer gates 21 and 22 are circuits for controlling the
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`exchange of data between the master read/write circuitry and the first
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`and second slave circuitry shown there on the left of Figure 2 in the
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`form of shift registers. This is not disputed.
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`The transfer gates 21 and 22 are switched by the control
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`signals that are shown driving the gate and puts in the transistors
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`forming transfer gates 21 and 22 within the red box annotation. This
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`is not disputed. One of ordinary skill in the art would have
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`Case IPR 2014-00418
`Patent 5,500,819
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`understood that control circuitry was required to generate those
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`control circuits, those control signals. To enable the correct transfer
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`of data between the sense amplifiers and the shift registers, that is not
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`disputed.
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`What is disputed is this. Page 36 of patent owner's response
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`reads, Toshiba's inherency argument fails because the recited control
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`circuitry can be outside of the Ogawa memory system. To support
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`this argument, patent owner arbitrarily draws a box around Figure 2 of
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`Ogawa '577, draws control circuitry outside that box and argues that
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`the box drawing exercise proves their point. However, there's no
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`limitation in the claim that requires that the control circuitry be within
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`any specific boundary of the memory system.
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`Control circuitry for controlling the exchange of data must
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`exist and must be part of the overall system. And also, since Ogawa
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`'577 would not function without the recited control circuitry, the
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`control circuitry must be within the overall system.
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`JUDGE McKONE: Now, is your argument limited to
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`inherency here or did you also argue that the placement in the circuit,
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`should we require it to be within the boundaries that patent owner
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`would draw, it nevertheless would have been obvious to put this
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`circuitry in those boundaries?
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`MR. HAMILTON: The latter. We argue that it nevertheless
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`would have been obvious to put the control circuitry within the
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`boundaries.
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`Case IPR 2014-00418
`Patent 5,500,819
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`JUDGE McKONE: Could you show me where that is in the
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`petition, please.
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`MR. HAMILTON: So it's stated here in paragraph 23 of
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`Mr. Murphy's declaration that accompanied the petition.
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`JUDGE McKONE: Is it in the petition itself?
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`MR. HAMILTON: It's in the petition on page 16. So the
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`idea that the control circuitry would be within that particular argument
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`is not made in the petition because -- it was made implicitly in the
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`petition because we said that it was inherent. But the idea --
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`JUDGE McKONE: Inherency is different than obviousness.
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`MR. HAMILTON: That's correct.
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`JUDGE McKONE: I see in the petition here where you
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`cited me is inherency.
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`MR. HAMILTON: So in the petition on -- if you don't
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`mind, we would like to take a moment. My co-counsel will take a
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`moment to look at it. Can we return to this?
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`JUDGE McKONE: That's fine with me. However you want
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`to handle it.
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`MR. HAMILTON: Thank you. Appreciate it.
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`So let's turn to slide 15. Slide 15 we see Figure 2 of Ogawa
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`'577 on the left. On the right we see limitation of control circuitry,
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`control sensing by the master read/write circuitry. Figure 2 of Ogawa
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`'577 has a bank of master sense amps 101 through 108. And one of
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`ordinary skill in the art would understand that control circuitry is
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`required to synchronize the operation of the sense amps with the
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`Case IPR 2014-00418
`Patent 5,500,819
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`memory array in the other circuitry. Therefore, Ogawa '577
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`inherently discloses the recited circuitry.
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`On slide 16 we see the Figure 2 of Ogawa '577 shown on the
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`left. On the right we see limitations of claims 1 and 17, the control
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`circuitry control transfer of data from the master read/write circuits to
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`the first or second slave circuitry. This limitation is almost identical
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`to claim element 1F we discussed a few minutes ago. As we
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`discussed with respect to that claim element 1F, Figure 2 of Ogawa
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`'577 shows transfer gates 21 and 22 within the red box limitation.
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`7
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