Trials@uspto.gov
`Tel: 571-272-7822
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`
`
`
`Paper 28
`Entered: August 7, 2015
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_______________
`
`TOSHIBA CORPORATION, TOSHIBA AMERICA, INC.,
`TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.,
`and TOSHIBA AMERICA INFORMATION SYSTEMS, INC.,
`Petitioner,
`
`v.
`
`INTELLECTUAL VENTURES II LLC,
`Patent Owner.
`_______________
`
`Case IPR2014-00418
`Patent 5,500,819
`_______________
`
`
`
`Before JACQUELINE WRIGHT BONILLA, TREVOR M. JEFFERSON,
`and DAVID C. McKONE, Administrative Patent Judges.
`
`JEFFERSON, Administrative Patent Judge.
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
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`

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`IPR2014-00418
`Patent 5,500,819
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`I. INTRODUCTION
`
`A. Background
`
`Toshiba Corporation, Toshiba America, Inc., Toshiba America Electronic
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`Components, Inc., and Toshiba America Information Systems, Inc. (collectively,
`
`“Petitioner”) filed a Petition (Paper 1, “Pet.”) to institute an inter partes review of
`
`claims 1–11 and 17–19 of U.S. Patent No. 5,500,819 (Ex. 1001, “the ’819 patent”).
`
`See 35 U.S.C. § 311. Intellectual Ventures II LLC (“Patent Owner”) filed a
`
`Preliminary Response (Paper 6, “Prelim. Resp.”). Pursuant to 35 U.S.C. § 314, in
`
`our Decision to Institute (Paper 7, “Dec.”), we instituted this proceeding as to
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`claims 1–11 and 17–19 of the ’819 patent. Dec. 19.
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`Patent Owner filed a Patent Owner Response (Paper 15, “PO Resp.”) and
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`Petitioner filed a Corrected Petitioner’s Reply to Patent Owner’s Response
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`(Paper 23, “Reply”). An oral hearing in this matter was held on May 6, 2015
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`(Paper 27, “Tr.”).
`
`We have jurisdiction under 35 U.S.C. § 6(c). This Final Written Decision is
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`issued pursuant to 35 U.S.C. § 318(a) and 37 C.F.R. § 42.73. For the reasons that
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`follow, Petitioner has demonstrated by a preponderance of the evidence that claims
`
`1–11 and 17–19 of the ’819 patent are unpatentable.
`
`B. Related Matters
`
`Patent Owner has sued Petitioner for infringement of the ’819 patent in
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`Intellectual Ventures I LLC v. Toshiba Corp., No. 1:13-cv-00453 (D. Del.). Pet. 1;
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`Paper 5 (Patent Owner’s Mandatory Notices).
`
`C. The ’819 Patent
`
`The ’819 patent, titled “Circuits, Systems and Methods for Improving Page
`
`Accesses and Block Transfers In A Memory System,” issued on March 19, 1996,
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`IPR2014-00418
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`and addresses control circuitry that controls the exchange of data between
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`read/write circuitry and first and second slave circuitry. Ex. 1001, Abstract. The
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`’819 patent discloses circuits for improving page accesses and block transfers in
`
`memory. Id. at 1:7–10. The “invention provide[s] for the construction of a
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`memory which includes an array of volatile memory cells, address decode circuitry
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`for selecting rows and/or columns of cells in the memory array, and master sense
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`amplifier circuitry for reading and writing data into those selected cells.” Id. at
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`2:52–57. The invention also includes “[a]t least two sets of latching circuitry . . .
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`coupled to the master sense amplifiers for temporarily storing data being
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`exchanged with the master sense amplifiers during read and write operations to the
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`array of memory cells.” Id. at 2:57–61.
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`Figure 2 of the ’819 patent, shown below, provides an exemplary block
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`diagram of the memory system disclosed.
`
`Figure 2 depicts a block diagram of memory system 200 with an M x N array of
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`flash memory cells 201, with wordlines (rows) 203 and bitlines (columns) 204.
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`Id. at 5:52–57, 3:25–26. Representative memory cell 202 is located at the
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`intersection of wordline 203 and bitline 204. Id. at 5:58–60. “[Bitlines] 204 of
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`memory array 201 are coupled to a bank 208 of master sense amplifiers,” which
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`are coupled via “bus 209 to a first bank 210 (bank 1) of slave sense amplifiers and
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`a second bank 211 (bank 2) of slave sense amplifiers.” Id. at 6:8–12. “Slave sense
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`amplifier banks 210 and 211 are further coupled by a local data I/O bus 212 to
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`column decoder circuitry 213.” Id. at 6:12–14. The challenged claims are directed
`
`to a memory that includes control circuitry that controls the sensing of data from
`
`cells via the master sense amplifiers, the temporary storage of those data in the first
`
`and second bank of slave sense amplifiers, and the rewriting of those data back in
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`the memory array at the same or different locations.
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`D. Illustrative Claims
`
`
`
`Illustrative independent claims 1, 7, and 17 (Ex. 1001, 8:20–44 (claim 1),
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`8:60–9:20 (claim 7), 11:8–12:3 (claim 17)) are reproduced below:
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`1. A memory comprising:
`
`an array of rows and columns of volatile memory cells;
`
`addressing circuitry for providing access to selected ones
`of said memory cells;
`
`master read/write circuitry for reading and writing data
`into said selected ones of said cells;
`
`first slave circuitry for storing data for exchange with
`said master read/write circuitry;
`
`second slave circuitry for storing data for exchange with
`said master read/write circuitry; and
`
`control circuitry for controlling exchange of data between
`said master read/write circuitry and said first and
`second slave circuitry, said control circuitry
`operable during a move operation to:
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`IPR2014-00418
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`control sensing by said master read/write circuitry of data
`from a said row in said array selected by said
`addressing circuitry;
`
`control transfer of said data from said master read/write
`circuitry to a selected one of said first and second
`slave circuitry; and
`
`through said master
`control writing of said data
`read/write circuitry to a second said row in said
`array selected by said addressing circuitry.
`
`7. A memory system comprising:
`
`an array of memory cells arranged in rows and columns,
`each said row associated with a conductive
`wordline and each said column associated with a
`conductive bitline;
`
`a row decoder coupled to said wordlines;
`
`a bank of master sense amplifiers coupled to said bitlines;
`
`a plurality of banks of slave sense amplifiers coupled to
`said master sense amplifiers;
`
`a column decoder coupled to each of the plurality of
`banks of slave sense amplifiers; and
`
`control circuitry coupled to said row decoder, said bank
`of master sense amplifiers and said banks of slave
`sense amplifiers, said control circuitry including
`mode control circuitry coupled to said row decoder
`and said master sense amplifiers and multiplexer
`control circuitry coupled to said mode control
`circuitry and said plurality of banks of slave sense
`amplifiers, said control circuitry operable during a
`move operation to:
`
`control sensing by said master sense amplifiers of data
`from a said row in said array selected by said row
`decoder;
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`IPR2014-00418
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`control transfer of said data from said master sense
`amplifiers to a selected one of said banks of slave
`sense amplifiers;
`
`control writing of said data through said master sense
`amplifiers to a second said row in said array
`selected said row decoder.
`
`17. A method of performing a block transfer within a
`memory including an array of memory cells
`arranged in rows and columns, each said row
`associated with a conductive wordline and each
`said column associated with a conductive bitline,
`comprising the steps of:
`
`selecting a row in the array;
`
`sensing the bitlines of the array to read data stored in the
`cells of the selected row with a bank of master
`sense amplifiers;
`
`latching the data read from the cells of the selected row
`in a bank of slave sense amplifiers;
`
`writing the data stored in the slave sense amplifiers
`through the master sense amplifiers to different
`cells in the array.
`
`E. The Asserted Ground
`
`We instituted trial on the ground alleging that claims 1–11 and 17–19 are
`
`unpatentable under 35 U.S.C. § 103(a) as obvious over Ogawa ’577,1 Ogawa
`
`’045,2 and JP ’832.3 Dec. 19.
`
`
`1 Ex. 1003, Ogawa, US 4,745,577, issued May 17, 1988, filed Nov. 15, 1985
`(“Ogawa ’577”).
`2 Ex. 1005, Ogawa, US 4,773,045, issued Sept. 20, 1988, filed Oct. 16, 1985
`(“Ogawa ’045”).
`3 Ex. 1006, Ogawa, Japanese Patent Application H3-46832, published July 17,
`1991 (Japan priority application 59-245802 for Ogawa ’577) (“JP ’832”).
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`IPR2014-00418
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`II. ANALYSIS
`
`A. Claim Construction
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`The ’819 patent, which was filed September 30, 1994 and issued March
`
`1996, expired. See PO Resp. 13 n.1; Reply 4. “[T]he Board’s review of the claims
`
`of an expired patent is similar to that of a district court’s review.” In re Rambus,
`
`Inc., 694 F.3d 42, 46 (Fed. Cir. 2012). Because the expired claims of the patent are
`
`not subject to amendment, we apply the principle set forth in Phillips v. AWH
`
`Corp., 415 F.3d 1303, 1312 (Fed. Cir. 2005) (en banc) (quoting Vitronics Corp. v.
`
`Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996)), that “words of a claim
`
`‘are generally given their ordinary and customary meaning,’” as understood by a
`
`person of ordinary skill in the art in question at the time of the invention. “In
`
`determining the meaning of the disputed claim limitation, we look principally to
`
`the intrinsic evidence of record, examining the claim language itself, the written
`
`description, and the prosecution history, if in evidence.” DePuy Spine, Inc. v.
`
`Medtronic Sofamor Danek, Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006) (citing
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`Phillips, 415 F.3d at 1312–17).
`
`Petitioner asserts that claim terms should be given their ordinary and
`
`customary meanings, as the patentee did not act as a lexicographer or provide
`
`special meaning for any claim terms. Pet. 8. Patent Owner has not disputed
`
`Petitioner’s conclusion and provides no alternate construction for any claim terms
`
`on this record.
`
`Based on the present record, we determine that no express claim
`
`construction is necessary for any claim term for purposes of this Decision.
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`B. Asserted Prior Art
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`1. Ogawa ’577 (Ex. 1003)
`
`Ogawa ’577 describes “[a] semiconductor memory device with shift
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`registers used for a video RAM.” Ex. 1003, Abstract. Specifically, Ogawa ’577
`
`discloses “a memory cell array, bit lines, and word lines, a pair of shift registers,
`
`and transfer gate circuits arranged between the bit lines and the shift registers.” Id.
`
`Figure 2 of Ogawa ’577, reproduced below, shows a semiconductor memory
`
`device with shift registers. Id. at 2:10–12.
`
`
`
`Figure 2 of Ogawa ’577 shows “a dynamic RAM 1 of an open bit-line type, groups
`
`of transfer gates 21 and 22, and shift registers 3 and 4.” Id. at 3:19–21. Data are
`
`provided via input lines 32 and 42 of shift registers 3 and 4. Data also are
`
`delivered through output lines 33 and 43 from shift registers 3 and 4. Id. at 3:22–
`
`25. Figure 2 shows that “RAM 1 includes sense amplifiers 101, 102, . . . 10n”; “bit
`
`lines (BL) 111, 112, . . . 11n”; “word lines (WL) 131, 132, . . . 13n”; and “bit lines
`(BL̅̅̅̅) 121, 122, . . . 12n.” Id. at 3:29–36. Ogawa ’577 discloses that shift registers
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`3 and 4 can be used for reading and writing in various combinations for the parallel
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`transfer of data between registers and for a scroll display operation.
`
`2. JP ’832 (Ex. 1006)
`
`JP ’832 is a Japanese counterpart application to Ogawa ’577. Pet. 8;
`
`Ex. 1003, at [30] Foreign Application Priority Data; Ex. 1006, 1 (21) [Application
`
`Number]. JP ’832 discloses the use of shift registers to transfer data from cells in a
`
`selected row of a memory array to different cells in the selected row in the array.
`
`Ex. 1006, 10–11.
`
`JP ’832 relates to random access memory (RAM) equipped with a shift
`
`register for high-speed reading and writing. Ex. 1006, 8. Figure 1 of JP ’832 is
`
`shown below.
`
`
`
`Figure 1 of JP ’832 shows a block diagram of open-bit-line RAM 10 with two shift
`
`registers, SRA and SRB. Ex. 1006, 8–9. JP ’832 discloses a video RAM
`
`comprising two shift registers SRA, SRB used to write a row of data into memory
`cells at the intersection of wordlines (WL) and bitlines (BL and BL̅̅̅̅) of RAM
`
`memory array 10. Ex. 1006, 9–10. JP ’832 further discloses reading data from one
`
`portion of the array, storing that data in the shift registers SRA and SRB, and
`
`writing that data in parallel to a different portion of the array or wordline (WL).
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`Ex. 1006, 10–11. Specifically, JP ’832 discloses writing via the shift registers,
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`SRA and SRB, from one wordline to a new wordline in array 10. Ex. 1006, Fig. 6.
`
`Figure 6 of JP ’832 is shown below.
`
`
`
`
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`Figure 6 depicts shift registers SRA and SRB being used to transfer data from cells
`
`in a selected row WLi in memory array 10, to different cells in the selected row
`
`WLj in memory array 10 along with New Data inserted in a portion of shift
`
`register A. Ex. 1006, 10–11. Figure 6(a) discloses that data of WLi is transferred
`
`first to shift register SRB from DRAM 10. Figure 6(b) shows that WLi is then
`
`transferred from SRB to shift register SRA, where new data may be serially added
`
`from INA to SRA. Id. Figure 6(c) shows that the data of shift register SRA is
`
`transferred in parallel back to different wordline WLj, although “the transfer
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`destination may be WLi rather than WLj.” Ex. 1006, 9–10.
`
`3. Ogawa ’045 (Ex. 1005)
`
`Ogawa ’045 shares an inventor with Ogawa ’577 and JP ’832 and discloses a
`
`“semiconductor memory device including a RAM and shift register for enabling
`
`parallel transfer of a one-word line amount of data of the RAM portion between
`
`the RAM portion and the shift register.” Ex. 1005, Abstract. Specifically,
`
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`10
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`Ogawa ’045 discloses a VRAM memory circuit, that has a bit line/sense amplifier
`
`configuration like that of Ogawa ’577, and that writes data stored in a shift register
`
`1 to memory cells formed at the intersection of wordlines (“WL”) and bitlines
`(“BL” and “BL̅̅̅̅”) through “sense amplifiers No. 1 to No. 8” for “making either of
`the bit lines BL1 and BL1̅̅̅̅̅, BL2 and BL2̅̅̅̅̅, . . . an H (high) level and the other an L
`
`(low) level.” Ex. 1005, 3:56–58, 3:40–65. Figures 1A and 1B of Ogawa ’045 are
`
`provided below.
`
`
`
`Figures 1A and1B (collectively, Figure 1) illustrate a schematic of prior art video
`RAM that uses shift register (SR) to write to BL-2 or BL̅̅̅̅-2 via sense amplifiers
`
`(Sense Amp No. 2). Ex. 1005, 3:40–65, 2:40–41. Shift registers 101 to 108 are
`
`serial input shift registers. Id. at 2:67–3:1. The RAM of Figure 1 has eight pairs of
`bit lines BL-1 to BL-8 and BL̅̅̅̅-1 to BL̅̅̅̅-8. Id. at 3:2–4. The RAM also has eight
`
`sense amplifiers No. 1 to No. 8 arranged at the center of Figure 1. Id. at 3:5–7.
`The pairs of BL and BL̅̅̅̅ bitlines are connected through the sense amplifiers. Id. at
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`3:9–11.
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`C. Asserted Grounds of Unpatentability
`
`1. Obviousness of Claims 1–11 and 17–19 over Ogawa ’577
`(Ex. 1003), Ogawa ’045 (Ex. 1005), and JP ’832 (Ex. 1006)
`
`With respect to claims 1–6, Petitioner provides claim charts, as well as the
`
`Declaration of Robert Murphy (Ex. 1004), in support of its contention that the
`
`disclosure in Ogawa ’045 (Ex. 1005) teaches the common technique of using a
`
`sense amplifier on a bit line to write data stored in a shift register to either BL or
`BL̅̅̅̅. Pet. 24–25 (citing Ex. 1004 ¶¶ 32, 33); Ex. 1005, 3:40–65. Petitioner also
`
`contends that the combination of the disclosure in Ogawa ’577 with the techniques
`
`known to one of ordinary skill in the art as disclosed in Ogawa ’045 and JP ’832
`
`render claims 1–6 and 17–19 obvious. Pet. 24–25, 32–33, 34–36. With respect to
`
`claim 7–11, Petitioner provides claim charts showing the claim limitations and the
`
`corresponding disclosure in JP ’832. Pet. 38–59. Petitioner also provides
`
`argument and discussion regarding the disclosures of Ogawa ’045 and Ogawa
`
`’577, and citations to the Murphy Declaration (Ex. 1004 ¶¶ 40–84) supporting the
`
`argument that the cited references together render claims 7–11 obvious. Pet. 38–
`
`60.
`
`a. Scope of the Challenged Claims
`
`Patent Owner contends that the challenged independent claims are limited to
`
`a “move/copy operation …, which moves data to slave circuitry and then writes the
`
`data to memory using the same slave circuitry.” PO Resp. 12. Patent Owner
`
`further avers that the ’819 patent confers significant advantages over the
`
`Ogawa ’577 and JP ’832 data transfer methods, which insert an additional write
`
`operation from one bank of alleged slave circuitry to a different alleged bank of
`
`slave circuitry prior to writing data to the memory array. PO Resp. 2 (citing
`
`Ex. 2001, Declaration of William R. Huber, D.Sc., P.E., ¶¶ 33–34), 4. Relying on
`
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`12
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`the Declaration of Dr. Huber, Patent Owner argues that independent claims 1, 7,
`
`and 17 and the ’819 patent specification require that data is read from the memory
`
`array to a bank of slave sense amplifiers and then data is written from the same
`
`bank of slave sense amplifiers to the memory array. PO Resp. 7 (citing Ex. 2001
`
`¶ 32).
`
`Patent Owner’s arguments are not commensurate in scope with language in
`
`the claims themselves. Claim 1 recites sensing data by master read/write circuitry
`
`and transferring “said data” to one of two slave circuits and “writing of said data
`
`through said master read/write circuitry.” Ex. 1001, 8:35–43. Thus, claim 1
`
`requires writing “said data” back to memory through the master read/write
`
`circuitry, but does not require writing such data by use of the same slave circuit.
`
`Independent claim 7 has similar limitations. Id. at 9:15–20.
`
`Claim 17 requires writing “the data stored in the slave sense amplifiers”
`
`back to memory through the master sense amplifiers. Id. at 12:1–3. Specifically,
`
`claim 17 latches the data read from a selected row into “a bank of slave sense
`
`amplifiers” and “writ[es] the data stored in the slave sense amplifiers through the
`
`master sense amplifiers to different cells in the array.” Id. at 11:17–12:3. Here,
`
`claim 17 recites writing of the data “through the master sense amplifiers” and does
`
`not limit the writing only to the same bank of slave sense amplifiers. It is
`
`informative that claim 18, which depends from the broader independent claim 17,
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`explicitly recites a step of writing data from one set of slave sense amplifiers to a
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`second set of slave sense amplifiers and then writing that data into different cells in
`
`the array. In sum, data can be moved to a different slave sense amplifier before
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`being written back to the array to comply with independent claim 17 and
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`dependent claim 18.
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`Accordingly, we are not persuaded by Patent Owner’s argument that claim
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`17 is limited to the same data using the same slave sense amplifiers. We note that
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`Patent Owner’s Response fails to discuss the scope of claim 18, which depends
`
`from independent claim 17. See generally PO Resp. 43 (referencing challenged
`
`dependent claims). Patent Owner’s argument at the hearing that both claim 17 and
`
`claim 18 are limited to transfers of data within the same bank of slave sense
`
`amplifiers (Tr. 30:9–22) is not supported by the plain reading of the limitations
`
`(Ex. 1001, 11:17–12:3).
`
`In addition, Patent Owner’s arguments that independent claims 1, 7, and 17,
`
`are limited to the same data using the same sense amplifiers improperly read
`
`limitations from the specification into the claims. See Thorner v. Sony Comput.
`
`Entm’t Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012). Patent Owner’s
`
`arguments rely heavily on the ’819 patent’s description of the so-called
`
`“move/copy” operation using the same slave circuitry. See PO Resp. 1–7
`
`(discussing advantages of move/copy operation). Limitations should not be
`
`imported from preferred embodiments into the claims absent a clear disclaimer of
`
`claim scope in the specification. See In re Am. Acad. of Sci. Tech Ctr., 367 F.3d
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`1359, 1369 (Fed. Cir. 2004). Patent Owner has not identified such a clear
`
`disclaimer of claim scope in the specification of the ’819 patent.
`
`Patent Owner argues that the specification as a whole excludes or disavows
`
`the interbank transfer among the slave circuitry in the copying of data back into the
`
`array. Tr. 41:24–42:17. Patent Owner has not shown, however, that the intrinsic
`
`evidence limits the independent claims to copying data using the same slave
`
`circuitry (or slave sense amplifiers). Indeed, for example, the file history shows
`
`that the Applicant amended the independent claims by adding the copying and
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`slave sense amplifier limitations at issue, and described the amendment as being
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`directed to writing the same data back through associated slave circuitry, but not
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`expressly requiring the same slave circuitry. Ex. 1002, 49–52, 55–56, 59–60. As
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`stated above, claims 1, 7, and 17 recite that the data is written to the array
`
`“through” the sense amplifier. We are not persuaded that claims 1, 7, and 17 are
`
`limited to copying of data using only the same sense amplifiers.
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`Finally, we also are not persuaded by Patent Owner’s argument that
`
`Petitioner’s expert, Dr. Murphy, agrees that the scope of claim 1 is limited to use
`
`of the same slave circuitry. PO Resp. 14 n.8 (citing Ex. 1002, 32:14–33:14);
`
`Tr. 35:18–36:22. We find that Dr. Murphy’s testimony merely addresses the
`
`description of the ’819 patent specification (Ex. 1002, 32:14–33:14) and not the
`
`scope or interpretation of claim 1. We do not agree with Patent Owner’s argument
`
`that the embodiments and general description of the ’819 patent limit the claims to
`
`use of the “same” sense amplifier for the copy functions. Accordingly, we
`
`conclude that independent claims 1, 7, and 17 do not require copying of the data
`
`using the same slave circuitry.
`
`b. The Prior Art
`
`Petitioner contends that the combination of the disclosure in Ogawa ’577
`
`with the techniques known to one of ordinary skill in the art, as disclosed in
`
`Ogawa ’045 and JP ’832, renders claims 1–6 and 17–19 obvious. Pet. 24–25, 32–
`
`33, 34–36. Petitioner cites the Murphy Declaration in support of the understanding
`
`of one of ordinary skill in the art with respect to the cited references. Pet. 28–38
`
`(citing Ex. 1004 ¶¶ 20, 26, 27, 32–36, 38, 39). Petitioner further contends that the
`
`combination of Ogawa ’577 and Ogawa ’045, from the same inventor and field of
`
`technology, “would have made it obvious to one of ordinary skill in the art that
`
`data written from the slave circuitry (shift registers 3 and 4) to the cells of the
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`memory array (RAM 1) is written through the master read/write circuitry (sense
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`amplifiers 101, 102, 103, . . . , 10n).” Pet. 25 (citing Ex. 1004 ¶ 33). Specifically,
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`Petitioner asserts that the block data transfer in JP ’832, in combination with the
`
`scroll display operation in Ogawa ’577, teaches the limitations of dependent claims
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`18 and 19, which require writing the data via the master sense amplifiers to
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`different memory cells in the selected row. Pet. 33–38. Petitioner also provides
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`claim charts and citations to the Murphy Declaration (Ex. 1004 ¶¶ 38–39) in
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`support of its argument that JP ’832, Ogawa ’577, and Ogawa ’045 teach the
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`limitations of claims 18 and 19.
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`We agree with Petitioner’s expert, Dr. Murphy, that one of ordinary skill in
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`the art would have understood that, during the scroll display operation of
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`Ogawa ’577, the data is sensed, written, and transferred back to the memory array
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`through the sense amplifiers. Ex. 1004 ¶ 32. Similarly, we find Dr. Murphy’s
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`testimony credible that the block data transfer process in JP ’832 and scroll display
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`operation in Ogawa ’577 teach writing data via master sense amplifiers to the same
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`or different locations in the memory array. Ex. 1004 ¶¶ 37–39. Based on such
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`evidence and the record overall, we determine that Petitioner has established that
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`the combination of Ogawa ’577 and Ogawa ’045 teaches the writing of data stored
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`in shift registers to memory cells at the intersection of wordlines and bitlines
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`through sense amplifiers. Ex. 1004 ¶ 33. We find that Petitioner has shown by a
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`preponderance of the evidence that Ogawa ’577, Ogawa ’045, and JP ’832 teach
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`the limitations of claims 1–11 and 17–19.
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`We address Patent Owner’s arguments that the prior art does not teach or
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`suggest the limitations of the challenged claims below.
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`Because Ogawa ’577 and JP ’832 both use multiple different alleged slave
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`circuitry, Patent Owner alleges that these references do not teach or suggest the use
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`of the same slave circuitry as required in claims 1, 7, and 17. PO Resp. 9–11.
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`Patent Owner further argues that Ogawa ’577, JP ’832, and Ogawa ’045 each
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`disclose using different slave circuits for writing data. PO Resp. 15–25. We
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`disagree with Patent Owner. As discussed above, claims 1, 7, and 17 of the ’819
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`patent do not exclude the use of an intervening slave sense amplifier when writing
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`data “through” a sense amplifier. Indeed, claim 18, which depends from
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`independent claim 17, indicates that such an intermediate transfer among slave
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`sense amplifiers is within the scope of the broader independent claim 17.
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`Accordingly, we are not persuaded by Patent Owner’s argument regarding the use
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`of different slave circuitry in the writing process by Ogawa ’577 and JP ’832.
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`Patent Owner also contends that Ogawa ’577 and JP ’832 disclose writing
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`data to memory without sense amplifiers. PO Resp. 32–35; Ex. 2001 ¶¶ 70–72,
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`Figs. 9, 10. Thus, Patent Owner contends that Ogawa ’577 and JP ’832 do not
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`teach or suggest writing data through the sense amplifiers into the memory array.
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`PO Resp. 32–35. We are not persuaded by Patent Owner’s argument or cited
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`expert testimony that rely on alternate arrangements to construct an embodiment
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`that does not use sense amplifiers to write data to the memory. Id. Patent Owner
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`relies on a single embodiment in Ogawa ’577 that purports to write data to the left
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`and right portions of an array using only shift registers. PO Resp. 34. Patent
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`Owner’s arguments for JP ’832 also rely on a similar circuit arrangement found in
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`alternate embodiments. PO Resp. 34 (citing Ex. 1006, 4). These alternate circuit
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`arrangements, however, do not negate the express teaching of Ogawa ’577 that
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`“[a] pair of data busses (not shown [in Figure 2 of Ogawa ’577]) are provided
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`along the sense amplifiers 101, 102, 103, . . . , 10n for writing or reading the data.”
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`Ex. 1003, 3:34–36. In addition, we credit the testimony of Petitioner’s expert,
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`Dr. Murphy, who states that it was common to use sense amplifiers in write
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`operations and that Figure 2 of Ogawa ’577 teaches the use sense amplifiers and
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`bitlines to write to data on the left and right sides of the memory array. Ex. 1004
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`¶ 28; see also Ex. 2002, 64:10–65:1, 69:1–71:6. We determine that Petitioner has
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`established that Ogawa ’577 teaches writing data through the sense amplifiers.
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`c. Control Circuitry of Claims 1 and 7
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`Claim 1 recites: “A memory comprising: . . . control circuitry for controlling
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`exchange of data . . . .” Claim 7 recites: “A memory system comprising: . . .
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`control circuitry . . . including mode control circuitry . . . and multiplexer control
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`circuitry . . . .” Petitioner contends that one of ordinary skill in the art would have
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`recognized that control circuitry, not explicitly illustrated in Figure 2 of
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`Ogawa ’577, is inherent to generating the signals used to control the exchange of
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`data between the master read/write circuitry (sense amplifiers) and the first and
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`second slave circuitry (shift registers 3 and 4), as expressly disclosed in
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`Ogawa ’577. Pet. 16 (citing Ex. 1004 ¶ 23). Thus, Petitioner asserts that the
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`control circuitry is disclosed inherently in Figure 2 of Ogawa ’577. Id.
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`Petitioner has shown sufficiently that such control is inherent in the memory
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`system to execute the read/write circuitry and slave circuitry as disclosed in
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`Ogawa ’577. Pet. 16. We agree with Petitioner that “[o]ne of ordinary skill in the
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`art would have recognized that although control circuitry is not explicitly
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`illustrated in Figure 2 [of Ogawa ’577], control circuitry is required to operate
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`every element shown in the figure, including generating the first and second
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`control signals that control transfer gates 21 and 22, respectively.” Pet. 16 (citing
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`Ex. 1004 ¶ 23). Patent Owner does not dispute that control circuitry is present
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`inherently, but disagrees with where a person of ordinary skill in the art would
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`understand it is located with respect to Figure 2 of Ogawa ’577. PO Resp. 36, 38–
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`40. Accordingly, Patent Owner’s argument and expert testimony arbitrarily places
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`the inherent control circuitry outside of Figure 2 of Ogawa ’577. PO Resp. 37–38
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`(citing Ex. 20021 ¶ 76, Fig. 11, which shows control circuitry external to Figure 2
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`of Ogawa ’577).
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`We agree with Petitioner that control circuitry as recited in claim 1 would
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`“necessarily be provided to control the transfer gates . . . used to transfer data from
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`the master read/write circuitry . . . to the selected one of the first and or second
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`slave circuitry.” Pet 17 (citing Ex. 1004 ¶ 25), 19 (citing Ex. 1004 ¶ 26). We find
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`credible the testimony of Petitioner’s expert that control circuitry not shown
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`explicitly in Ogawa ’577 Figure 2 (but inherent) is required to operate the move
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`operation, such as the scroll operation. Ex. 1004 ¶ 23. Patent Owner does not
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`dispute that a control circuit is necessarily present in Ogawa’s Figure 2. In
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`addition, Patent Owner does not provide evidence sufficient to outweigh
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`Petitioner’s evidence that the control circuit as inherently disclosed teaches or
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`suggests the claimed control circuitry of claims 1 and 7.See Par Pharm., Inc. v.
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`TWI Pharms., Inc., 773 F.3d 1186 (Fed. Cir. 2014) (stating that in order to rely on
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`inherency in an obviousness analysis, “the limitation at issue necessarily must be
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`present, or the natural result of the combination of elements explicitly disclosed by
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`the prior art”). Thus, after consideration of Patent Owner’s argument, we
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`nevertheless are persuaded, by Petitioner’s evidence, that the claimed control
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`circuitry of claims 1 and 7 are disclosed in Figure 2 of Ogawa ’577.
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`d. Column Decoder of Claim 7
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`Claim 7 recites “a column decoder coupled to each of the plurality of banks
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`of slave sense amplifiers.” Petitioner contends “that a column decode function
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`must be implemented to achieve the data shifting (shift-in or shift-out) function
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`performed by the scroll display operation.” Pet. 41 (citing Ex.1004 ¶ 44).
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`Specifically, Figure 6 of JP ’832 shows that data is shifted out of shift registers
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`SRA and SRB. Ex. 1006, 10–11. Petitioner has provided sufficient expert
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`testimony that this operation requires column addresses to identify the data shifted
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`in and out of the appropriate registers and that such a decoder would have been
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`obvious to a person of ordinary skill in the art. Ex. 1004 ¶¶ 44, 45.
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`We are not persuaded by Patent Owner’s argument that, because there are
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`alternate ways to implement the column decode function, the column decoder
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`limitation of claim 7 is not disclosed inherently in JP ’832. PO Resp. 41–42 (citing
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`Ex. 2001 ¶ 81). Petitioner has argued that the function was inherent or that it
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`would have been obvious to use a column decoder in the system of JP ’832.
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`Pet. 41–42 (citing Ex. 1004 ¶¶ 44–45 (stating that a column decoder was inherently
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`disclosed “or it would have been obvious to use a column decoder” to implement
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`the shifting performed in JP ’832)). Thus, Petitioner’s contention on the column
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`decoder of claim 7 does not rely on inherency alone. We credit the testimony of
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`Petitioner’s expert and conclude that it