IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re patent of Conley:
`
`U.S. Pat. No. 8,316,177
`
`Issued: November 20, 2012
`
`Title: PARTIAL BLOCK DATA
`PROGRAMMING AND READING
`OPERATIONS IN A NON-VOLATILE
`MEMORY
`
`Petition for Inter Partes Review
`
`Attorney Docket No.:
`337722-70.177
`
`Customer No.: 26379
`
`Petitioner: Apple Inc.
`Real Party-in-Interest: Apple Inc.
`
`
`
`
`PETITION FOR INTER PARTES REVIEW
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`Dear Sir:
`
`Pursuant to the provisions of 35 U.S.C. §§ 311-319, Apple Inc. (hereinafter
`
`“Petitioner”) hereby petitions the Patent Trial and Appeal Board to institute an
`
`inter partes review of claims 1-9 of United States Patent No. 8,316,177 (“the ’177
`
`patent”)
`
`WEST\261524743.1
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`
`
`In re patent of Conley:
`
`U.S. Pat. No. 8,316,177
`
`Issued: November 20, 2012
`
`Title: PARTIAL BLOCK DATA
`PROGRAMMING AND READING
`OPERATIONS IN A NON-VOLATILE
`MEMORY
`
`Petition for Inter Partes Review
`
`Attorney Docket No.:
`337722-70.177
`
`Customer No.: 26379
`
`Petitioner: Apple Inc.
`Real Party-in-Interest: Apple Inc.
`
`
`
`
`PETITION FOR INTER PARTES REVIEW
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`Dear Sir:
`
`Pursuant to the provisions of 35 U.S.C. §§ 311-319, Apple Inc. (hereinafter
`
`“Petitioner”) hereby petitions the Patent Trial and Appeal Board to institute an
`
`inter partes review of claims 1-9 of United States Patent No. 8,316,177 (“the ’177
`
`patent”)
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`WEST\261524743.1
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`
`
`TABLE OF CONTENTS
`
`
`Page
`
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`I. MANDATORY NOTICES ............................................................................ 1
`
`A.
`
`B.
`
`C.
`
`D.
`
`Real Party-in-Interest ........................................................................... 1
`
`Related Matters ..................................................................................... 1
`
`Lead and Back-up Counsel .................................................................. 2
`
`Service Information .............................................................................. 2
`
`II. GROUNDS FOR STANDING ....................................................................... 3
`
`III. RELIEF REQUESTED .................................................................................. 3
`
`IV. THE REASONS FOR THE REQUESTED RELIEF ..................................... 3
`
`A.
`
`B.
`
`Summary of Reasons ............................................................................ 3
`
`Relevant Technology Background (Flash Memory) ............................ 4
`
`C. Overview of the ’177 Patent ................................................................. 7
`
`D.
`
`E.
`
`Level of Ordinary Skill in the Art ........................................................ 9
`
`Claim Construction............................................................................. 10
`
`1.
`
`“memory controller” (claims 1, 2, 4, 7) ................................... 10
`
`F.
`
`Challenge #1: Niijima Anticipates Claims 1-4, 6, and 8 .................. 11
`
`1.
`
`2.
`
`3.
`
`Overview of Niijima ................................................................ 11
`
`Niijima anticipates claim 1 ...................................................... 15
`
`Niijima anticipates claim 2 ...................................................... 23
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`- i -
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`TABLE OF CONTENTS
`(continued)
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`Page
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`4.
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`5.
`
`6.
`
`7.
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`Niijima anticipates claim 3 ...................................................... 25
`
`Niijima anticipates claim 4. ..................................................... 26
`
`Niijima anticipates claim 6 ...................................................... 26
`
`Niijima anticipates claim 8 ...................................................... 27
`
`G.
`
`Challenge #2: If the Board finds that Niijima does not
`anticipate any of claims 1-4, 6, or 8, then Niijima and the
`Admitted Prior Art or Cappelletti render such claim obvious ........... 27
`
`As discussed above, Niijima anticipates claims 1-4, 6 and 8 ............ 27
`
`1.
`
`2.
`
`3.
`
`“block” and “page” .................................................................. 28
`
`“in a preset order in a block at a specified offset position” ..... 28
`
`“to assemble the read pages of updated data and read
`pages of original data not updated in an order of the
`logical addresses associated therewith” ................................... 29
`
`4.
`
`“electrically conductive floating gates” ................................... 30
`
`H.
`
`I.
`
`Challenge #3 (Logical Block Number and Page Offset):
`Niijima And the Admitted Prior Art or Miyauchi Render
`Obvious Claim 5 ................................................................................. 32
`
`Challenge #4 (Multilevel Cells): Niijima and the Admitted
`Prior Art or Cappelletti Render Obvious Claim 7 .............................. 35
`
`1.
`
`Claim 7: The memory system of any one of claims 1-2
`wherein the memory controller is additionally
`characterized by operating the individual storage
`elements with more than two storage states in order to
`store more than one bit of data per storage element ................ 35
`
`- ii -
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`
`
`
`
`
`
`
`TABLE OF CONTENTS
`(continued)
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`Page
`
`
`
`J.
`
`Challenge #5 (Portable Card): Claim 9 Is Rendered Obvious by
`Niijima and the Admitted Prior Art or the PC Card Standard ........... 38
`
`1.
`
`Claim 9: The memory system of any one of claims 1-4,
`wherein the memory system is enclosed in a portable
`card and wherein the interface includes a plurality of
`external electrical contacts ....................................................... 38
`
`V.
`
`CONCLUSION ............................................................................................. 40
`
`
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`- iii -
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`
`
`
`EXHIBITS
`EXHIBITS
`
`Ex. 1001
`EX.
`1001
`
`U.S. Patent No. 8,316,177 (“the ’177 patent”)
`U.S. Patent No. 8,316,177 (“the ’ 177 patent”)
`
`Ex. 1002
`EX.
`1002
`
`File History for the ’177 patent
`File History for the ’ 177 patent
`
`Ex. 1003
`EX.
`1003
`
`U.S. Patent No. 5,457,658 (“Niijima”)
`U.S. Patent No. 5,457,658 (“Niijima”)
`
`Ex. 1004
`EX.
`1004
`
`Flash Memories, edited by Cappelletti, et al (1999)
`Flash Memories, edited by Cappelletti, et al (1999)
`
`(“Cappelletti”)
`(“Cappelletti”)
`
`Ex. 1005
`EX.
`1005
`
`U.S. Patent No. 5,627,783 (“Miyauchi”)
`U.S. Patent No. 5,627,783 (“Miyauchi”)
`
`Ex. 1006
`EX.
`1006
`
`PC Card Standard, Volumes 1 and 3 (1999) (“PC Card
`PC Card Standard, Volumes 1 and 3 (1999) (“PC Card
`
`Standard”)
`Standard”)
`
`Ex. 1007
`EX.
`1007
`
`Declaration of Dr. Vivek Subramanian
`Declaration of Dr. Vivek Subramanian
`
`Ex. 1008
`EX.
`1008
`
`CV of Dr. Vivek Subramanian
`CV of Dr. Vivek Subramanian
`
`Ex. 1009
`EX.
`1009
`
`Excerpt from Microsoft Computer Dictionary, 4th edition
`Excerpt from Microsoft Computer Dictionary, 4th edition
`
`1999, “controller”
`1999, “controller”
`
`
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`U.S. Pat. No. 8,316,177
`Petition For Inter Partes Review
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`I. Mandatory Notices
`
`A. Real Party-in-Interest
`
`Pursuant to 37 C.F.R. § 42.8(b)(1), the real party-in-interest is Apple Inc.
`
`B. Related Matters
`
`Pursuant to 37 C.F.R. § 42.8(b)(2), Petitioner states that Longitude Flash
`
`Memory Systems S.A.R.L. (“Patent Owner”) is asserting the ’177 patent against
`
`the Real Party-In-Interest in a suit filed September 23, 2014, styled Longitude
`
`Licensing Ltd., and Longitude Flash Memory Systems S.A.R.L. v. Apple Inc., Case
`
`No. 3:14-cv-4275, pending in the United States District Court for the Northern
`
`District of California (“Related Litigation”). Petitioner has filed, or soon will file,
`
`petitions for inter partes review of U.S. Patent Nos. 6,510,488; 6,763,424 (the
`
`“’424 patent”); 6,831,865; 6,968,421; 7,012,835; 7,120,729; 7,224,607; 7,181,611;
`
`7,657,702 (the “’702 patent”); 7,818,490; 7,970,987; and 8,050,095.
`
`The ’424 patent, which is the great-great-grandparent of the ’177 patent, was
`
`the subject of previous litigation and the following opinions in which one or more
`
`claim terms found in both patents were construed: (1) SanDisk Corp. v. Kingston
`
`Tech. Co., 695 F.3d 1348 (Fed. Cir. 2012); (2) In the Matter of Certain Flash
`
`Memory Controllers, United States Int’l Commission, Inv. No. 337-TA-619, Order
`
`No. 33, July 15, 2008 (Bullock, ALJ); and (3) In the Matter of Certain Flash
`
`Memory Controllers, United States Int’l Commission, Inv. No. 337-TA-619,
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`U.S. Pat. No. 8,316,177
`Petition For Inter Partes Review
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`Commission Opinion, November 24, 2009. The ’702 patent, which is related to
`
`the ’177 patent, was the subject of previous litigation and the following opinion in
`
`which one or more claim terms found in both patents were construed: SanDisk
`
`Corp. v. Kingston Tech. Co., Inc., United States District Court for the Western
`
`District of Wisconsin, Case No. 10-cv-243-bbc, March 16, 2011 (Crabb, J.).
`
`As of the filing of this petition, no other judicial or administrative matters
`
`are known to Petitioner that would affect, or be affected by, a decision in an inter
`
`partes review of the ’177 patent.
`
`C. Lead and Back-up Counsel
`
`Pursuant to 37 C.F.R. § 42.8(b)(3), lead counsel for this matter is Brent
`
`Yamashita (USPTO Reg. No. 53,808), and back-up counsel for this matter are Ed
`
`Sikorski (USPTO Reg. No. 39,478) and Kevin Hamilton (USPTO Reg. No.
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`67593), all at the e-mail address: Apple-Longitude-IPR@dlapiper.com. The
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`postal and hand delivery address for both is DLA Piper LLP (US), 2000 University
`
`Avenue, East Palo Alto, California, 94303, and the telephone number is 650-833-
`
`2000.
`
`D.
`
`Service Information
`
`Pursuant to 37 C.F.R. § 42.8(b)(4), papers concerning this matter should be
`
`served on the following email address: Apple-Longitude-IPR@dlapiper.com.
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`U.S. Pat. No. 8,316,177
`Petition For Inter Partes Review
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`II. Grounds for Standing
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`Pursuant to 37 CFR § 42.104(a), Petitioner certifies that (i) the ’177 patent is
`
`available for inter partes review, and that (ii) Petitioner is not estopped or barred
`
`from requesting inter partes review challenging the ’177 patent on the grounds
`
`identified in this petition.
`
`III. Relief Requested
`
`Petitioner asks that the Board review the accompanying prior art and
`
`analysis, institute a trial for inter partes review of claims 1-9 of the ’177 patent,
`
`and cancel those claims as invalid for the reasons set forth below.
`
`IV. The Reasons for the Requested Relief
`
`A.
`
`Summary of Reasons
`•
`
`Challenge #1: Niijima (Ex. 1003) anticipates claims 1-4, 6,
`
`and 8.
`
`•
`
`•
`
`Challenge #2: If the Board finds that Niijima does not
`
`anticipate any of claims 1-4, 6, or 8, then Niijima and the
`
`Admitted Prior Art or Cappelletti (Ex. 1004) render such claim
`
`obvious.
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`Challenge #3 (Logical Block Number and Page Offset):
`
`Niijima and the Admitted Prior Art or Miyauchi render obvious
`
`claim 5.
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`U.S. Pat. No. 8,316,177
`Petition For Inter Partes Review
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`•
`
`•
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`Challenge #4 (Multilevel Cells): Niijima and the Admitted
`
`Prior Art or Cappelletti render obvious claim 7.
`
`Challenge #5 (Portable Card): Niijima and the Admitted
`
`Prior Art or the PC Card Standard (Ex. 1006) render claim 9
`
`obvious.
`
`B. Relevant Technology Background (Flash Memory)
`
`A flash memory device contains one or more arrays of non-volatile memory
`
`cells. (Ex. 1001 at 1:34-45). Non-volatile memory cells retain their data when
`
`power is removed. (Id.) However, unlike most types of non-volatile memory cells
`
`(such as ROM and EPROM cells), flash memory cells are electrically
`
`reprogrammable. (Id.). The typical flash memory architecture used to achieve
`
`non-volatility and reprogrammability has several functional limitations. For
`
`example, once a flash memory cell is programmed with data, the cell must be
`
`erased before that cell can be reprogrammed with new data. (Id.). Further,
`
`extensive circuitry is required to erase flash memory cells individually. (Id.).
`
`Therefore, instead of erasing individual cells, the typical flash memory has large
`
`groups of cells arranged into erasable blocks, a block containing the smallest
`
`number of cells that can be erased at one time. (Id.). It is desirable to read or write
`
`data in units smaller than the size of a block. (Ex. 1001 at 1:55-63). Therefore,
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`blocks are further partitioned into pages, a page containing the smallest number of
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`U.S. Pat. No. 8,316,177
`Petition For Inter Partes Review
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`cells that can be read or written at one time. (Id.). Also, in some flash memories,
`
`the pages within each block can only be programmed in a physically sequential
`
`manner. (Ex. 1001 at 7:7-10; Ex. 1008 at ¶ 13).
`
`In addition to user data, each page in a flash memory can contain a set of
`
`overhead data fields and flags to store information related to the user data. (Ex.
`
`1001 at 1:45-49, 5:59-65). For example, each time user data is written to a page, a
`
`logical block number (“LBN”) indicating the data’s logical address can be
`
`recorded in a data field within the page. (Ex. 1001 at 5:60-65). Figure 6 of the
`
`’177 patent, shown below, illustrates some elements of the typical flash memory
`
`architecture.
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`(Ex. 1001 at Figure 6; Ex. 1008 at ¶ 14).
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`U.S. Pat. No. 8,316,177
`Petition For Inter Partes Review
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`The block and page architecture of the typical flash memory presents several
`
`challenges when updating user data. In the ideal case, the data in all pages of a
`
`block are modified together and written to the pages of an erased block. (Ex. 1001
`
`at 2:9-13). However, a partial block update is more common, in which the data in
`
`only some pages within a block are updated, while the data in the remaining pages
`
`is unchanged. (Ex. 1001 at 2:14-20). At least two techniques to perform a partial
`
`block update in a flash memory device were well known when the ’177 patent was
`
`filed and are acknowledged as prior art by the ’177 patent itself. (Ex. 1001 at 2:9-
`
`35). The first technique involves writing the updated data into a new, erased block.
`
`(Id.) The system then copies the unchanged data from the old block into the new
`
`block. (Id.). Finally, the system erases the old block. (Id.). This technique is
`
`inefficient because it requires copying unchanged pages of data to a different
`
`block. (Id.; Ex. 1008 at ¶ 15).
`
`The second known partial block update technique also involves writing the
`
`data of the updated pages to a corresponding number of pages in a new block. (Ex.
`
`1001 at 2:26-35). However, instead of copying the unchanged pages of data to the
`
`new block, the flags of the pages in the original block which are being updated are
`
`modified to indicate that those pages contain superseded data. (Id.). When reading
`
`the data, the updated data from pages of the new block are combined with the
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`unchanged data from the pages of the original block that are not flagged as
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`U.S. Pat. No. 8,316,177
`Petition For Inter Partes Review
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`superseded. (Id.). While the second technique avoids copying the unchanged data
`
`to the new block, it still requires updating a flag in each superceded page. (Id.; Ex.
`
`1008 at ¶ 16).
`
`C. Overview of the ’177 Patent
`
`The ’177 patent discloses a method and apparatus for an improved partial
`
`block transfer that does not require copying the unchanged pages of data to the
`
`new block (like the prior art), and also does not require modifying the flags of the
`
`pages in the original block which are being updated to indicate they contain
`
`superseded data. (Ex. 1001 at 2:38-61). By eliminating the step of modifying the
`
`flags in the superceded pages, “a potential of disturbing the previously written data
`
`in adjacent pages of that same block that can occur from such a writing operation is
`
`eliminated. Also, a performance penalty of the additional program operation is
`
`avoided.” (Ex. 1001 at 2:62-3:3). The ’177 patent purports to achieve these
`
`advantages “by maintaining both the superceded data pages and the updated pages
`
`of data with a common logical address. The original and updated pages of data are
`
`then distinguished by the relative order in which they were programmed.” (Ex.
`
`1001 at 2:54-61; Ex. 1008 at ¶ 17).
`
`The ’177 patent eliminates the need to modify flags by tracking the relative
`
`order in which pages having the same logical address are programmed. (Id. at
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`U.S. Pat. No. 8,316,177
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`2:54-61). Among pages with the same logical address, only the page most recently
`
`programmed has valid data. (Id.) Specifically, the ’177 patent explains:
`
`But rather than tagging the pages containing original data
`
`as being superceded, the memory controller distinguishes
`
`the pages containing the superceded data from those
`
`containing the new, updated version either (1) by keeping
`
`track of the order in which the pages having the same
`
`logical addresses were written, such as by use of a
`
`counter, and/or (2) from the physical page addresses
`
`wherein, when pages are written in order within blocks
`
`from the lowest page address to the highest, the higher
`
`physical address contains the most recent copy of the
`
`data.
`
`(Ex. 1001 at 7:64-8:6). An example embodiment distinguishes valid and invalid
`
`pages using a combination of time stamps written to blocks and the relative
`
`locations of pages within each block, exploiting the fact that the pages within each
`
`block must be programmed in a known physical order to determine the order in
`
`which pages within the block were programmed. (Id. at 9:44-57). Specifically, the
`
`’177 patent explains:
`
`A second specific implementation of the inventive
`
`technique can also be described with respect to FIG. 8. In
`
`this example, the time stamp is used only to determine
`
`the relative age of the data stored in blocks, While the
`
`most recent pages among those that carry the same LBN
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`U.S. Pat. No. 8,316,177
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`and page number are determined by their relative
`
`physical locations. The time stamp 43 then does not need
`
`to be stored as part of each page. Rather, a single time
`
`stamp can be recorded for each block, either as part of
`
`the block or elsewhere within the non-volatile memory,
`
`and is updated each time a page of data is written into the
`
`block.
`
`(Id. at 9:44-57; Ex. 1008 at ¶¶ 18-19).
`
`Therefore, the ’177 uses a combination of known prior art, including only
`
`writing updated pages to the new block, and the known limitation of certain flash
`
`memories that pages within each block must be written sequentially, to achieve its
`
`goal of performing a partial block update without modifying the flags of the
`
`superceded pages. In fact, the only element in the implementation above for which
`
`the ’177 patent even claims novelty is the use of a timestamp to record the relative
`
`times at which blocks are programmed. Notably, however, the claims of the ’177
`
`patent do not contain any limitations directed to this alleged point of novelty, and
`
`all claims are anticipated and/or rendered obvious as discussed below. (Ex. 1008
`
`at ¶ 20).
`
`D. Level of Ordinary Skill in the Art
`
`A person of ordinary skill in the relevant art at the time of the ’177 patent
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`would have had a Master’s Degree or equivalent in electrical engineering or a
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`related field and two years of experience in memory technology or the equivalent.
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`(Ex. 1008 at ¶ 21).
`
`E. Claim Construction
`
`For unexpired patents, claims should be given the “broadest reasonable
`
`interpretation in light of the specification” (“BRI”). See 37 C.F.R. § 42.100(b) and
`
`42.204(b)(3); see also In re Yamamoto, 740 F.2d 1569, 1571 (Fed. Cir. 1984); In
`
`re Am. Acad. Of Sci. Tech. Ctr., 367 F.3d 1359, 1363-64 (Fed. Cir. 2004). Due to
`
`the different claim construction standards of Inter Partes Review and U.S. District
`
`Court proceedings, Petitioner expressly reserves the right to assert different claim
`
`constructions and to take different positions with respect to any claim terms of the
`
`’177 patent construed in the Related Litigation or any other proceeding.
`
`1.
`
`“memory controller” (claims 1, 2, 4, 7)
`
`
`
`This phrase was previously construed by a district court in prior litigation
`
`involving the related ’702 patent, SanDisk Corp. v. Kingston Tech. Co., Case No.
`
`10-cv-243-bbc, slip op., March 16, 2011, W.D. Wisconsin. The court in that
`
`decision held: “The ‘memory controller’ (’702 pat., cls 24 and 33) must be
`
`connected directly to the blocks, but it need not apply voltage to the blocks.” In
`
`the Related Litigation, Petitioner is advocating this construction and believes it is
`
`appropriate under the Phillips standard, while Patent Owner contends the term
`
`should be given its plain and ordinary meaning.
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`U.S. Pat. No. 8,316,177
`Petition For Inter Partes Review
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`Under the broadest reasonable interpretation standard, Petitioner contends
`
`that “memory controller” should be construed as: “a device that controls access to
`
`a memory device.” (Ex. 1008 at ¶ 24; Ex. 1009 (“controller n. A device on which
`
`other devices rely for access to a computer subsystem. A disk controller, for
`
`example, controls access to one or more disk drives, managing physical and logical
`
`access to the drive or drives.”)).
`
`F. Challenge #1: Niijima Anticipates Claims 1-4, 6, and 8.
`
`The earliest claimed priority date of the ’177 patent is the filing date of
`
`parent U.S. Patent Application No. 09/766,436, filed on January 19, 2001.
`
`Niijima (Ex. 1003) issued on October 10, 1995, more than one year before
`
`the earliest claimed priority date of the ’177 patent. Niijima is therefore prior art to
`
`the ’177 patent under pre-AIA 35 U.S.C. § 102(a), (b) and (e), and pre-AIA 35
`
`U.S.C. § 103(a).
`
`As explained below, Niijima discloses all elements and limitations of claims
`
`1-4, 6, and 8 of the ’177 patent.
`
`1. Overview of Niijima
`
`Niijima discloses a nonvolatile memory with cluster-erase flash capability
`
`and a solid state file apparatus (“SSF”) that can dynamically allocate flash memory
`
`sectors. (Ex. 1003 at 1:10-14). Niijima is based in part on a “dynamic sector
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`allocation” method for flash memories previously disclosed in Japanese Patent
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`Application No. 3-197318. (Id. at 7:38). Niijima explains that dynamic sector
`
`allocation involves creating and maintaining an address translation table to map
`
`between logical addresses specified by a host processor and physical address
`
`within a flash-memory-based SSF. (Id. at 2:28-35). In addition to storing data,
`
`each addressable sector in the SSF includes a reverse reference pointer (“RP”) area
`
`to store the logical address corresponding to the data stored in the sector, and a
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`status area storing flags to indicate whether or not the data stored in the sector is
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`valid. (Id. at 2:35-56). (Ex. 1008 at ¶ 25).
`
`When the SSF receives a command from the host processor to write data to a
`
`logical address, the SSF allocates a new physical sector of the flash memory to the
`
`logical address, writes the data to the data area of the physical sector, writes the
`
`logical address to the RP area of the physical sector, and sets a “valid” flag in the
`
`status area of the physical sector. (Id. at 2:45-56). The SSF also records the
`
`physical address of the allocated physical sector in an address translation table
`
`entry for the logical address. (Id. at 2:51-53). The results of writing data to logical
`
`address “(1,4,5)” are illustrated in Figure 1 of Niijima, shown below. (Id. at 2:45-
`
`56).
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`(Ex. 1008 at ¶ 26).
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`When the SSF again receives a command from the host processor to write
`
`new data to the same logical address, the SSF sets an “invalid” flag in the status
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`area of the physical sector previously allocated to that logical address. (Id. at 2:57-
`
`67). The SSF allocates another new physical sector of the flash memory to the
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`logical address, writes the new data to the data area of the new sector, writes the
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`logical address to the RP area of the new sector, and sets a “valid” flag in the status
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`area of the new sector. (Id.). The SSF also records the physical address of the new
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`sector in the address translation table entry for the logical address. (Id.). The
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`results of writing new data to logical address “(1,4,5)” are illustrated in Figure 2 of
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`Niijima, shown below. (Id. at 2:57-67).
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`(Ex. 1008 at ¶ 27).
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`Niijima describes known methods of updating the “valid” and “invalid”
`
`flags within the status area of an allocated physical sector. (Id. at 3:11-22). Like
`
`the ’177 patent, Niijima explains that it is difficult, and in some cases impossible,
`
`to update a sector’s status flags once data is written to the sector. (Ex. 1001 at
`
`6:65-7:13; Ex. 1003 at 3:11-22). Also like the ’177 patent, Niijima explains that
`
`the object of the invention is to provide a flash memory that operates without the
`
`need to update the flags. (Ex. 1001 at 2:26-35, 7:14-19; Ex. 1003 at 3:14-22, 3:26-
`
`29). To this end, Niijima discloses:
`
`4) Writing into a sector uses a dynamic allocation
`
`method. However, unlike Japanese Pat. Appln. No. 3-
`
`197318, it does not set valid/invalid flags.
`
`(Id. at 7:38-41). Instead of relying of status flags to distinguish valid and invalid
`
`sectors, Niijima recognizes that “it is easy to distinguish valid sectors from invalid
`
`sectors if the sequence of all sectors in time order can be determined.” (Id. at 7:60-
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`62). Using the same method later claimed in the ’177 patent, Niijima determines
`
`the order in which all sectors were written using sequence numbers written to
`
`clusters and the relative locations of sectors within their clusters:
`
`The present invention maintains this time sequence
`
`information by two-level hierarchies, the cluster and the
`
`sector. Clusters are sequenced by sequence numbers in
`
`cluster information sectors… . Sectors are sequenced by
`
`the locations where they are in their clusters due to the
`
`write methods described in 4). By combining them, the
`
`sequence of all sectors in temporal order can be
`
`uniquely… .
`
`(Id. at 7:54-8:6). The write method described in 4) explains that “[s]ectors in the
`
`same cluster are written in ascending or descending order of address.” (Id. at 7:40-
`
`41). Therefore, Niijima identifies precisely the same problem, and anticipates
`
`precisely the same solution, as the ’177 patent. (Ex. 1008 at ¶¶ 28-30).
`
`2.
`
`Niijima anticipates claim 1.
`
`a.
`
`Preamble: A re-programmable non-volatile memory
`system, comprising:
`
`Niijima discloses this preamble. For example, Niijima discloses “a
`
`nonvolatile memory with cluster-erase flash capability.” (Ex. 1003 at 1:10-11; see
`
`also Id. at Title, Fig. 4, 3:26-29, 4:57-61, 5:24-34; Ex. 1008 at ¶¶ 31-32).
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`b.
`
`an array of storage elements organized into a
`plurality of blocks, each block having storage
`elements that are erasable together and organized
`into a plurality of pages, each page having storage
`elements that are accessed together and each page is
`programmable in a preset order in a block at a
`specified offset position,
`
`
`
`Niijima discloses this element. The nonvolatile memory “comprises N
`
`clusters, each comprising M sectors, wherein M and N are integers greater than
`
`one.” (Id. at 3:31-33). Niijima explains, “The cluster consists of one or more
`
`blocks each of which is a physical erasure unit.” (Id. at 5:43-45; see also Id. at
`
`1:60-63). Niijima discloses an embodiment in which a sector “is the minimum
`
`access unit of the CPU 10 to the [nonvolatile memory].” (Id. at 5:35-38). In the
`
`same embodiment, “one physical sector uses two word lines in a flash EEPROM.
`
`That is, two pages constitute one sector.” (Id. at 5:38-40). Therefore, Niijima
`
`discloses a non-volatile memory system having a plurality of blocks of memory
`
`storage elements (i.e., “clusters” and/or “blocks”) that are individually organized
`
`into a plurality of pages of memory storage elements (i.e., “sectors” and/or
`
`“pages”). (Ex. 1008 at ¶¶ 33-34).
`
`The ’177 patent discloses that “a block contains the smallest number of cells
`
`(unit of erase) that are erasable at one time.” (Ex. 1001 at 1:41-45). Likewise,
`
`Niijima discloses an embodiment in which a “cluster consists of one or more
`
`blocks each of which is a physical erasure unit.” (Ex. 1003 at 5:43-45). Since
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`Niijima expressly discloses an embodiment with a cluster comprising one block,
`
`one of ordinary skill in the art would have understood that the “clusters” disclosed
`
`in Niijima anticipate the “blocks” recited in the claims of the ’177 patent. (Ex.
`
`1008 at ¶ 35).
`
`The ’177 patent discloses that a page is “the basic unit for reading and
`
`programming user data (unit of programming and/or reading).” (Ex. 1001 at 1:56-
`
`63). Likewise, Niijima discloses that a sector “is the minimum access unit of the
`
`CPU 10 to the SSF 20.” (Ex. 1003 at 5:35-38). Niijima further discloses that “two
`
`pages constitute one sector.” (Id. at 5:40). Likewise, the ’177 patent discloses
`
`“pages [] are the basic unit for reading and programming user data (unit of
`
`programming and/or reading). Each page usually stores one sector of user data, but
`
`a page may store a partial sector or multiple sectors. A ‘sector’ is used herein to
`
`refer to the an amount of user data that is transferred to and from the host as a
`
`unit.” (Ex. 1001 at 1:56-63). Therefore, one of ordinary skill in the art would have
`
`understood that the “sector” disclosed in Niijima anticipates the “page” and “at
`
`least one page” elements recited in the claims of the ’177 patent. (Ex. 1008 at ¶
`
`36).
`
`Niijima discloses that each page is programmable in a preset order in a block
`
`at a specified offset position. For example, Niijima states:
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`4) Writing into a sector uses a dynamic allocation
`
`method. However, unlike Japanese Pat. Appln. No. 3-
`
`197318, it does not set valid/invalid flags. Sectors in the
`
`same cluster are written in ascending or descending order
`
`of address. In the embodiment, because the cluster
`
`information sector is placed at the top of the cluster, data
`
`is written into the sector in ascending order of address,
`
`but, if it is placed at the end of a cluster, data is written in
`
`the sector in descending order of address.
`
`
`
`Until writing is complete for one cluster, that is,
`
`until all the sectors in the cluster are used, or it is decided
`
`that the rest of the cluster is to be left unused, data is not
`
`written into other clusters. If all sectors within a cluster
`
`are bad, writing of data is terminated therein. Such
`
`termination can be determined because bad sector
`
`information is previously written in a part of the flash
`
`memory 34 in the initialize process in SSF fabrication.
`
`
`
`Initially, user data is written into the cluster
`
`according to the initial sequence number assign in 2), but,
`
`once data is written into all the clusters, writing is
`
`performed in the cluster with the maximum sequence
`
`number through the erasure and initialization processes.”
`
`(Ex. 1003 at 7:38-59; Ex. 1008 at ¶ 37).
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`c.
`
`a memory controller for controlling the operations of
`the non-volatile memory system, the operations
`including:
`
`
`
`Niijima discloses this element. Niijima describes a memory controller as
`
`follows: “FIG. 4 shows a schematic configuration of the SSF 20. The SSF 20
`
`comprises a controller 30 connected to the family bus 18, and an internal bus 31
`
`consisting of a random access memory (RAM) 32, a bus control element 33 and a
`
`flash memory 34.” (Ex. 1003 at 4:24-27). The controller 30 controls the
`
`operations of the non-volatile memory system. (Ex. 1003 at 6:35-37, 9:34-36;
`
`Figure 4; Ex. 1008 at ¶¶ 38-39).
`
`d.
`
`(a) in response to a host command for programming
`and one or more pages of original user data
`addressable by logical addresses and received from
`the host, programming the one or more pages of
`original user data into a first one or more pages of
`storage elements in the preset order in at least a first
`one of the blocks,
`
`
`
`Niijima discloses this element. For example, it states:
`
`Now, it is assumed that, when the SSF receives a write
`
`command regarding a logical address (H, C, S)=(1, 4, 5)
`
`from the host processor, a sector Y, which is empty until
`
`then, is allocated to the logical address. A controller of
`
`SSF writes data in the data area of the physical sector Y,
`
`and writes an RP are
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