UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`VOLKSWAGEN GROUP OF AMERICA, INC.
`Petitioner
`
`v.
`
`ADVANCED SILICON TECHNOLOGIES LLC
`Patent Owner
`
`
`
`
`Case IPR2016-TBA
`Patent 6,630,935 B1
`
`
`
`
`PETITION FOR INTER PARTES REVIEW
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent & Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`

`
`
`
`TABLE OF CONTENTS
`
`I. 
`
`INTRODUCTION ........................................................................................... 1 
`
`II.  MANDATORY NOTICES ............................................................................. 3 
`
`A. 
`
`B. 
`
`C. 
`
`Real parties-in-interest .......................................................................... 3 
`
`Notice of related matters ....................................................................... 3 
`
`Lead and back-up counsel with service information ............................ 4 
`
`III.  GROUNDS FOR STANDING ........................................................................ 4 
`
`IV.  STATEMENT OF RELIEF REQUESTED .................................................... 5 
`
`V. 
`
`TECHNICAL BACKGROUND ..................................................................... 5 
`
`A.  A graphics processor includes specially-designed hardware
`for graphics-processing tasks. ............................................................... 5 
`
`B.  Matsushita designed a multithreaded processor for computer
`graphics that improved the utilization of functional units. ................... 8 
`
`C. 
`
`The challenged claims recite the functionality of a
`conventional multithreaded processor that was predicted by
`industry experts years before the ’935 patent was filed. ..................... 11 
`
`VI.  CLAIM CONSTRUCTION .......................................................................... 15 
`
`VII. 
`
`IDENTIFICATION OF CHALLENGE ........................................................ 16 
`
`A.  Ground 1: Claims 1, 2, and 7 are obvious over Hirata in
`view of Kimura. ................................................................................... 20 
`
`1. 
`
`2. 
`
`3. 
`
`Claim 1—Hirata and Kimura teach or suggest all the
`features of this claim. ................................................................ 20 
`
`Claim 2—Hirata and Kimura teach or suggest all the
`features of this claim. ................................................................ 30 
`
`Claim 7—Hirata and Kimura teach or suggest all the
`features of this claim. ................................................................ 31 
`
`
`
`
`- i -
`
`

`
`
`
`
`
`
`B. 
`
`C. 
`
`Ground 2: Claim 3 is obvious over Hirata in view of Kimura
`and further in view of Hennessy. ........................................................ 32 
`
`Ground 3: Claims 4 and 5 are obvious over Hirata in view of
`Kimura and further in view of Watkins. ............................................. 38 
`
`1. 
`
`2. 
`
`Claim 4—Hirata, Kimura, and Watkins teach or
`suggest all the features of this claim. ........................................ 38 
`
`Claim 5— Hirata, Kimura, and Watkins teach or
`suggest all the features of this claim. ........................................ 39 
`
`D.  Ground 4: Claims 6 and 8 are obvious over Kimura in view
`of Hirata and further in view of Rentschler. ....................................... 40 
`
`1. 
`
`2. 
`
`Claim 6—Kimura, Hirata, and Rentschler teach or
`suggest all the features of this claim. ........................................ 41 
`
`Claim 8—Kimura, Hirata, and Rentschler teach or
`suggest all the features of this claim. ........................................ 43 
`
`E. 
`
`Ground 5: Claims 9-18 are obvious over Hirata in view of
`Kimura, Hennessy, Watkins, and Rentschler ...................................... 44 
`
`1. 
`
`2. 
`
`3. 
`
`4. 
`
`5. 
`
`Claim 9—Kimura, Hirata, Hennessy, Watkins, and
`Rentschler teach or suggest all the features of this
`claim. ......................................................................................... 45 
`
`Claim 10—Kimura, Hirata, Hennessy, Watkins, and
`Rentschler teach or suggest all the features of this
`claim. ......................................................................................... 48 
`
`Claim 11—Kimura, Hirata, Hennessy, Watkins, and
`Rentschler teach or suggest all the features of this
`claim. ......................................................................................... 49 
`
`Claim 12—Kimura, Hirata, Hennessy, Watkins, and
`Rentschler teach or suggest all the features of this
`claim. ......................................................................................... 50 
`
`Claim 13—Kimura, Hirata, Hennessy, Watkins, and
`Rentschler teach or suggest all the features of this
`claim. ......................................................................................... 51 
`- ii -
`
`

`
`
`
`6. 
`
`7. 
`
`8. 
`
`9. 
`
`Claim 14—Kimura, Hirata, Hennessy, Watkins, and
`Rentschler teach or suggest all the features of this
`claim. ......................................................................................... 51 
`
`Claim 15—Kimura, Hirata, Hennessy, Watkins, and
`Rentschler teach or suggest all the features of this
`claim. ......................................................................................... 52 
`
`Claim 16—Kimura, Hirata, Hennessy, Watkins, and
`Rentschler teach or suggest all the features of this
`claim. ......................................................................................... 53 
`
`Claim 17—Kimura, Hirata, Hennessy, Watkins, and
`Rentschler teach or suggest all the features of this
`claim. ......................................................................................... 54 
`
`10.  Claim 18—Kimura, Hirata, Hennessy, Watkins, and
`Rentschler teach or suggest all the features of this
`claim. ......................................................................................... 55 
`
`VIII.  MOTIVATION TO COMBINE: THE REFERENCES
`THEMSELVES SUGGEST THE PROPOSED COMBINATIONS. ........... 55 
`
`A.  A POSA would have been motivated to combine Hirata and
`Kimura and would have had a reasonable expectation of
`success in doing so. ............................................................................. 56 
`
`B. 
`
`C. 
`
`A POSA would have been motivated to combine Hirata and
`Kimura with Hennessy and would have had a reasonable
`expectation of success in doing so. ..................................................... 57 
`
`A POSA would have been motivated to combine Hirata and
`Kimura with either Watkins and would have had a
`reasonable expectation of success in doing so. ................................... 57 
`
`D.  A POSA would have been motivated to combine Hirata and
`Kimura with Rentschler and would have had a reasonable
`expectation of success in doing so. ..................................................... 58 
`
`
`
`
`- iii -
`
`

`
`
`
`IX.  CONCLUSION .............................................................................................. 60 
`
`CONCLUSION ............................................................................................ ..6O
`
`IX.
`
`
`
`
`
`
`
`
`
`
`- iv -
`
`_iV_
`
`

`
`
`
`Cases 
`
`TABLE OF AUTHORITIES
`
`In re Cuozzo Speed Techs.,
`778 F.3d 1271 (Fed. Cir. 2015) ............................................................................ 16
`
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007) ...................................................................................... 16, 56
`
`Standard Oil Co. v. Am. Cyanamid Co.,
`774 F.2d 448 (Fed. Cir. 1985) .............................................................................. 16
`
`Statutes 
`
`35 U.S.C. § 102(a) ................................................................................................... 18
`
`35 U.S.C. § 102(b) ...................................................................................... 18, 19, 20
`
`35 U.S.C. § 102(e) ................................................................................................... 18
`
`35 U.S.C. §103 ......................................................................................................... 16
`
`Other Authorities 
`
`37 C.F.R. § 42.6(d) .................................................................................................. 16
`
`
`
`
`
`
`
`
`- v -
`
`

`
`
`
`EXHIBIT LIST
`
`DESCRIPTION
`
`1004
`1005
`
`Exhibit
`No.
`1001 U.S. Patent No. 6,630,935 B1 to Taylor et al. (“’935 patent”)
`
`1002 Declaration of Robert A. Horst
`1003 H. Hirata et al., “An Elementary Processor Architecture with
`Simultaneous Instruction Issuing from Multiple Threads,” 19th Annual
`Int’l Symposium on Computer Architecture (May 19-21, 1992)
`European Patent Application No. EP 0827071 A2 to Kozo Kimura et al.
`J. Watkins et al., “A memory controller with an integrated graphics
`processor,” Computer Design: VLSI in Computers and Processors
`(1993)
`1006 U.S. Patent No. 5,859,789 to Nathan M. Sidwell (“Sidwell”)
`1007 U.S. Patent No. 5,821,950 to Rentschler et al (“Rentschler”)
`Prosecution History of U.S. Patent No. 6,630,935 B1 to Taylor et al.
`1008
`1009 U.S. Patent No. 5,778,243 to Aipperspach et al. (“Aipperspach”)
`1010 U.S. Patent No. 6,002,411 to Dye (“Dye”)
`1011 U.S. Patent No. 5,440,710 to Richter et al. (“Richter”)
`Prosecution History of U.S. Patent No. 5,778,243 to Aipperspach et al.
`1012
`1013
`Prosecution History of U.S. Patent No. 6,002,411 to Dye
`Prosecution History of U.S. Patent No. 5,440,710 to Richter et al.
`1014
`1015 M. J. Flynn, “Computer Architecture: Pipelined and Parallel Processor
`Design” (1995)
`1016 M. J. Flynn, “Some Computer Organizations and Their Effectiveness,”
`IEEE Transactions on Computers, Vol. c-21, No. 9 (September 1972)
`Foley et al., “Computer Graphics: Principles and Practice,” Second ed.
`in C (1987)
`J. L. Hennessy and D. A. Patterson, “Computer Architecture: A
`Quantitative Approach” (1990)
`L. C. Higbie, “Supercomputer Architecture,” Tutorial (December 1973)
`1019
`1020 R. Klein et al., “Illumination dependent refinement of multiresolution
`meshes” (1998)
`1021 Woo et al., “OpenGL Programming Guide: The Official Guide to
`Learning OpenGL, Release 1” (2nd ed.) (1997)
`S. Whitman, “Multiprocessor Methods for Computer Graphics
`Rendering,” Computer Science Publishing Program (1992)
`
`1017
`
`1018
`
`1022
`
`
`
`
`- vi -
`
`

`
`DESCRIPTION
`
`S. J. Eggers, “Simultaneous Multithreading: A Platform for Next-
`Generation Processors,” IEEE Micro (1997).
`P. Song, “Multithreading Comes of Age: Multithreaded Processors Can
`Boost Throughput on Servers, Media Processors,” Microdesign
`Resources (July 14, 1997)
`J. Neider et al. “OpenGL Programming Guide, The Official Guide to
`Learning OpenGL, Release 1,” Silicon Graphics, Inc. (1993)
`
`- vii -
`
`
`
`Exhibit
`No.
`1023
`
`1024
`
`1025
`
`
`
`
`
`
`

`
`
`I.
`
`Introduction
`
`Inter Partes Review of U.S. Patent No. 6,630,935 B1
`
`Volkswagen Group of America, Inc. (“Volkswagen”) petitions for inter
`
`partes review of claims 1-18 (“challenged claims”) of U.S. Patent No. 6,630,935
`
`(“’935 patent”), assigned to Advanced Silicon Technologies LLC (“AST”). The
`
`challenged claims are directed to a multithreaded computation module that may be
`
`configured to perform graphics-processing tasks. But this type of multithreaded
`
`computation module was taught or suggested by Matsushita Electric Industrial Co.
`
`(“Matsushita”) and others well before the ’935 patent was filed. The claims are
`
`therefore unpatentable and should be canceled.
`
`Specifically, in the mid-1990s (several years before the ’935 patent was
`
`filed), Matsushita designed a processor architecture that could issue and execute
`
`multiple instruction threads in parallel. At a high level, an instruction thread is a
`
`sequence of instructions, where each instruction tells the processor what operation
`
`or set of operations to perform on a given set of data. Matsushita’s multithreaded
`
`processor architecture was described in several publications, including a 1992
`
`article (Hirata1) and 1998 European Patent Application (Kimura2).
`
`
`1 H. Hirata et al., “An Elementary Processor Architecture with Simultaneous
`
`Instruction Issuing from Multiple Threads,” 19th Annual Int’l Symposium on
`
`Computer Architecture (May 19-21, 1992) (Ex. 1003) (“Hirata”), 136-145.
`
`
`
`- 1 -
`
`

`
`Inter Partes Review of U.S. Patent No. 6,630,935 B1
`
`These publications were not before the examiner during prosecution.
`
`Consequently, the examiner allowed independent claim 1 because he believed the
`
`prior art did not teach or suggest “an arbitration module” that uses “an application
`
`specific prioritization scheme” as recited in this claim. But the combination of
`
`Hirata and Kimura teaches or suggests this feature.
`
`For example, Hirata discloses a thread prioritization scheme that may be set
`
`on an application-by-application basis. For a computer-graphics application, Hirata
`
`discloses one type of prioritization scheme, and for a numerical-computation
`
`application, Hirata discloses a different type of prioritization scheme. And the
`
`combination of Hirata and Kimura discloses a mechanism for dynamically
`
`switching between these two types of prioritization schemes.
`
`A person of ordinary skill in the art (“POSA”) would have been motivated to
`
`combine these teachings for several reasons. For example, Hirata and Kimura both
`
`worked for Matsushita, and both of these references are directed to the same type
`
`of multithreaded-processor architecture.
`
`Unfortunately, this information was not before the examiner during
`
`prosecution. If it had been, independent claim 1 should not have been allowed.
`
`
`2 EP 0827071 A2, filed August 27, 1997, and published March 4, 1998 (Ex.
`
`1004) (“Kimura”).
`
`
`
`- 2 -
`
`

`
`Inter Partes Review of U.S. Patent No. 6,630,935 B1
`
`And the other claims of the ’935 patent also should not have been allowed because
`
`they merely recite well-known aspects of the so-called graphics pipeline and vector
`
`processors. For these reasons and as set forth in more detail below, all the
`
`challenged claims should be canceled.
`
`II. Mandatory Notices
`
`A. Real parties-in-interest
`
`Volkswagen Group of America, Inc., which is a subsidiary of Volkswagen
`
`AG.
`
`B. Notice of related matters
`
`AST asserted the ’935 patent in the following cases filed on December 21,
`
`2015 in Delaware: AST v. Volkswagen AG, 1-15-cv-01181; AST v. Toyota Motor
`
`Corporation, 1-15-cv-01180; AST v. Honda Motor Co., Ltd., 1-15-cv-01179; AST
`
`v. Bayerisch Motoren Werke AG, 1-15-cv-01178; AST v. NVIDIA Corp., 1-15-cv-
`
`01177; AST v. Renesas Electronics Corp., 1-15-cv-00176; AST v. Texas
`
`Instruments Inc., 1-15-cv-01175; AST v. Fujitsu Ten Ltd., 1-15-cv-01174; and AST
`
`v. Harman Int’l Industries, Inc., 1-15-cv-01173. AST has also asserted the ’935
`
`patent in the complaint Certain Computing or Graphics Systems, Components
`
`Thereof, and Vehicles Containing Same, Investigation No. 337-TA-984, filed
`
`December 28, 2015 at the U.S. International Trade Commission, naming, among
`
`numerous others, Volkswagen AG, Volkswagen Group of America, Inc.,
`
`
`
`- 3 -
`
`

`
`Inter Partes Review of U.S. Patent No. 6,630,935 B1
`
`Volkswagen Group of America Chattanooga Operations, LLC, Audi AG, and Audi
`
`of America, LLC as respondents. Volkswagen Group of America Chattanooga
`
`Operations, LLC and Audi of America, LLC are subsidiaries of Volkswagen
`
`Group of America, Inc. Audi AG is a subsidiary of Volkswagen AG.
`
`C. Lead and back-up counsel with service information
`
`Lead Counsel:
`
`Jonathan Tuminaro (Reg. No. 61,327); 202.772.8967
`
`Backup Counsel: Michael D. Specht (Reg. No. 54,463); 202.772.8756
`
`Backup Counsel: Daniel E. Yonan (Reg. No. 53,812); 202.772.8899
`
`Address:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
`
`1100 New York Avenue, NW, Washington, DC 20005
`
`202.371.2540 (fax)
`
`Volkswagen consents to service via email at: jtuminar-PTAB@skgf.com,
`
`
`
`
`
`
`
`
`
`
`
`mspecht-PTAB@skgf.com, and PTAB@skgf.com
`
`III. Grounds for Standing
`
`Volkswagen certifies that the ’935 patent is eligible for inter partes review
`
`and that Volkswagen is not barred or estopped from requesting inter partes review
`
`of the ’935 patent. The required fee is paid via online credit-card payment. The
`
`Office is authorized to charge fee deficiencies and credit overpayments to Deposit
`
`Acct. No. 19-0036 (Customer ID No. 45324).
`
`
`
`- 4 -
`
`

`
`Inter Partes Review of U.S. Patent No. 6,630,935 B1
`
`IV. Statement of Relief Requested
`
`Volkswagen requests inter partes review and cancelation of the challenged
`
`claims (i.e., claims 1-18) based on the detailed statements presented below.
`
`V. Technical Background
`
`The ’935 patent was filed on April 21, 2000. See Ex. 1001, ’935 patent at
`
`(22). This patent is directed to a geometric engine including a computational
`
`module for use in a video-graphics controller. See id., (54). Such a geometric
`
`engine was taught or suggested well before the ’935 patent’s filing date.
`
`A. A graphics processor includes specially-designed hardware for
`graphics-processing tasks.
`
`Traditionally, graphics-processing tasks were performed by a computer’s
`
`central-processing unit (CPU). Horst Dec., ¶ 29; see also id., ¶¶ 22-28; Foley et al.,
`
`Computer Graphics: Principles and Practice (Addison-Wesley Publishing Co., 2d
`
`ed. 1996) (Ex. 1017) (“Foley”), 855.3 Eventually, however, the computational
`
`demands of these graphics-processing tasks exceeded the capabilities of a single
`
`CPU. Horst Dec., ¶ 29; see also Foley, 855 (“In high-performance graphics
`
`systems, the number of computations usually exceeds the capabilities of a single
`
`CPU . . . .”). As a result, many of these graphics-processing tasks were offloaded to
`
`a dedicated graphics processor that was specially designed to handle the repetitive
`
`3 Foley is a well-known textbook on graphics processing. Horst Dec., ¶ 29.
`
`
`
`- 5 -
`
`

`
`
`
`Inter Partes Revieww of U.S. PPatent No.. 6,630,9355 B1
`
`
`
`
`
`
`
`
`
`
`
`mathemmatical commputations involved in graphicss processinng. Horst DDec., ¶ 29; ssee
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`also Folley, 855 (““[P]arallel systems haave becomme the rule iin recent yyears.”).
`
`
`
`
`
`
`
`referredd to as the ggraphics ppipeline. Hoorst Dec., ¶¶ 29; see aalso id., ¶¶
`
`
`
`
`
`
`
`sing steps,, commonl
`
`y
`
`
`
`22-28; seee
`
`
`
`
`
`
`
`
`
`GGraphics-prrocessing ttasks include a seriess of proces
`
`
`
`
`
`
`
`
`
`
`
`also Folley, 866-677. As illusttrated in Fooley’s Figuure 18.7 (rreproducedd below), thhe
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`graphics pipeline includes twwo major pprocessing
`
`
`
`
`
`
`
`
`
`Dec., ¶ 29phase annd a pixel (or rasterizzation) phaase. Horst D
`
`
`
`
`
`
`
`
`phases or
`
`
`
`subsystemms: a geomeetry
`
`
`
`
`
`; see also FFoley, 8666-67.
`
`
`
`
`
`
`
`The geoometry phaase includees, for exammple, (i) mmodel transfformation
`
`
`
`
`
`
`
`
`
`
`
`
`
`to transforrm
`
`
`
`betweenn the variouus coordinnate systemms that are uused in graaphics proccessing, annd
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`(ii) clippping to remmove data for objectss that will nnot be withhin a user’
`
`
`
`
`
`
`
`
`
`
`
`s view
`
`
`
`volume. Horst Dec., ¶ 32; seee also Folley, 868, 8669. The pixxel phase mmay includde
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`several different tyypes of intterpolationn operation
`
`
`
`
`
`
`
`
`
`
`
`
`
`s to determmine the coolors of thee
`
`various
`
`
`
`
`pixels. Hoorst Dec., ¶¶ 36; see allso id., ¶¶ 330-35; Folley, 868-699, 878.
`
`
`
`
`
`
`
`
`
`
`
`TTo performm these grapphics-proceessing taskks, virtuallyy all graphhics proces
`
`
`
`
`
`sors
`
`orst Dec.,
`
`¶
`
`
`
`
`
`
`
`
`
`
`
`since thhe mid-19990s have beeen designeed as pipellined and pparallel. H
`
`
`
`
`
`
`
`
`
`
`
`
`
`30; see also Foleyy, 876. “A ppipeline prrocessor coontains a nnumber of pprocessingg
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`- 6 -
`
`

`
`
`
`Inter Partes Revieww of U.S. PPatent No.. 6,630,9355 B1
`
`
`
`
`
`
`
`
`
`
`
`elementts (PEs) arrranged
`
`
`
`
`
`such thaat the outpuut of one
`
`
`
`
`
`becomees the inputt of the
`
`
`
`
`
`next, in pipeline fafashion.”
`
`
`
`
`
`8.9(a) Foley, 8874, Fig. 1
`
`
`
`
`(reproduuced abovee). “The
`
`
`
`
`
`PEs of aa parallel pprocessor are arrangeed side by
`
`
`
`
`
`
`
`
`
`side and ooperate simmultaneouslly
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`on diffeerent portioons of the ddata.” Id., 8874, Fig. 118.9(b) (repproduced aabove).
`
`
`
`
`
`
`
`TThe pipelinning and paarallelism ccan be appllied to bothh the geommetry phasee
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`and the pixel phasse
`
`
`
`
`
`of the sttandard
`
`s pipeline,
`graphic
`
`
`
`as illusttrated in
`
`Figure
`Foley’s
`
`
`
`18.11 (rreproducedd
`
`
`
`
`
`at right)). Horst Deec., ¶ 31; seee also Folley, 876.
`
`
`
`
`
`
`
`
`
`FFoley disclooses severaal examplee graphics--processor
`
`
`
`
`
`
`
`
`
`
`
`architecturres. See, e.
`
`g.,
`
`
`
`Foley, 8890-93. In addition too Foley’s eexamples, oothers in thhe industryy—includinng
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Matsushhita—desiggned multiithreaded pprocessors
`
`
`
`
`
`
`
`for graphi
`
`
`
`cs-processsing tasks.
`
`
`
`Horst DDec., ¶¶ 37--41; see alsso Hirata;
`Kimura.
`
`
`
`
`
`
`
`- 7 -
`
`

`
`
`
`Inter Partes Revieww of U.S. PPatent No.. 6,630,9355 B1
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`B. Matssushita designed a mmultithreaaded proceessor for ccomputer
`
`
`
`
`
`
`graphics that iimproved the utilizaation of fuunctional uunits.
`
`
`
`nn the mid-1990s, enggineers at MMatsushita
`
`
`
`
`
`
`
`
`
`designed aa multithreeaded
`
`
`
`B I
`
`
`
`processor architeccture for usse in a grapphics systeem. This mmultithreadeed processoor
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`architeccture is desscribed in sseveral pubblications,
`
`
`
`including
`
`
`
`Hirata andd Kimura.
`
`
`
`FFor examplle, Hirata ddiscloses “aa multithreeaded proc
`
`
`
`
`
`
`
`
`
`
`
`improvees machinee throughput.” Hirataa, 136. Acccording to
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`multithrreaded processor archhitecture can be “useed as the baase processsor in a
`
`
`
`
`
`essor archiitecture whhich
`
`
`
`Hirata, thi
`
`s
`
`
`
`
`
`
`
`parallel machine wwhich coulld run . . . aa graphics
`
`
`
`
`
`
`
`
`
`
`
`
`
`system.” IId., 136. Thhe hardwarre
`
`organiz
`ation for
`
`
`
`Hirata’ss
`
`
`
`multithrreaded
`
`or
`process
`
`
`
`architeccture is
`
`
`
`illustratted in Figure
`
`
`
`
`
`2 (reprooduced at
`
`
`
`right). IId., 138.
`
`
`
`Referrinng to this ffigure, Hiraata’s hardwware includdes:
`
`
`
`
`
`
`
`
`
` a reg
`
`
`
`
`ister set thhat has a pluurality of rregister bannks (id., 1338);
`
`
`
`
`
`
`
` a plu
`
`
`
`
`rality of fuunctional uunits—incluuding an innteger arithhmetic loggic
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`unit ((“ALU”), aa barrel shiifter, an intteger multtiplier, a flooating poinnt
`
`
`
`
`
`
`
`- 8 -
`
`

`
`
`
`
`
`
`
`
`
`Inter Partes Revieww of U.S. PPatent No.. 6,630,9355 B1
`
`
`
`
`
`
`
`
`
`
`
`
`
`(“FP””) adder, aan FP multiiplier, an FFP converteer, and loaad/store uniits
`
`
`
`
`
`
`
`(id., 138);
`
`
`
`n instructiomanage anthat each mrality of thhread slots
`
`
`
`on thread (iid.,
`
` a plu
`
`
`
`
`
`
`137-338); and
`
` an in
`
`
`
`
`reads to truction thrwhich instnit selects wstruction sschedule un
`
`
`
`
`
`
`
`
`
`execuute based oon a threadd prioritizattion schemme (id., 1400, Fig. 4).
`
`
`
`
`
`
`
`
`
`
`
`
`
`Inn particulaar, Hirata’s “instructioon schedulle unit worrks in one oof two moddes:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`implicitt-rotation mmode and eexplicit-rottation modde.” Id., 14
`
`
`
`
`
`
`
`
`
`
`
`0. “In the iimplicit-
`
`
`
`rotationn mode, priiority rotatiion occurs at a
`
`
`
`
`
`
`
`
`
`given nuumber of ccycles (rotaation interrval),
`
`
`
`
`
`
`
`as showwn in Figurre 4 [reprodduced at
`
`
`
`
`
`
`
`
`
`
`
`
`
`right].” Id. “On thhe other hannd, in the
`
`explicit
`
`
`
`
`-rotation mmode, the rrotation of
`
`priority
`
`
`
`
`is controllled by softtware.” Id.
`
`
`
`UUsing thesee two modees of operaation, Hiratta’s instrucction scheddule unit caan
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`implemment differeent types off prioritizaation schemmes dependding on thee type of
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`applicattion that is running. FFor example, for a coomputer-grraphics appplication,
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Hirata ddiscloses a first prioriitization sccheme, andd for a nummerical-commputation
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`applicattion, Hirataa disclosess a second pprioritizatiion schemee. Id., 141--42.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`BBoth of these prioritizzation scheemes aim aat reducingg the idle ti
`
`
`
`
`
`
`
`
`
`
`
`me of the
`
`
`
`- 9 -
`
`

`
`
`
`Inter Partes Revieww of U.S. PPatent No.. 6,630,9355 B1
`
`
`
`
`
`
`
`
`
`
`
`functionnal units. Inn particulaar, Hirata’ss computerr-graphics
`
`
`
`
`
`
`
`
`
`
`
`prioritizatiion schemee
`
`
`
`
`
`“flood[ss]” the functional uniits with suffficient insstructions tto reduce thhe idle timme.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Id., 141. And Hiraata’s numerical-compputation prrioritizationn scheme rreduces idlle
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`time by
`
`
`
`
` “guaranteee[ing that]] the execuution of succceeding itterations dooes not hinnder
`
`
`
`
`
`
`
`
`
`
`
`
`
`the execcution of ppreceding itterations.” Id., 142.
`
`
`
`
`
`
`
`
`
`BBuilding onn Hirata, KKimura disccloses addiitional detaails regardiing
`
`
`
`
`
`
`
`
`
`
`
`
`
`Matsushhita’s multtithreaded pprocessor aarchitecturre. See, e.gg., Kimura
`
`at (71), (5
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Kimuraa’s Figure 11 disclosess a “prior arrt” design
`
`
`
`
`
`
`
`
`
`that is remmarkably siimilar to
`
`
`
`
`
`
`
`
`
`
`
`
`
`Hirata’ss Figure 2, as illustratted in the sside-by-sidde compariison beloww:
`
`
`
`
`
`
`
`Kimuraa, Fig. 1 (annnotated); Hirata, Figg. 2 (annottated). A POOSA woulld understaand
`
`
`
`
`
`
`
`4).
`
`
`
`
`
`
`
`
`
`
`
`
`
`that Hirrata’s integger ALU, bbarrel shifteer, integer
`
`
`
`
`
`
`
`multiplier
`
`, FP adder
`
`, FP
`
`e units are
`multipliier, FP connverter, andd load/stor
`
`
`
`
`
`
`
`
`
`
`e example ttypes of Kiimura’s
`
`
`
`functionnal units 5006. Horst DDec., ¶¶ 399-40; see a
`
`
`
`
`
`
`
`lso Kimur
`
`a 9:26-33.
`
`
`
`- 10 -
`
`

`
`Inter Partes Review of U.S. Patent No. 6,630,935 B1
`
`Thus, both Hirata and Kimura disclose a multithreaded processor for
`
`processing multiple instruction streams independently. Hirata, Title; Kimura, (54).
`
`These references also disclose that this multithreaded processor can be used for
`
`graphics processing. See Hirata, 136; Kimura, 11:51-58. Although neither of these
`
`references explicitly discloses a vector processor, an industry expert predicted that
`
`multithreading would be used in a vector engine for graphics processing sometime
`
`before the end of the 1990s. See P. Song, Multithreading Comes of Age:
`
`Multithreaded processors can boost throughput on Servers, Media Processors,
`
`Microprocessor Report (July 14, 1997) (Ex. 1024) (“Song”) at 6 (“A multithreaded
`
`vector processor has a future in multimedia processing and could appear by the end
`
`of this decade [i.e., 2000].”).
`
`C. The challenged claims recite the functionality of a conventional
`multithreaded processor that was predicted by industry experts
`years before the ’935 patent was filed.
`
`The ’935 patent was filed on April 21, 2000—nearly three years after Song
`
`predicted that a graphics-based multithreaded vector processor would appear on
`
`the market. Compare ’935 patent at (22) with Song at 6. And like Hirata and
`
`Kimura (discussed above), the ’935 patent discloses a multithreaded processor
`
`architecture for reducing the idle time—and, thereby, improving the utilization—of
`
`a computation engine. See ’935 patent, 2:42-59, Fig. 1. The ’935 patent’s processor
`
`architecture is illustrated in Figure 1 (reproduced below).
`
`
`
`- 11 -
`
`

`
`
`
`
`
`
`
`
`
`Inter Partes Revieww of U.S. PPatent No.. 6,630,9355 B1
`
`
`
`
`
`TThe featurees disclosedd in this figgure were aall taught oor suggesteed by Hiraata
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`well beffore the ’935 patent wwas filed. FFor exampple, like Hirrata’s threaad slots, thhe
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`’935 paatent disclooses
`
`
`
`that
`thread ccontrollers
`
`
`
`
`
`each maanage a thrread.
`
`
`
`
`
`See ’935 patent, 3
`:34-
`
`
`
`37 (“Thhe thread
`
`
`
`controlllers 18-24
`each
`
`
`
`only rellease operaation
`
`
`
`
`
`codes 38-44 whenn the
`
`
`
`
`
`operatioon codes caan be executed withoout any pottential for ddelay in wwaiting for tthe
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`results oof previoussly issued ooperation ccodes.”). LLike Hirataa’s instructtion scheduule
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`unit, thee ’935 pateent disclosees an arbitrration moddule that seelects whicch operatioon
`
`
`
`
`
`
`
`
`
`
`
`
`
`code to execute. SSee id., 3:4
`
`
`
`
`
`8-51 (“Thee arbitratioon module
`
`
`
`
`
`14 receivees the
`
`
`
`operatioon codes 38-44 from the thread controllerrs 18-24 annd, based oon an
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`applicattion specifific prioritizzation scheme 46, ordders the opperation coddes to prodduce
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`orderedd operation codes 48.””). And likke Hirata’s
`
`
`
`
`
`
`
`
`
`
`
`
`
`functionall units, thee ’935 patennt
`
`
`
`disclosees a compuutation enggine that peerforms a ccomputatioon based onn the selectted
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`operatioon code. Seee id., 4:4-7 (“The coomputationn engine 122 . . . receivves the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`orderedd operation codes 48 aand generaates resultaants 50 therrefrom.”).
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`- 12 -
`
`

`
`Inter Partes Review of U.S. Patent No. 6,630,935 B1
`
`Independent claim 1 of the ’935 patent is directed to components illustrated
`
`in Figure 1—including the memory, computation engine, thread controllers, and
`
`arbitration module. Specifically, claim 1 recites:
`
`1. A computation module comprises:
`
`memory;
`
`a computation engine operable to perform an operation based
`on an operation code and to provide a corresponding result to the
`memory as indicated by the operation code;
`
`a plurality of thread controllers, wherein each of the plurality of
`thread controllers manages at least one corresponding thread of a
`plurality of threads, wherein the plurality of threads constitutes an
`application, and wherein each of the plurality of threads includes at
`least one operation code; and
`
`an arbitration module operably coupled to the plurality of
`thread controllers, wherein
`the arbitration module utilizes an
`application specific prioritization scheme to provide operation codes
`from the plurality of thread controllers to the computation engine in
`an order to minimize idle time of the computation engine.
`
`Id., 33:13-29 (emphasis added). The examiner allowed this claim because he
`
`believed that the claimed “arbitration module” is not taught or suggested by the
`
`prior art. See ’935 File History (Ex. 1008), Not. of Allow., 2. But, of course, it is.
`
`For example, Hirata discloses an instruction schedule unit that corresponds
`
`
`
`- 13 -
`
`

`
`
`
`Inter Partes Revieww of U.S. PPatent No.. 6,630,9355 B1
`
`
`
`
`
`
`
`
`
`
`
`to the cllaimed “arrbitration mmodule.” Seee Hirata,
`
`
`
`
`
`
`
`
`
`138, Fig. 22. Like the
`
`claimed
`
`
`
`
`
`
`
`
`
`
`
`“arbitraation moduule,” Hirataa’s instruction scheduule unit sellects whichh thread’s
`
`
`
`
`
`
`
`instructions to exeecute basedd on a dynaamic instruuction-priooritization scheme. Seee
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`id., 140
`
`
`
`
`-42, Fig. 44. In fact, HHirata’s priioritizationn scheme (iillustrated
`
`
`
`
`
`in Fig. 4) iis
`
`
`
`(illustratedd in Fig. 7)):
`
`
`
`
`
`
`
`
`
`remarkaably similaar the ’935 patent’s prioritizatioon scheme
`
`
`
`
`
`
`
`
`
`
`
`In all reelevant resppects, thesee figures are essentiaally the samme. The maain differennce
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`betweenn them is thhat Hirata’’s Figure 4 shows thee highest-ppriority threead at the ttop;
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`whereass the ’935 ppatent’s Fiigure 7 shoows the higghest-priorrity thread
`
`
`
`
`
`
`
`
`
`
`
`
`
`at the bottoom.
`
`
`
`In all otther respeccts, these fiigures illusstrate the saame thing——a schemme for
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`prioritizzing threadds in a multtithreaded processor.. See Horstt Dec., ¶ 400. So, the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`combination of Hiirata and KKimura discclose all asspects of inndependennt claim 1,
`
`
`
`
`
`
`
`
`
`
`
`
`
`as
`
`
`
`explaineed in greatter detail beelow. See iinfra Sectiion VII.A.11.
`
`
`
`
`
`
`
`
`
`
`
`
`
`UUnfortunateely, this infformation was not beefore the exxaminer duuring
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`- 14 -
`
`

`
`Inter Partes Review of U.S. Patent No. 6,630,935 B1
`
`prosecution. If it had been, the ’935 patent should not have been allowed.
`
`VI. Claim Construction
`
`Volkswagen contends that no term requires an express construction in this
`
`proceeding.4, 5 Instead, each claim term should be given its “broadest reasonable
`
`
`4 To the extent that the patent owner (Advanced Silicon Technologies
`
`(“AST”)) argues that certain claim terms should be construed according to 35
`
`U.S.C. § 112(f), the prior art applied below teaches or suggests all the limitations
`
`of the challenged claims even under such a construction. For example, even if the
`
`term “arbitration module” is construed under § 112(f), the combination of Hirata
`
`and Kimura teaches or suggests the “arbitration module” claimed and disclosed in
`
`the ’935 patent, as set forth below. See Section VII.A.
`
`5 In the related ITC investigation, AST tries to read graphics-processing
`
`limitations into claim 1. For example, AST’s proposed construction for
`
`“computation engine” is specialized graphics circuitry that receives and executes
`
`operation codes and generates results therefrom (emphasis added). Simi