Trials@uspto.gov
`571-272-7822
`
`
`
`
`
`Paper 24
`Entered: November 6, 2017
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`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`
`
`CPI CARD GROUP INC.,
`Petitioner,
`
`v.
`
`GEMALTO S.A.,
`Patent Owner.
`____________
`
`Case IPR2016-01092
`Patent 5,944,833
`____________
`
`
`
`Before TREVOR M. JEFFERSON, PATRICK M. BOUCHER, and
`TERRENCE W. McMILLIN, Administrative Patent Judges.
`
`BOUCHER, Administrative Patent Judge.
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. §318(a) and 37 C.F.R. § 42.73
`
`
`CPI Card Group Inc. (“Petitioner”) filed a Petition (Paper 2, “Pet.”) to
`institute an inter partes review of claims 1–26 of U.S. Patent No. 5,944,833
`(“the ’833 patent”), and we instituted review of claims 1–5, 7, 12–14, and
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`17–26. Paper 8 (“Dec.”), 23–24. We subsequently denied Petitioner’s
`Request for Rehearing (Paper 11) of our denial of review of claims 6, 8–11,
`15, and 16. Paper 14.
`During the trial, Patent Owner timely filed a Response (Paper 12, “PO
`Resp.”), to which Petitioner timely filed a Reply (Paper 15, “Reply”). An
`oral hearing was held on August 4, 2017, and a copy of the transcript was
`entered into the record. Paper 22 (“Tr.”).
`We have jurisdiction under 35 U.S.C. § 6. This Decision is a Final
`Written Decision under 35 U.S.C. § 318(a) as to the patentability of the
`claims on which we instituted trial. Based on the record before us, Petitioner
`has shown, by a preponderance of the evidence, that claims 1–5, 12–14, 17,
`19–21, and 23–26 are unpatentable, but has not shown that claims 7, 18, or
`22 are unpatentable.
`
`
`I. BACKGROUND
`A. The ’833 Patent
`The ’833 patent addresses security vulnerabilities in microprocessors
`that result from the predictable character of regularly timed clock pulses.
`Ex. 1001, col. 1, ll. 14–60. As the Specification explains, “microprocessors
`and microcomputers sequentially execute successive instructions of a
`program stored in a memory, in sync with one or more timing signals
`referenced relative to one of the clock signals supplied to the microprocessor
`or microcomputer.” Id. at col. 1, ll. 14–18. Such clock signals may be
`supplied either internally or externally. Id. at col. 1, ll. 18–19. Because the
`execution of each particular instruction breaks down into several steps timed
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`by the clock pulses, “it is possible to correlate the various phases of this
`program execution with the clock signals.” Id. at col. 1, ll. 20–23.
`The Specification provides examples of the types of vulnerabilities
`that may result. For instance, it is possible to determine the number of clock
`pulses delivered since the startup of a program, “or even the time that has
`elapsed since an event or an external or internal reference signal.” Id. at
`col. 1, ll. 39–43. As a consequence, “an ill-intentioned individual would
`thus be able to know the successive states of the processor and use this
`information to gain knowledge of certain internal output data.” Id. at col. 1,
`ll. 47–50. By exploiting the regularity of the clock pulses, information could
`be gleaned by a bad actor “on the output data or on the confidential content
`of the information, and in the case of cryptographic calculations, on the
`secret encryption key used.” Id. at col. 1, ll. 56–60. As Patent Owner
`summarizes, the objective of the ’833 patent is thus to render “observation of
`[the microprocessor’s] internal data values unobservable from outside.” PO
`Resp. 2.
`To accomplish this, the ’833 patent describes “decorrelating the
`running of at least one instruction sequence of a program from the internal or
`external signals of the circuit.” Ex. 1001, col. 2, ll. 9–11. In particular,
`decorrelation may be achieved with a random-number generator that enables
`desynchronizing execution of the program sequence in the processor. Id. at
`col. 2, ll. 18–21. Structure for achieving such decorrelation is illustrated in
`Figure 1 of the ’833 patent, which is reproduced below.
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`Figure 1 is a schematic diagram of electronic circuits of a microcomputer.
`Id. at col. 3, ll. 24–25.
`The microcomputer includes random-number generator 2, which can
`run on internal clock 11. Id. at col. 3, ll. 59–61. Internal clock 11 (“FRC”)
`may be embodied by “a free fixed frequency oscillator, de-synchronized and
`phase shifted relative to the external clock CLKE” of the microcomputer.
`Id. at col. 4, ll. 23–28. Random-number generator 2 either supplies a
`random value that is loaded into various devices of the microcomputer via
`data bus 3, or generates a pulse signal of variable periodicity at output 22.
`Id. at col. 4, ll. 40– 44. To serve as a clock for processor 1, this signal “must
`be sent” to calibration circuit 9, whose output 95 (i.e., “decorrelation clock”
`CLK2) is sent to multiplexing circuit 18. Id. at col. 4, ll. 50–53.
`Decorrelation clock CLK2, thus, results from modulation of internal clock
`11 with the output of random-number generator 2. See id. at col. 8, l. 50–
`col. 9, l. 36. Input 19 to multiplexing circuit 18 controls the multiplexing
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`with one or more bits of register 8, which can be loaded by random-number
`generator 2 or with a value determined by main program 5. Id. at col. 4, ll.
`52–57. That is, selection of whether the clock used for sequencing
`processor 1 is external clock CLKE or decorrelation clock CLK2 is
`determined either randomly or by main program 5. Id. at col. 4, ll. 57–63.
`Random interrupts may be generated similarly, by loading register R2 with a
`value determined by random number generator 2 or by main program 5. Id.
`at col. 5, ll. 20–23.
`
`
`B. Illustrative Claim
`Independent claim 4 is illustrative of the claims at issue:
`4. An improved integrated circuit comprising a microprocessor
`having a main program arranged to execute at least one
`instruction sequence in the microprocessor in synchronization
`with internal or external electrical signals of the integrated circuit
`and means for decorrelating an execution of the at least one
`instruction sequence of the main program from the internal or
`external signals of the integrated circuit so that the execution of
`the at least one instruction sequence is desynchronized with
`respect to the internal or external electrical signals.
`
`C. Instituted Grounds of Unpatentability
`Petitioner relies on the following references. Pet. 3.
`Sprunk
`US 5,404,402
`Apr. 4, 1995
`Griffin
`US 5,249,294
`Sep. 28, 1993
`Matsumura
`US 4,908,038 Mar. 13, 1990
`
`Ex. 1004
`Ex. 1005
`Ex. 1006
`
`
`
`
`
`
`
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`
`We instituted trial on the following bases. Dec. 23–24.
`Reference(s)
`Basis
`Claim(s) Challenged
`Sprunk
`§ 102(b) 4, 5, 7, 17–20, and 23–25
`Sprunk
`§ 103(a) 21 and 26
`Sprunk and Matsumura § 103(a) 1–3 and 12–14
`Sprunk and Griffin
`§ 103(a) 22
`
`
`D. Real Parties in Interest and Related Proceedings
`The parties identify only themselves as real parties in interest. Pet. 2;
`Paper 5, 1. The parties identify Gemalto S.A. v. CPI Card Group Inc., Civil
`Action No. 1:15-cv-02776 (D. Colo.) (“the related litigation”) as involving
`the ’833 patent. Pet. 2; Paper 5, 1.
`
`
`II. ANALYSIS
`A. Claim Construction
`The parties agree that the ’833 patent expired on March 7, 2017.
`Pet. 4; Paper 6, 2. Accordingly, we accord claim terms their ordinary and
`customary meaning, as would be understood by a person of ordinary skill in
`the art at the time of the invention. See Cisco Sys., Inc. v. AIP Acquisition,
`LLC, Case IPR2014-00247, slip op. at 2 (PTAB July 10, 2014) (Paper 20)
`(citing Phillips v. AWH Corp., 415 F.3d 1303, 1313–1317 (Fed. Cir. 2005)
`(en banc)). In doing so, “we look principally to the intrinsic evidence of
`record, examining the claim language itself, the written description, and the
`prosecution history, if in evidence.” DePuy Spine, Inc. v. Medtronic
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`Sofamor Danek, Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006) (citing Phillips,
`415 F.3d at 1312–17).1
`In the Institution Decision, we adopted preliminary constructions for
`several phrases recited in the form “means for . . . ,” construing those
`phrases in accordance with 35 U.S.C. § 112, ¶ 6, as “cover[ing] the
`corresponding structure, material, or acts described in the specification and
`equivalents thereof.” Dec. 6 (citing Williamson v. Citrix Online, LLC, 792
`
`
`1 We disagree with Patent Owner’s suggestion during the oral hearing
`that application of a district-court-type claim construction during post grant
`proceedings before the Board “introduces the concept of preserving the
`validity of the claims.” See Tr. 68:16–22. While a presumption of validity
`is applied by district courts in accordance with 35 U.S.C. § 282, any
`implication that § 282 must also be applied in proceedings before the Office
`“miscontrues the purposes for which that statute [was] enacted.” In re Etter,
`756 F.2d 852, 856 (Fed. Cir. 1985) (en banc). “A statute setting rules of
`procedure and assigning burdens to litigants in a court trial does not
`automatically become applicable to proceedings before the PTO.” Id.
`Although Etter considered application of a presumption of validity in
`the context of reexamination proceedings, its reasoning equally applies to
`inter partes review proceedings in light of the Supreme Court’s explicit
`recognition that “the purpose of [an inter partes review] proceeding is not
`quite the same as the purpose of district court litigation.” Cuozzo Speed
`Techs., LLC v. Lee, 136 S.Ct. 2131, 2144 (2016). “Although Congress
`changed the name from ‘reexamination’ to ‘review,’ nothing convinces us
`that, in doing so, Congress wanted to change its basic purposes, namely, to
`reexamine an earlier agency decision.” Id. In Cuozzo, the Supreme Court
`explicitly endorsed the Office’s use of the broadest-reasonable-interpretation
`standard for unexpired patents by analogy with reexamination proceedings;
`it logically follows by the same analogy that the Office’s use, in
`reexamination proceedings, of a claim construction standard similar to that
`used by district courts, but without a presumption of validity, applies to inter
`partes review proceedings.
`
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`F.3d 1339, 1348 (Fed. Cir. 2015)).2 Of those preliminary constructions,
`Patent Owner disputes only the “means for decorrelating,” recited in each of
`independent claims 1, 2, and 4. See PO Resp. 3–6. Based on the complete
`record developed during the trial, we see no compelling reason to alter our
`constructions of the other “means for . . .” limitations, summarized in the
`table below by identifying the recited function and the corresponding
`structure described in the Specification of the ’833 patent. Accordingly, we
`adopt them for this Final Written Decision. See Dec. 10–13.
`Claim Limitation
`Function
`Structure
`“means for generating
`generation of one of (1)
`an internal clock, a
`one of a timing signal,
`a timing signal, and (2)
`random number
`and a sequence of
`a sequence of clock
`generator, and a
`clock pulses which is
`pulses dispatched at
`calibration circuit
`dispatched at random
`random times
`times”
`“means for randomly
`generating interrupts”3
`
`randomly generating
`interrupts
`
`a random number
`generator, a register,
`and a logic circuit
`a main program and a
`secondary program
`
`triggering the
`execution of a
`secondary sequence
`execution of a
`secondary program
`
`“means for triggering
`the execution of a
`secondary program”
`“means for execution
`of a secondary
`program”
`“means for phase
`shifting the timing,
`synchronization or
`status signals of the
`processor”
`
`2 Section 112, paragraph 6, was recodified by the America Invents Act as
`Section 112(f).
`3 Although not recited as a means-plus-function limitation, we construe the
`related phrase of a “random interrupt generating system” as including
`similar components. Dec. 11.
`
`a main program
`
`shift registers and a
`multiplexer
`
`shifting the timing,
`synchronization, or
`status signals of a
`processor
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`“means for decorrelating”
`Each of independent claims 1, 2, and 4 recites “means for
`decorrelating an execution of the at least one instruction sequence of the
`[main] program from the internal or external electrical signals of the
`integrated circuit so that the execution of the at least one instruction
`sequence is desynchronized with respect to the internal or external electrical
`signals,” including or omitting the word “main” in accordance with an
`antecedent in the respective claims.
`The “so that the execution . . .” recitations were added by amendment
`during prosecution after rejections under 35 U.S.C. § 112, ¶¶ 1 and 2, in
`which the Examiner determined that “[t]he process or act of ‘decorrelating’
`is not sufficiently described to determine what this is and how it is
`accomplished.” Ex. 1002, 206–07, 217–30. With the amendments, the
`applicant explained that “[s]imply stated, decorrelation is the opposite of
`correlation, i.e., in the context of this application, the opposite of an
`operation which is correlated to a sequencing clock.” Id. at 223.
`Petitioner’s expert, Nathanial Polish, Ph.D., opines that “[w]ith this
`amendment, the patent applicant is clarifying that decorrelation requires the
`desynchronization of ‘the execution of the at least one instruction sequence’
`with ‘respect to the internal or external electrical signals.’” Ex. 1003 ¶ 45.
`Petitioner relies on the express language of the claims, the prosecution
`history, and this testimony of its expert to contend that a person of ordinary
`skill in the art “would have understood the claimed function is
`desynchronizing the execution of instructions by the microprocessor with
`respect to internal or external electrical signals.[]” Pet. 6 (citing Ex. 1003
`§ 45).
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`In addressing the structural aspect of the construction, Petitioner
`observes that the Specification includes a “recitation that ‘the decorrelation
`means comprise one or more circuits generating a sequence of clock or
`timing pulses which are dispatched at random times.’” Pet. 6–7 (quoting Ex.
`1001, col. 2, ll. 18–21; citing Ex. 1003 ¶ 47).4 Figure 1 of the ’833 patent,
`reproduced above, illustrates that random clock CLK2 desynchronizes
`execution of instructions in microprocessor 1 from external clock CLKE,
`and that CLK2 is generated with internal clock 11, random number
`generator 2, and calibration circuit 9. See Ex. 1001, col. 2, ll. 18–21, col. 3,
`ll. 59–61, col. 4, ll. 23–28. Figures 3A and 3B of the ’833 patent are
`reproduced below.
`
`
`4
`In the body, we consider what Petitioner characterizes as the “first” of
`“a few structures” that Petitioner contends the Specification “links” to the
`“means for decorrelating.” Pet. 6. Petitioner additionally provides analysis
`for “second” and “third” structures that it describes as similarly “linked,” but
`argues that each of those structures “should not be construed as
`corresponding to the [claimed] means for decorrelating.” Id. at 11, 14.
`In its Response, Patent Owner does not contest Petitioner’s positions
`with respect to the “second” and “third” structures, instead presenting a
`further distinct position that relies on a different formulation of the function
`performed by the “means for decorrelating.” See PO Resp. 4–6; see infra.
`Accordingly, we limit ourselves to considering Petitioner’s “first” position
`and to considering the position presented by Patent Owner in its Response.
`See Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir.
`1999) (stating that only those terms in controversy need to be construed, and
`only to the extent necessary to resolve the controversy).
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`Figure 3A (top) is a block diagram of calibration circuit 9, and Figure 3B
`(bottom) represents logical sequencing diagrams of calibration circuit 9. Id.
`at col. 3, ll. 28–31. Calibration circuit 9 receives output FRC of internal
`clock 11 on line 111, and NAND gates 90, 91, JK flip flops 93, 94, and
`inverter 92 modulate internal clock FRC with output I on line 22 of random
`number generator 2 to generate CLK2 for driving microprocessor 1. Id. at
`col. 8, ll. 50–62.
`In light of these disclosures, and consistent with the Institution
`Decision, we identify a structure corresponding to the “means for
`decorrelating” as an internal clock, a random number generator, and a
`calibration circuit. Dec. 9.
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`Patent Owner disputes the identified function for the “means for
`decorrelating,” and instead quotes the Specification in contending that the
`function should be:
`[To enable] the microprocessor running the main program to go
`from an operation that is perfectly in phase and correlated to the
`external sequencing clock, to a decorrelated operation in which,
`as desired and depending on the embodiment chosen, the
`execution time of a given instruction will no longer be identical,
`even when the same instruction is executed several times, or in
`which the execution duration of an instruction sequence will be
`variable even if the same sequence is re-executed several times
`by the main program, or even in which the execution duration of
`an instruction will be variable, the execution time of the same
`instruction itself being variable.
`
`PO Resp. 5 (quoting Ex. 1001, col. 4, ll. 12–23; citing Ex. 2001 ¶¶ 59–62;
`Ex. 2005). Patent Owner contends that this function is supported by the
`prosecution history, quoting the following excerpt (which was also partially
`quoted by Petitioner as support for its identification of the appropriate
`function):
`Simply stated, decorrelation is the opposite of correlation, i.e., in
`the context of this application, the opposite of an operation which
`is correlated to a sequencing clock. The Examiner’s attention is
`invited to . . . page 3, lines 1-4, . . . “the decorrelation means
`comprise a random number generator which makes it possible to
`desynchronize the execution of the program sequence in the
`processor.” This is further described at page 6, lines 6-18,
`indicating a certain number of elements added a microprocessor
`and a random number generator, which will allow the
`microprocessor running the main program to go from an
`operation that is perfectly in phase and correlated to the external
`sequencing clock to a decorrelated operation in which, as desired
`and depending on the embodiment chosen, the execution time of
`a given instruction no longer is identical, even when the same
`instruction is executed several times, or in which the execution
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`duration of an instruction sequence is variable even if the same
`sequence is re-executed several times by the main program or in
`which the execution duration of an instruction is variable.
`
`PO Resp. 5–6 (quoting Ex. 1002, 223–24) (alterations by Patent Owner).
`Patent Owner’s proposed construction is deficient because it fails to
`identify corresponding structure described in the Specification for
`performing the proposed function. See Williamson at 1351 (“Construing a
`means-plus-function claim term is a two-step process. The court must first
`identify the claimed function. . . . Then, the court must determine what
`structure, if any, disclosed in the specification corresponds to the claimed
`function.) (citation omitted, emphases added).5 In addition, the function
`proposed by Patent Owner as performed by the “means for decorrelating”
`includes multiple functional variations that are not recited in the claim itself.
`Although the Specification and prosecution history serve important roles in
`claim construction, the Federal Circuit has repeatedly warned against
`importing limitations from the specification into the claims. Phillips at
`1323. Patent Owner’s proposed function for the “means for decorrelating”
`improperly attempts to import such limitations.
`
`
`5 When questioned at the oral hearing about this omission, Patent Owner
`referred to the structure identified in the Institution Decision as part of our
`preliminary construction, i.e. an internal clock, a random number generator,
`and a calibration circuit. Tr. 48:21–50:22. But that structure was identified
`for a different function than the one proposed by Patent Owner in its
`Response, which includes insufficient explanation how those components
`are disclosed by the ’833 patent to perform all the functional variations
`within Patent Owner’s proposal.
`
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`Furthermore, although we recognize that both parties provide expert
`testimony in support of their respective identifications of the function (Ex.
`1003 ¶ 45; Ex. 2001 ¶ 59), the Federal Circuit has also warned that
`“extrinsic evidence in general [is] less reliable than the patent and its
`prosecution history in determining how to read claim terms.” Phillips at
`1318. Expert testimony, in particular, “can suffer from bias that is not
`present in intrinsic evidence.” Id. Thus, although we have considered the
`testimony of both experts, we accord it less weight than the intrinsic
`evidence in arriving at our construction of the “means for decorrelating.”6
`Consistent with the preliminary construction applied in the Institution
`Decision, we construe “means for decorrelating” for this Final Written
`Decision as having the function of desynchronizing the execution of
`instructions by the microprocessor with respect to internal or external
`signals, with corresponding structure of an internal clock, a random number
`generator, and a calibration circuit.
`
`
`
`6 Petitioner contends that we should “discount” the testimony of Patent
`Owner’s expert, Çetin Kaya Koç, Ph.D., “in its entirety.” Reply 2. Dr. Koç
`testifies that the opinions in his Declaration “take into consideration the
`Board’s construction as well as the more specific meaning found in the ’833
`Patent,” Ex. 2001 ¶ 62, but, according to Petitioner, “a review of Dr. Koc’s
`declaration reveals that on the few times he actually applied a construction
`of the function for the means for decorrelating, he applied [Patent Owner’s]
`proposed construction, not the Board’s.” Reply 2. Although the specific
`manner in which Dr. Koç applies a claim construction may legitimately
`affect the weight accorded to his testimony on specific issues, Petitioner has
`not filed a motion to exclude Dr. Koç’s Declaration, and the Reply
`articulates insufficient basis for wholesale rejection of the entirety of Dr.
`Koç’s opinions.
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`B. Level of Skill in the Art
`Supported by their respective experts, the parties make similar
`contentions regarding the educational background of a person of ordinary
`skill in the art, but disagree with respect to the industry experience of such
`an individual. Pet. 22 (citing Ex. 1003 ¶ 20); PO Resp. 3 (citing Ex. 2001
`¶ 31). Petitioner contends that, at the time of filing the application that
`matured into the ’833 patent, a person of ordinary skill in the art would have
`had at least bachelor’s degree in “computer science, electrical or computer
`engineering, or a related field of study,” while Patent Owner contends that
`such a person would have had a bachelor’s degree in “computer science or
`computer engineering.” Pet. 22; PO Resp. 3. As far as industry experience,
`Petitioner contends that a person of ordinary skill in the art would have had
`“four or more years of industry experience relating to secure integrated
`circuits.” Pet. 22. Patent Owner contends that such extensive experience “is
`unnecessary” and proposes that a person of skill in the art would have had
`“sufficient industry experience to have had a working knowledge of
`computer architecture, i.e., approximately 1 year of experience in computer
`architecture design.” PO Resp. 3.
`The record provides relatively little basis to discriminate between the
`parties’ proposals, although we agree with Patent Owner that the level of
`industry experience proposed by Petitioner seems unjustifiably high.
`Nevertheless, the conclusions we set forth herein do not turn on the
`distinctions between the levels of skill in the art proposed by the parties. We
`adopt a level of skill that includes at least a bachelor’s degree in computer
`science, electrical or computer engineering, or a related field of study, and at
`least two years of industry experience in computer architecture.
`
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`C. Sprunk
`Sprunk “enhances the security of a secure microprocessor by
`rendering it extremely difficult, if not impossible, to observe a clock signal
`and predict the occurrence of subsequent clock pulses therefrom.” Ex. 1004,
`col. 3, ll. 35–39. This is accomplished “by modulating the signal which
`clocks the processor on a pseudorandom basis to render the time at which
`each successive clock pulse occurs completely unpredictable.” Id. at col. 3,
`ll. 42–46. As Sprunk explains, such clock-signal modulation “is designed to
`resist analysis attempts of a pirate.” Id. at col. 7, ll. 25–29.
`Figure 1 of Sprunk, reproduced below, illustrates.
`
`
`Figure 1 is a block diagram of a cryptographic processor that is “clocked by
`a random and unpredictable clock signal.” Id. at col. 3, ll. 11–13.
`Unpredictable pulse stream CLK is output from variable frequency source
`10, variably tuned or selected using substantially random modulation circuit
`12, and used to clock crypto processor 14 for encryption or decryption of
`data entered via terminal 16. Id. at col. 4, ll. 5–13.
`Details of substantially random modulation circuit 12 are illustrated in
`Figures 2 and 3 of Sprunk, reproduced below.
`
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`In similar illustrations, Figure 2 (left) and Figure 3 (right) show substantially
`random modulation circuit 12 as comprising a series of delay stages 24,
`multiplexer 26, a plurality of linear feedback shift register generators
`(“LFSRGs”) 28 and, optionally, substitution box (“S-Box”) 30. Id. at col. 4,
`ll. 36–40. LFSRGs 28 and S-Box 30 provide control signals that multiplexer
`26 uses to select one of the delays provided by delay stages 24 for each
`clock pulse. Id. at col. 4, ll. 40–43. A detailed understanding of the various
`specific ways that Sprunk performs the delay selection is unnecessary for
`our analysis; it is sufficient to observe that Sprunk teaches that such delay
`selection results in providing a clock signal “modulated to provide a
`substantially random . . . and unpredictable series of clock pulses for
`clocking a secure microprocessor.” Id. at col. 7, ll. 25–28.
`
`
`1. Anticipation of Independent Claim 4
`Petitioner challenges independent claim 4 as anticipated under 35
`U.S.C. § 102(b) by Sprunk. Pet. 26–28. “To be anticipatory, a reference
`must describe, either expressly or inherently, each and every claim limitation
`and enable one of skill in the art to practice an embodiment of the claimed
`invention without under experimentation.” Am. Calcar, Inc. v. Am. Honda
`
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`Patent 5,944,833
`
`Motor Co., Inc., 651 F3.d 1318, 1341 (Fed. Cir. 2012) (citing In re Gleave,
`560 F.3d 1331, 1334 (Fed. Cir. 2009))
`Petitioner presents an analysis in which it parses the claim as reciting
`an “improved integrated circuit” that comprises two components: “a
`microprocessor having a main program” and “means for decorrelating,” each
`of which is further defined by the claim. Pet. 26–28. We agree that this is
`the natural reading of the claim and address Patent Owner’s different parsing
`of the claim below. See infra, Section II.C.1.b.
`Petitioner addresses the first component by observing that Sprunk’s
`microprocessor executes instructions of an algorithm in synchronization
`with a clock signal, thereby disclosing “a microprocessor having a main
`program arranged to execute at least one instruction sequence . . . in
`synchronization with internal or external signals of the integrated circuit.”
`Pet. 26 (citing Ex. 1004, col. 2, ll. 11–13).
`Petitioner addresses the second component by pointing to the
`illustration in Figure 1 of Sprunk, in which “Sprunk desynchronizes the
`execution of instructions by the microprocessor 14 from internal clock 10 by
`modulating the output of the clock 10 with a random function to provide the
`microprocessor 14 with a random clock signal.” Id. at 27 (citing Ex. 1004,
`col. 2, ll. 7–13, col. 1, ll. 50–54). Noting that the random modulation of
`internal clock 10 is performed with a random number generator in the form
`of LFSRGs, Petitioner identifies the desynchronization function as
`performed by an internal clock (clock 10), a random number generator
`(LFSRG 0 – LFSRG 2), and a calibration circuit (circuit 12). Id. at 28. This
`analysis is consistent with our construction of “means for decorrelating”
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`IPR2016-01092
`Patent 5,944,833
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`because it identifies both the function and structure that define that
`construction.
`Based on these identifications, Petitioner demonstrates, by a
`preponderance of the evidence that claim 4 is anticipated by Sprunk.
`Patent Owner draws two distinctions in response, neither of which is
`persuasive. First, Patent Owner contends that Sprunk’s invention is
`embodied on two separate chips (“two-chip theory”). PO Resp. 6, 7, 11–16,
`18, 20, 21, 25, 31, 32, 34, 42, 55. Second, Patent Owner contends that
`Sprunk’s operation is not controlled by a “main program” (“main-program
`control theory”). Id. at 16–18, 20, 29, 33, 34, 50, 55. We address each of
`these purported distinctions in turn below.
`
`
`a. Two-Chip Theory
`In presenting its two-chip theory, Patent Owner effectively gives
`weight to the preamble (“An improved integrated circuit”) by arguing that
`“Sprunk does not teach ‘an improved integrated circuit’ with a decorrelation
`means as required by these claims, but instead teaches conventional separate
`[integrated circuits], which are fundamentally different.” PO Resp. 10; see
`Tr. 39:15–23 (Patent Owner asserting at oral hearing that “‘improved’ needs
`to be taken into consideration”). Patent Owner specifically contends that
`“the ‘means for decorrelating’ must be in the same [integrated circuit] in
`which the execution of at least one of the program’s instruction sequences is
`decorrelated from the electrical signals of the [integrated circuit].” PO Resp.
`10. Patent Owner further contends that this “single [integrated circuit]
`requirement is confirmed by the specification [of the ’833 patent], which
`repeatedly refers to the microprocessor or microcomputer type as being
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`‘monolithic,’ i.e., a single [integrated circuit].” Id. at 11 (citing Ex. 1001,
`col. 3, ll. 52–58, col. 10, ll. 40–44, col. 7, l. 40, col. 10, ll. 41, 45, 49, 52, 55,
`58, 60).
`“Generally, . . . the preamble does not limit the claims.” DeGeorge v.
`Bernier, 768 F.2d 1318, 1322 n.3 (Fed. Cir. 1985). But we need not decide
`whether the preamble is limiting in this instance because, as Petitioner
`contends, Sprunk “expressly describes that its invention can be embodied on
`a single chip.” Reply 3. In addressing the preamble, under the assumption
`that “it is limiting,” the Petition observes that Sprunk discloses that the
`embodiment of Figure 2 “can be implemented in very large scale integration
`(VLSI) using a minimum area for the modulator.’” Pet. 26 (citing Ex. 1001,
`col. 5, ll. 40–42; Ex. 1003 ¶ 94). Petitioner’s expert, Dr. Polish, testifies that
`a person of ordinary skill in the art would have understood such very large
`scale integration, using a minimum area for the modulator, “to be an
`integrated circuit.” Ex. 1003 ¶ 94.
`Patent Owner, supported by testimony of its expert, Dr. Koç, disputes
`that interpretation, arguing that “Sprunk describes the crypto processor in
`Fig. 1 as a ‘conventional crypto processor,’ i.e., a separate integrated circuit,
`encapsulated in a package, which cannot be opened without destroying the
`crypto processor.” PO Resp. 13 (citing Ex. 1004, col. 4, ll. 9–13; E