Trials@uspto.gov
`571-272-7822
`
` Paper No. 36
`
` Entered: November 24, 2016
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`EMC CORPORATION,
`Petitioner,
`
`v.
`
`INTELLECTUAL VENTURES II LLC,
`Patent Owner.
`____________
`
`Case IPR2016-01106
`Patent 6,516,442 B1
`____________
`
`
`
`Before JUSTIN T. ARBES, BRIAN J. McNAMARA, and MINN CHUNG,
`Administrative Patent Judges.
`
`CHUNG, Administrative Patent Judge.
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`
`I. INTRODUCTION
`In this inter partes review, instituted pursuant to 35 U.S.C. § 314,
`EMC Corporation (“Petitioner”) challenges the patentability of claims 1, 5,
`9, 10, 12, 24, 28, 32, 33, and 34 (the “challenged claims”) of U.S. Patent
`No. 6,516,442 B1 (Ex. 1001, “the ’442 patent”), owned by Intellectual
`Ventures II LLC (“Patent Owner”). The Board has jurisdiction under
`35 U.S.C. § 6. This Final Written Decision is entered pursuant to 35 U.S.C.
`§ 318(a) and 37 C.F.R. § 42.73. With respect to the grounds instituted in
`this trial, we have considered the papers submitted by the parties and the
`evidence cited therein. For the reasons discussed below, we determine
`Petitioner has shown by a preponderance of the evidence that claims 1, 5, 9,
`10, 12, 24, 28, 32, 33, and 34 of the ’442 patent are unpatentable.
`
`II. BACKGROUND
`A. Procedural History
`On May 27, 2016, Petitioner filed a Petition (Paper 3, “Pet.”)
`requesting an inter partes review of claims 1, 2, 5, 9, 10, 12, 24, 25, 28, 32,
`33, and 34 of the ’442 patent. Patent Owner filed a Preliminary Response
`(Paper 7, “Prelim. Resp.”). On November 30, 2016, we instituted an inter
`partes review of claims 1, 5, 9, 10, 12, 24, 28, 32, 33, and 34 of the ’442
`patent. Paper 9 (“Dec. on Inst.”), 50.
`After institution, Patent Owner filed a Patent Owner Response (Paper
`15, “PO Resp.”), to which Petitioner filed a Reply (Paper 18, “Pet. Reply”).
`In addition, Patent Owner filed a Motion for Observations on certain
`cross-examination testimony of Douglas W. Clark, Ph.D. (Paper 26, “Obs.”),
`to which Petitioner filed Responses (Paper 28, “Obs. Resp.”). An oral
`
`2
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`hearing was held on September 7, 2017. A transcript of the hearing is
`included in the record as Paper 35 (“Tr.”). After the hearing, upon our
`authorization, Patent Owner filed a Patent Owner Sur-Reply (Paper 33, “PO
`Sur-Reply”), in response to which Petitioner filed a Sur-Sur-Reply (Paper
`34, “Pet. Sur-Sur-Reply”).
`
`B. Related Proceedings
`According to the parties, the ’442 patent has been asserted in the
`following patent infringement cases: Intellectual Ventures I LLC v. HCC
`Insurance Holdings, Inc., No. 6:15-cv-660 (E.D. Tex.); Intellectual Ventures
`II LLC v. Kemper Corp., No. 6:16-cv-81 (E.D. Tex.); Intellectual Ventures I
`LLC v. Lenovo Group Ltd., No. 1:16-cv-10860 (D. Mass.); and Intellectual
`Ventures I LLC v. NetApp, Inc., No. 1:16-cv-10868 (D. Mass.). Pet. 2–3;
`Paper 6, 1.
`
`C. The ’442 Patent
`1. Background
`As background, the ’442 patent describes that, in conventional
`symmetric multiprocessor (SMP) systems, a shared system bus is used for
`memory access by the processors. Ex. 1001, col. 1, ll. 18–21. In such
`systems, transactions between the processors and the memory take place one
`at a time over the shared bus. Id. at col. 1, ll. 30–32. According to the ’442
`patent, the serial availability of the shared bus ensures that the transactions
`are performed in a well-defined order. Id. at col. 1, ll. 32–33. Such strong
`transaction ordering also is necessary to support cache coherency, i.e.,
`coherent state management of the caches associated with each processor. Id.
`at col. 1, ll. 21–24, 33–35.
`
`3
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`
`According to the ’442 patent, a shortcoming of the traditional SMP
`system is that, as more processors are added to the traditional SMP system,
`the serial or sequential nature of the transactions leads to saturation of the
`shared system bus, limiting the performance and scalability of the system.
`Id. at col. 1, ll. 36–40. Hence, the ’442 patent identifies a need for an SMP
`system architecture that provides greater scalability and increased
`transaction throughputs by permitting concurrent use of multiple buses,
`while still providing a system serialization point to maintain strong
`transaction ordering and cache coherency. Id. at col. 1, ll. 41–46.
`
`2. Described Invention
`The ’442 patent describes a symmetric multiprocessor system that
`includes a switched fabric, such as a switch matrix, which provides multiple
`concurrent buses for transferring data between processors and shared
`memory. Id. at col. 1, ll. 49–53, Abstract.
`
`4
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`
`Figure 3 of the ’442 patent is reproduced below.
`
`
`
`Figure 3 illustrates an embodiment of a symmetric multiprocessor system
`using a Flow-Control Unit (FCU) based on a switched fabric data path
`architecture. Id. at col. 2, ll. 1–9. Figure 3 describes internal detail of the
`components of the multiprocessor system depicted in Figure 2 (not
`reproduced herein). Id. As shown in Figure 3, FCU 220 includes a Data
`Switch, which is also referred to as a Simultaneous Switched Matrix (SSM)
`or switched fabric data path. Id. at col. 3, ll. 6–9. The Data Switch provides
`for parallel routing of data between multiple initiators and multiple targets
`(or destinations), such as CPUs and memory devices. Id. at col. 4, ll. 30–37.
`The multiple, simultaneous data transfers over the Data Switch take
`place via a series of interfaces between the initiators and the targets. As
`
`5
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`depicted in Figures 2 and 3, CPU 120 and memory units 1300–1303
`exchange data with processor and memory interfaces, namely, Dual CPU
`Interface Unit (DCIU) 210 and Memory Control Unit (MCU) 230,
`respectively. Id. at col. 2, ll. 65–67, col. 3, ll. 26–31, Figs. 2, 3. The DCIU
`and MCU, in turn, communicate with another set of interfaces on the switch
`or FCU side over point-to-point interconnect buses or channels 112 and 114,
`respectively, to transfer data through the Data Switch. Id. at col. 2, ll. 50–
`65, col. 3, ll. 36–42, col. 4, ll. 45–49, 59–65, Fig. 3.
`As illustrated in Figure 3, each of these interfaces uses a common
`block called the Channel Interface Block (CIB) to communicate over a
`channel. Id. at col. 7, ll. 38–42, Fig. 3. The ’442 patent describes that each
`end of a channel is connected to a CIB (id. at col. 1, ll. 55–56) and that the
`CIBs are the “transmit and receive interface[s]” for the channel connections
`to and from the FCU. Id. at col. 5, ll. 20–22. In other words, all
`communications or data transfers over the FCU take place between a pair of
`CIBs positioned across a channel. Id. at col. 6, ll. 65–66 (“Each packet is
`exchanged between CIB transceivers . . . .”), col. 7, ll. 38–42, Fig. 3.
`According to the ’442 patent, a channel “of the present invention is a
`general-purpose, high-speed, point-to-point, full-duplex, bi-directional
`interconnect bus suitable for use in a broad range of applications including
`computer memory, I/O, CPU, switching/routing, or any other application
`where high bandwidth and low latency is required.” Id. at col. 6, ll. 40–45.
`In an exemplary embodiment, the CIB forms a logical interface to a channel,
`providing a communication path (i.e., a channel) between a pair of CIBs,
`such as the CIB pair between the DCIU and the FCU, or the CIB pair
`
`6
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`between the FCU and the MCU. Id. at col. 1, ll. 56–58, col. 5, ll. 20–24,
`col. 6, ll. 50–52. A CIB comprises two subparts: namely, transceivers
`connected to a channel, and the CIB logic which forms the interface between
`the transceivers and the “core-logic” (i.e., the internal circuits) of the chip or
`device to which the CIB belongs (i.e., the DCIU, MCU, or FCU). Id. at
`col. 7, ll. 48–51, 57–58, col. 5, ll. 23–24. Reflecting the full-duplex, bi-
`directional nature of the channels, the CIB provides a full-duplex,
`bidirectional interface between the channel, the transceivers, and the core-
`logic. Id. at col. 15, ll. 23–26.
`A “packet” is a basic unit of transport over a channel. Id. at col. 6,
`l. 53. In one embodiment, a packet is a single 80-bit frame exchanged
`between CIBs. Id. at col. 6, ll. 54–55. A packet frame may include payload
`data, control information, and error correction code (ECC) bits.1 Id. at
`col. 6, ll. 54–63.
`In addition to their data transport functions, the CIBs also perform
`error detection and error correction functions for the data transmitted over
`the channels. Id. at col. 15, ll. 42–45. The CIB logic generates ECC bits,
`detects errors, and invokes a transmit retry procedure for error recovery. Id.
`at col. 19, ll. 3–5. According to the ’442 patent, although the ECC error
`detection code may be used for single-bit error correction, this is not done in
`the disclosed system. Instead, the data transfer is retried using a transport
`retry protocol. Id. at col. 16, ll. 50–55, col. 19, ll. 55–58, col. 20, l. 10–
`col. 25, l. 25. Further, the channel transport protocol implemented in the
`
`
`1 The ’442 patent describes ECC bits as “error detection bits” or an “error
`detection code.” Ex. 1001, col. 15, ll. 46–49, col. 16, ll. 50–55.
`7
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`CIB provides reliable data transfer over the channels in the face of errors and
`limited buffering. Id. at col. 1, ll. 60–64, col. 25, ll. 28–32.
`In addition to the Data Switch, FCU 220 includes Transaction
`Controller 400, which provides a single system-serialization point through
`which all transactions over the FCU must pass. Id. at col. 3, ll. 55–58, 62–
`63. By guaranteeing that all transactions pass through the system-
`serialization point, a precise order of transactions can be defined. Id. at
`col. 3, ll. 58–61. The Transaction Controller also provides cache coherency
`support for the CPUs by maintaining the coherency state of each CPU with a
`duplicate set of the CPU’s L2 cache-tags stored in the Transaction
`Controller. Id. at col. 3, ll. 9–13, 63–65. Cache coherence ensures that the
`CPU caches are updated reflecting system transactions so that all software
`executing in the system is well-behaved. Id. at col. 1, ll. 21–25. The
`Transaction Controller acts as the system-serialization and cache coherence
`point, “ensuring that all transactions in the system occur in a defined order,
`obeying defined rules.” Id. at col. 3, l. 66–col. 4, l. 2.
`
`3. Illustrative Claim
`Of the challenged claims, claims 1 and 24 are independent. Claim 1 is
`illustrative of the challenged claims and is reproduced below:
`1.
`A shared-memory multi-processor system comprising:
`a switch fabric configured to switch packets containing
`
`data;
`
`a plurality of channels configured to transfer the packets;
`a plurality of switch interfaces configured to exchange the
`packets with the switch fabric, exchange the packets over the
`channels, and perform error correction of the data in the packets
`exchanged over the channels;
`
`8
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`
`a plurality of microprocessor interfaces configured to
`exchange the data with a plurality of microprocessors, exchange
`the packets with the switch interfaces over the channels, and
`perform error correction of the data in the packets exchanged
`over the channels; and
`a memory interface configured to exchange the data with
`a memory device, exchange the packets with the switch
`interfaces over the channels, and perform error correction of the
`data in the packets exchanged over the channels.
`
`
`Ex. 1001, col. 36, ll. 27–44.
`
`
`D. Applied References and Declarations
`Petitioner relies upon the following references in its challenges to
`patentability:
`
`Designation
`Reschke2
`Nishtala
`
`Reference
`U.S. Patent No. 5,490,250 (Feb. 6, 1996)
`U.S. Patent No. 5,581,729 (Dec. 3, 1996)
`
`Pet. 4. Petitioner also relies on the Declaration (Ex. 1002) and Reply
`Declaration (Ex. 1028) of Douglas W. Clark, Ph.D. in support of its Petition
`and Reply, respectively. Patent Owner relies on the Declaration of Donald
`Alpert, Ph.D. (Ex. 2020) in support of its Patent Owner Response.
`
`Exhibit No.
`Ex. 1003
`Ex. 1004
`
`
`2 For clarity and ease of reference, we only list the first named inventor.
`
`9
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`
`E. Instituted Grounds of Unpatentability
`We instituted inter partes review of the challenged claims based on
`the following specific grounds (Dec. on Inst. 50).
`
`Claims Challenged
`
`Statutory Basis
`
`Reference(s)
`
`1, 12, 24, and 34
`5, 9, 10, 28, 32, and 33
`
`§ 103(a)
`§ 103(a)
`
`Reschke
`Reschke and Nishtala
`
`III. CLAIM CONSTRUCTION
`In an inter partes review, claim terms in an unexpired patent are given
`their broadest reasonable construction in light of the specification of the
`patent in which they appear. 37 C.F.R. § 42.100(b); see Cuozzo Speed
`Techs., LLC v. Lee, 136 S. Ct. 2131, 2144–46 (2016) (upholding the use of
`the broadest reasonable interpretation standard as the claim construction
`standard to be applied in an inter partes review proceeding). Under the
`broadest reasonable interpretation standard, and absent any special
`definitions, claim terms generally are given their ordinary and customary
`meaning, as would be understood by one of ordinary skill in the art in view
`of the specification. In re Translogic Tech. Inc., 504 F.3d 1249, 1257 (Fed.
`Cir. 2007). Any special definitions for claim terms or phrases must be set
`forth with reasonable clarity, deliberateness, and precision. In re Paulsen,
`30 F.3d 1475, 1480 (Fed. Cir. 1994). A particular embodiment appearing in
`the written description generally is not incorporated into a claim if the claim
`language is broader than the embodiment. SuperGuide Corp. v. DirecTV
`Enterprises, Inc., 358 F.3d 870, 875 (Fed. Cir. 2004); In re Van Geuns, 988
`F.2d 1181, 1184 (Fed. Cir. 1993).
`
`10
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`
`In our Decision on Institution, we preliminarily interpreted three claim
`terms as follows.
`
`Term
`
`“packet”
`“channel”
`
`“switch fabric”
`
`Construction
`“a basic unit of transport over a channel”
`“a general-purpose, high-speed, point-to-point,
`full-duplex, bi-directional interconnect bus”
`
`“a data switching circuitry having a matrix or
`similar arrangement of interconnections”
`
`Dec. on Inst. 9–19.
`The parties do not dispute the construction of “channel” in their Patent
`Owner Response or Petitioner Reply. PO Resp. 36; Pet. Reply 1–15. Upon
`considering the complete record, we discern no reason to deviate from our
`preliminary construction and, therefore, adopt the construction of “channel”
`as set forth above for this Final Written Decision.
`Petitioner also agrees with our preliminarily constructions for the
`terms “packet” and “switch fabric.” Pet. Reply 1–15. Patent Owner, on the
`other hand, disputes the constructions for both of these claim terms. PO
`Resp. 16–36. We discuss each of these terms in turn below. No other claim
`terms need to be construed expressly for purposes of this Final Written
`Decision because we need only construe terms “that are in controversy, and
`only to the extent necessary to resolve the controversy.” Nidec Motor Corp.
`v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017 (Fed. Cir.
`2017) (quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795,
`803 (Fed. Cir. 1999)).
`
`11
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`
`A. “Packet”
`The main claim construction dispute between the parties with respect
`to the term “packet” centers on whether a “packet” must necessarily include
`control information. Patent Owner asserts that the term “packet,” or
`“packet[] containing data” as recited in claims 1 and 24, should be construed
`to mean “a formatted transmission unit including at least data and control
`information.”3 PO Resp. 24. Petitioner argues that the term “packet” is not
`so limited and asserts that the term, instead, should be construed to mean “a
`basic unit of transport over a channel,” as defined in the ’442 patent. Pet. 13
`(citing Ex. 1001, col. 6, ll. 52–55); Pet. Reply 9–10. For the reasons
`explained below, we agree with Petitioner’s proposed construction and
`conclude that the term “packet” is not limited as Patent Owner contends.
`Because the challenged independent claims, i.e., claims 1 and 24, expressly
`recite “packets containing data,” we need not address the issue of whether a
`“packet” must necessarily include data to decide the patentability of the
`challenged claims based on the asserted prior art. See Nidec Motor, 868
`
`
`3 We note that Patent Owner in its Patent Owner Response proposes an
`express construction of the phrase “packet containing data” (PO Resp. 24,
`25, 36), although its Preliminary Response, the Petition, and our Decision on
`Institution discussed the construction of the term “packet” (see Prelim. Resp.
`17; Pet. 13–14; Dec. on Inst. 12–17). Patent Owner, however, does not
`explain the significance of construing the phrase “packet containing data” as
`opposed to interpreting the term “packet.” Indeed, Patent Owner appears to
`argue the same meaning for both “packet” and “packet containing data” as
`including “at least data and control information.” PO Resp. 24–25; Prelim.
`Resp. 17–18. Hence, we understand Patent Owner’s argument to be an
`argument for construction of the term “packet” as including both data and
`control information. See PO Resp. 24–25.
`12
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`F.3d at 1017. Therefore, our discussion below focuses on whether the
`claimed “packet” must necessarily include control information.
`
`1. Claim Language
`We begin our claim construction analysis by considering the language
`of the claims themselves. Phillips v. AWH Corp., 415 F.3d 1303, 1314 (Fed.
`Cir. 2005) (en banc). As noted above, claim 1 recites that “a switch fabric”
`is configured to “switch packets,” and “channels” are configured to “transfer
`the packets.” Ex. 1001, col. 36, ll. 28, 30. In addition, claims 1 and 24
`recite “exchang[ing] packets . . . over the channels” between microprocessor
`interfaces and switch interfaces, as well as between switch interfaces and
`memory interfaces. Id. at col. 36, ll. 35–38, 40–43, col. 38, ll. 28–30, 33–34.
`Claims 1 and 24 also recite exchanging packets with or through the switch
`fabric. Id. at col. 36, ll. 31–32, col. 38, ll. 31–32. Thus, the plain language
`of the claims indicate that the claimed “packet” is a packet transferred over
`the channels between the interfaces and through the switch fabric.
`Next, we note that the term “control information” is not recited in any
`of the challenged claims. Nor do the claims expressly recite including
`control information in the packets. The only claims of the ’442 patent that
`recite “control information” are claims 39 and 40, which recite “said first
`and second channel interfaces exchange flow control information” and “said
`flow control information comprises a command to cease sending packets
`containing data,” respectively. Id. at col. 39, l. 53–col. 40, l. 3 (emphases
`added). Independent claim 35, from which claims 39 and 40 depend, recites
`that “first and second channel interfaces transport packets across said point-
`to-point connection according to a channel protocol.” Id. at col. 39, ll. 29–
`
`13
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`31 (emphasis added). Claims 35, 39 and 40 are not at issue in this
`proceeding. Nonetheless, transmission of “control information” over a
`channel expressly recited in these dependent claims indicates that, had the
`patentee intended to limit the “packets” recited in claims 1 and 24, or any
`other challenged claims, to require “control information,” it could have done
`so by explicitly modifying the disputed term with “control information,” but
`did not.
`Therefore, to show the term “packet” is limiting, Patent Owner must
`demonstrate “a clear indication in the intrinsic record that the patentee
`intended the claims to be so limited.” Liebel–Flarsheim Co. v. Medrad, Inc.,
`358 F.3d 898, 913 (Fed. Cir. 2004).
`
`2. Written Description
`Turning to the written description, Petitioner asserts that the term
`“packet” is not limited as Patent Owner contends because the Specification
`provides an express definition of the term. Pet. 13–14; Pet. Reply 9–11.
`Petitioner relies upon the following sentence in the ’442 patent (Pet. 13) in
`support of its proposed construction of the term “packet”: “A ‘packet’ is the
`basic unit of transport over the Channel” (Ex. 1001, col. 6, l. 53). In our
`Decision on Institution, we preliminarily determined that this sentence (the
`“packet sentence”) indicates that the patentee was acting as a lexicographer
`and defining the term “packet.” Dec. on Inst. 13.
`When “express definitional language” is found in a patent, “[the]
`definition set forth in the specification governs the meaning of the claims.”
`Sinorgchem Co., Shandong v. Int’l Trade Comm’n, 511 F.3d 1132, 1138
`(Fed. Cir. 2007); see also Phillips, 415 F.3d at 1321 (“[T]he specification
`
`14
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`acts as a dictionary when it expressly defines terms used in the claims . . . .”
`(internal quotation marks omitted)). As discussed in our Decision on
`Institution, the form of the “packet sentence” is definitional in that it uses the
`word “packet” set off by quotation marks followed by a definitional
`description: “is the basic unit of transport over the Channel.” Ex. 1001,
`col. 6, l. 53 (emphasis added). See Sinorgchem, 511 F.3d at 1136 (A term
`set off by quotation marks is often “a strong indication that what follows is a
`definition;” the use of the word “is” in the specification may “signify that a
`patentee is serving as its own lexicographer.” (citations omitted)).
`As discussed above, the plain language of the claims indicates that the
`“packet” recited in the claims is a packet transferred over the channels
`between the interfaces. Hence, the “packet sentence”—i.e., “[a] ‘packet’ is
`the basic unit of transport over the Channel” (Ex. 1001, col. 6, l. 53)—
`provides a definition for a “packet” recited in the claims, i.e., a packet
`transferred over the channels.
`Further, the “packet sentence” appears in the section of the
`Specification titled “Channel Overview and Terminology.” Ex. 1001, col. 6,
`ll. 38, 53 (emphasis added). In our Decision on Institution, we preliminarily
`determined that this section provides an express definition of the term
`“channel” as follows: “The Channel of the present invention is a general-
`purpose, high-speed, point-to-point, full-duplex, bi-directional interconnect
`bus suitable for use in a broad range of applications including computer
`memory, I/O, CPU, switching/routing, or any other application where high
`bandwidth and low latency is required.” Id. at col. 6, ll. 40–45; Dec. on Inst.
`17–19. As discussed above, Patent Owner agrees, and Petitioner does not
`
`15
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`dispute, that this sentence (the “channel definition sentence”) provides a
`definition of the term “channel.” PO Resp. 36–41; Pet. Reply 1–15.
`Similarly, the “packet sentence” provides a definition of a “packet”
`transferred over a channel as part of the “terminology” for describing the
`structure and operation of the channels in the “Channel Overview and
`Technology” section.
`In addition, we note that the “channel definition sentence” is followed
`by a description of implementation details and preferred embodiments of
`using CIBs (Channel Interface Blocks) to provide a “communication path (a
`Channel)” between CIBs. Ex. 1001, col. 6, ll. 45–52. Similarly, the “packet
`sentence” is followed by a detailed description of exemplary embodiments
`of packets exchanged between CIBs. Id. at col. 6, ll. 53–66. The “packet
`sentence” does not mention any particular embodiment and is broader than
`other descriptions found in the Specification regarding packets transferred
`over a channel. This suggests that the “packet sentence,” which is not
`limited to a particular embodiment, provides a definition that applies to the
`claimed invention in general. That broad definition is consistent with other
`descriptions of the packets transferred over the channels in the Specification.
`For example, in one exemplary embodiment, a packet is an 80-bit frame
`exchanged between CIBs over a channel, i.e., a unit of transport over a
`channel. Id. at col. 6, ll. 54–63.
`Based on the foregoing, we determine that the “packet sentence” of
`the ’442 patent provides an express definition for the term “packet” because
`the form and the substance of the sentence, the context in which the sentence
`appears, and the related disclosures all indicate that the patentee intended to
`
`16
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`define the term in the ’442 patent, and defined it “clearly, deliberately, and
`precisely” in the “packet sentence.” See Sinorgchem, 511 F.3d at 1136.
`Therefore, in this case, the ’442 patent provides an express definition for the
`term “packet” in the “packet sentence” of the Specification.
`Patent Owner contends that the “packet sentence” does not provide an
`express definition of the term “packet,” and argues that the Specification,
`instead, supports its proposed limiting construction of the term. PO Resp.
`26–34. First, Patent Owner argues that the “packet sentence” does not
`define the term “packet” because “the particular connotation for the term
`packet must be determined from the context in which it is used” (id. at 29,
`31 (quoting Ex. 1001, col. 7, ll. 17–19)), and “the specification clarifies that
`‘packet’ is limited to the ‘context of the core functions’” (id. at 29 (citing
`Ex. 1001, col. 7, ll. 14–15) (emphases added)).
`We are not persuaded by Patent Owner’s argument. The sentence
`cited by Patent Owner actually states that “[i]n the context of the core
`functions, the term packet is used to refer to just the core-to-core data.”
`Ex. 1001, col. 7, ll. 14–15. Hence, the cited sentence describes the meaning
`of the term “packet” in the context of the core functions, as used in the ’442
`patent, but does not “clarify” or describe that the term “packet” is generally
`“limited” to the context of the core functions.
`On the contrary, as discussed above, the Specification also describes
`“packets” transferred over the channels or exchanged between CIBs. Id. at
`col. 6, ll. 50–66. As also discussed above, the plain language of the claims
`indicates that the claimed “packet” is a packet transferred over a channel
`between the interfaces and through the switch fabric. Thus, the issue at hand
`
`17
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`is whether the Specification defines “packets” as recited in the claims, i.e.,
`the packets transferred over the channels. The fact that the Specification
`also describes “packets” in other contexts, such as in the context of core
`functions, has limited relevance to this question. As discussed above, the
`“packet sentence”—i.e., “[a] ‘packet’ is the basic unit of transport over the
`Channel” (Ex. 1001, col. 6, l. 53 (emphasis added))—directly addresses
`“packets” as recited in the claims (i.e., “packets” transferred over the
`channels), and provides a clear, deliberate, and precise definition for the
`term.
`
`Next, Patent Owner argues that the “packet sentence” does not define
`the term “packet,” but, rather, conveys information about “the Channel.” PO
`Resp. 27–28. Similarly, Patent Owner argues that the “packet sentence”
`should be understood as describing “the Channel,” rather than defining the
`term “packet,” because the sentence appears in the section of the
`Specification titled “Channel Overview and Technology.” Id. at 33.
`We are not persuaded because Patent Owner’s argument is contrary to
`the plain language of the sentence, which describes what a packet is, not
`what a channel is. Furthermore, as discussed above, the “packet sentence”
`defines a packet transferred over a channel. Hence, contrary to Patent
`Owner’s contention, the title of the section, “Channel Overview and
`Technology,” indicates that the sentence defining a “packet” transferred over
`a channel is provided in the section as part of the “terminology” for
`describing the structure and operation of the channels.
`Patent Owner further asserts that the “packet sentence” does not
`provide a lexicographic definition because the Specification does not show a
`
`18
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`“clear intent” to depart from the “dictionary definition (the ordinary
`meaning).” Id. at 28.
`We are not persuaded by Patent Owner’s argument because, as
`discussed separately below, we are not persuaded that the dictionaries or
`other extrinsic evidence cited by Patent Owner establish the ordinary and
`customary meaning of the term “packet,” as used in the challenged claims,
`given the explicit lexicographic definition in the Specification.
`We have reviewed carefully the rest of Patent Owner’s arguments
`against the express definition provided in the “packet sentence” and find
`them unpersuasive. For example, Patent Owner argues that the “packet
`sentence” does not define the term “packet” because the Specification does
`not capitalize the term, unlike the “channel definition sentence,” which
`capitalizes the term “Channel.” Id. at 31–32. Patent Owner’s argument is
`unpersuasive because Patent Owner does not cite any authority in support of
`its proposition that a patentee must capitalize a term in a specification to
`define it. Moreover, as explained above, the context in which the “packet
`sentence” appears indicates that the patentee intended to define the term.
`Patent Owner also asserts that the disclosure in the Specification
`supports its proposed construction requiring a “packet” to necessarily
`include control information. Id. at 30 (citing Ex. 1001, col. 6, ll. 54–63,
`col. 12, ll. 35–43, col. 14, ll. 1–12). Patent Owner’s argument is
`unpersuasive because the passages relied upon by Patent Owner describe
`preferred embodiments where packets comprising an 80-bit frame (including
`payload data and control information) are exchanged between CIBs. See
`Ex. 1001, col. 6, ll. 54–55 (“In a preferred embodiment, conceptually a
`
`19
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`packet is a single 80-bit frame (information unit) exchanged between
`CIBs.”) (emphasis added); col. 12, ll. 35–43 (describing the details of the
`signals for the “Core Logic to CIB” interface); col. 14, ll. 1–12 (describing
`the details of the signals for the “CIB to Core Logic” interface).
`As discussed above, the term “control information” is not recited in
`independent claims 1 and 24. Nor do the claims expressly recite including
`control information in the packets. In general, a particular embodiment
`appearing in the written description is not incorporated into a claim if the
`claim language is broader than the embodiment. Van Geuns, 988 F.2d at
`1184. Further, “[e]ven when the specification describes only a single
`embodiment, the claims of the patent will not be read restrictively unless the
`patentee has demonstrated a clear intention to limit the claim scope using
`‘words or expressions of manifest exclusion or restriction.’” In re Am. Acad.
`of Sci. Tech Ctr., 367 F.3d 1359, 1369 (Fed. Cir. 2004) (quoting Liebel–
`Flarsheim Co. v. Medrad, Inc., 358 F.3d 898, 906 (Fed. Cir. 2004)). In view
`of the word “preferred embodiment” used in the passages discussed above,
`we are not persuaded that the cited passages limit the challenged claims to
`require a “packet” to necessarily include control information. Hence, based
`on the complete record, we determine that the passages of the ’442 patent
`cited by Patent Owner do not override the express definition of a “packet”
`provided in the Specification.
`
`3. Extrinsic Evidence
`Relying on the dictionaries submitted by the parties and testimony
`from Patent Owner’s declarant, Dr. Alpert, Patent Owner argues that the
`ordinary meaning of the term “packet” in the context of packet switching
`
`20
`
`

`

`IPR2016-01106
`Patent 6,516,442 B1
`
`
`was well-know