Ulllted States Patent [19]
`Kim et al.
`
`US005808948A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,808,948
`Sep. 15, 1998
`
`[54] SEMICONDUCTOR MEMORY DEVICE
`
`[56]
`
`References Cited
`
`[75] Inventors: Chul-s00 Kim, SuWon; H0-che0l Lee,
`$90111, both of Rep- Of Korea
`
`[73] Asslgnee: givnszgnlgzflegrgélrcei’ Co" Ltd"
`’
`p'
`
`[21] Appl. No.: 769,615
`
`[22]
`[30]
`
`Dec‘ 18’ 1996
`Flled:
`Foreign Application Priority Data
`
`Rep. Of Korea .................... .. 95/69724
`D60. 30, 1995
`[51]
`Int. Cl.6 ..................................................... .. G11C 7/00
`
`[52] US. Cl. .................... .. 365/201; 365/200; 365/230.03
`[58] Field of Search ................................... .. 365/200, 201,
`365/23003
`
`HS‘ PATENT DOCUMENTS
`5,576,999 11/1996 Kim et a1. ............................. .. 365/200
`5,619,460
`4/1997 Kirihata et a1. ....................... .. 365/251
`Primary Examiner—A. Zarabian
`Attorney, Agent, or Firm—Marger, Johnson, McCollom &
`StoloWitZ RC.
`[57]
`
`ABSTRACT
`
`There is provided a semiconductor memory device Which
`does not require an additional input pad to apply a signal for
`discriminating betWeen a normal cell and a redundant cell.
`The Semieodnuetor memory device has(c1ai[n
`Therefore,
`the normal Cell array or the redundant Cell array is Sequen'
`tially selected and tested by using the same input pad to
`Which the bank Select bit is input, Without an additional pad‘
`
`11 Claims, 4 Drawing Sheets
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`MEANS
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`WCBRSWET
`
`Apple – Ex. 1019
`Apple Inc., Petitioner
`1
`
`

`
`U.S. Patent
`
`Sep. 15, 1998
`
`Sheet 1 of4
`
`5,808,948
`
`FIG.
`
`1
`
`(PRIOR ART)
`
`RA13B
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`2
`
`

`
`U.S. Patent
`
`Sep. 15, 1998
`
`Sheet 2 of4
`
`5,808,948
`
`FIG. 2
`
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`

`
`U.S. Patent
`
`Sep. 15, 1998
`
`Sheet 3 of4
`
`5,808,948
`
`NORMAL CELL
`OF FIRST BANK
`(A155)
`
`ROW
`REDUNDANT
`CELL
`(A15)
`
`ROW
`REDUNDANT
`CELL
`(A138)
`
`NORMAL CELL
`OF SECOND
`BANK \
`(A15)
`56
`
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`
`COLUMN
`REDUNDANT
`CELL(A1Z>)
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`
`4
`
`

`
`U.S. Patent
`
`Sep. 15,1998
`
`Sheet 4 of4
`
`5,808,948
`
`FIG. 5
`
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`
`5
`
`

`
`5,808,948
`
`1
`SEMICONDUCTOR MEMORY DEVICE
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to a semiconductor memory
`device, and more particularly, to a semiconductor memory
`device that does not require an additional pad for discrimi
`nating betWeen normal cells and redundant cells during
`testing.
`Generally, a memory cell array. in a memory device
`comprises a normal cell array and a redundant cell array. In
`testing a memory device according to the prior art, only the
`normal cell is initially tested. If a repairable failure is found,
`the cell is repaired. The cell is then retested, and memory
`device assembled if it passes the test.
`HoWever, there are some cases Where a redundant cell is
`susceptible to a failure despite a repair. Thus, efforts have
`recently been made to reduce the possibility of a post-repair
`failure by repairing only redundant cells that pass initial
`tests.
`FIG. 1 is a schematic block diagram of a conventional
`memory device for enabling redundant cell testing. The
`conventional memory device has a memory cell array 24,
`address input pads 10 (PAO—PA13), a roW address buffer 12,
`roW decoding means 14, redundancy decoding means 16, a
`column address buffer 18, column decoding means 20, and
`redundancy column decoding means 22.
`The memory cell array 24 is divided into a normal cell
`array de?ned by RA13B and CA13B and a redundant cell
`array de?ned by RA13 and CA 13. Address input pads
`PAO—PA12 are connected to external pins that are applied
`during a package process. Address input pad PA13 is only
`used during testing. The roW address buffer 12 buffers roW
`address signals input via the address input pads PAO—PA13.
`The roW decoding means 14 and the redundancy roW
`decoding means 16 decode the roW addresses. The roW
`decoding means 14 decodes addresses for the normal cell
`array and the redundancy roW decoding means 16 decodes
`addresses for the redundant cell array. The column address
`buffer 18 buffers column addresses on the address input pads
`PAO—PA13. The column decoding means 20 decodes
`addresses for the normal cell array and the redundancy
`column decoding means 22 decodes addresses for the redun
`dant cell array.
`In conventional memory devices, addresses needed for
`normal addressing are applied to the pads PAO—PA12.
`HoWever, to test both the normal and redundant cell arrays,
`an additional signal is required to discriminate betWeen the
`normal cell array and the redundant cell array. The signal is
`applied on pad PA13. That is, to test the normal cell array,
`de?ned by RA13B and CA13B, and the redundant cell array,
`de?ned by RA13 and CA13, a signal is either asserted or
`deasserted on the address input pad PA13. The normal cell
`array is selected When the most signi?cant bit (MSB) of the
`address input on input pad PA13 is logic “0”. If the MSB is
`logic “1”, the redundant cell array is selected.
`When an address is received on the address input pads 10
`(PAO—PA13), the roW address buffer 12 and the column
`address buffer 18 buffer the address. If the address selects the
`normal cell, that is, if the MSB of the address is logic “0”,
`a roW predecoder 14a and a column predecoder 20a are
`activated. The roW decoder 14a and column decoder 20b
`receive and decode the outputs of the roW predecoder 14a
`and the column predecoder 20a selecting the normal cell
`de?ned by RAI3B and CA13B.
`If the signal applied to the address input pad PA13 is logic
`“1”, that is, if the redundant cell is to be tested, a redundancy
`
`2
`roW fuse box 16a and a redundancy column fuse box 22a are
`activated. The redundancy roW decoder 16b and the redun
`dancy column decoder 22b receive and decode the outputs
`of the redundancy roW fuse box 16a and the redundancy
`column fuse box 22b, respectively, selecting the redundant
`cell, de?ned by RA13 and CA13.
`Thus, the semiconductor memory device shoWn in FIG. 1
`needs an additional address input pad for applying a signal
`that sWitches betWeen normal cells and redundant cells in a
`test mode, in addition to the address input pads used in the
`normal operating mode. A probe card used for testing the
`semiconductor device must include an additional input pin
`that corresponds to the additional address input pad PA 13.
`
`15
`
`SUMMARY OF THE INVENTION
`
`An object of the invention is to provide a semiconductor
`memory device that does not require an additional address
`pad for accessing both normal cells and redundant cells
`during testing.
`A semiconductor memory device includes a plurality of
`banks each having normal and redundant cell arrays. One of
`the banks is selected in response to an external input bank
`select bit. A test mode determining means receives an
`external address and generates a test mode signal in response
`to external control signals. A redundant cell test controller
`selects one of the normal and redundant cell arrays of the
`selected bank in response to the bank select bit and the test
`mode signal.
`A ?rst control signal comprises an external roW address
`strobe signal. A second control signal is a logical combina
`tion of an external chip select signal, column address strobe
`signal, and Write enable signal.
`The test mode determining means includes a ?rst trans
`ferring means for transferring the address in response to the
`?rst control signal. A?rst latch stores the address transferred
`from the ?rst transferring means. A ?rst inverter inverts the
`output of the ?rst latch. A second transferring means trans
`fers an output signal from the ?rst inverter in response to the
`second control signal. A second latch stores a signal trans
`ferred by the second transferring means. A second inverter
`inverts an output signal from the second latch and outputs
`the test mode signal. A ?rst precharge circuit precharges an
`input of the ?rst latch. Asecond precharge circuit precharges
`an input of the second latch.
`The test mode determining means and redundant cell test
`controlling means reduce the number of address pads
`required for testing redundant memory cells.
`The foregoing and other objects, features and advantages
`of the invention Will become more readily apparent from the
`folloWing detailed description of a preferred embodiment of
`the invention Which proceeds With reference to the accom
`panying draWings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram of a conventional memory
`device for enabling redundant cell testing.
`FIG. 2 is a block diagram of a memory device that enables
`redundant cell testing according to the present invention.
`FIG. 3 is a block diagram shoWing memory cell address
`ing for the memory device shoWn in FIG. 2.
`FIG. 4 is a detailed circuit diagram of a test mode
`determining means for the memory device shoWn FIG. 2.
`FIG. 5 is a timing diagram for testing a memory cell array
`for the semiconductor memory device shoWn in FIG. 2.
`
`25
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`

`
`3
`DETAILED DESCRIPTION OF THE
`INVENTION
`Referring to FIG. 2, a semiconductor memory device
`according to the present invention includes a memory cell
`array 44 having a normal cell array de?ned by RA13B and
`CA13B and a redundant cell array de?ned by RA13 and
`CA13. Address input pads 30 (PAO—PA13) receive exter
`nally applied addresses. A roW address buffer 32 buffers a
`roW address for the address input on the address input pads
`30 (PAO—PA13). Either roW decoding means 34 or redun
`dancy roW decoding means 36 are activated in response to
`a redundancy control signal RED. The roW decoding means
`34 address roW lines for the normal cell array of the RA13B
`and CA13B areas. The redundant roW decoding means 36
`address the roW lines for the redundant cell array of the
`RA13 and CA13 areas.
`A column address buffer 38 buffers a column address
`among the addresses input on the address input pads 30
`(PAO—PA13). Column decoding means 40 address column
`lines of the normal cell array RA13B and CA13B and the
`redundancy column decoding means 42 address the column
`lines of the redundant cell array RA13 and CA13. A test
`mode determining means 46 receives an address or a com
`bination of addresses and generates a test mode signal PRCT
`indicating the initiation of a test mode. The PRCT signal is
`generated in response to control signals PRP1D,
`WCBRSET, and PVCCH. A redundant cell test controlling
`means 48 generates the redundancy control signal RED in
`response to a bank select bit B of the address and the test
`mode signal PRCT.
`The memory cell array 44 has a plurality of banks, one of
`Which is selected in response to the bank select bit B of the
`address. The roW decoding means 34 includes a roW prede
`coder 34a for predecoding a roW address from the roW
`address buffer 32. A roW decoder 34b is activated in
`response to the redundancy control signal RED, redecodes
`an output signal of the roW predecoder 34a, and addresses a
`roW of the normal cell array RA13B and CA13B. The
`redundancy roW decoding means 36 includes a roW fuse boX
`36a Which is activated When the roW address is selected for
`the redundant cell. A redundancy roW decoder 36b is acti
`vated in response to the redundancy control signal RED,
`redecodes an output signal of the redundancy roW fuse boX
`36a, and addresses a roW line of the redundant cell array of
`RA13 and CA13.
`The column decoding means 40 includes a column pre
`decoder 40a that predecodes a column address input from
`the column address buffer 38. A column decoder 40b is
`activated in response to the redundancy control signal RED,
`redecodes an output signal from the column predecoder 40a,
`and addresses a column line of the normal cell array of
`RA13B and CA13B. The redundancy column decoding
`means 42 includes a redundancy column fuse boX 42a Which
`is activated When the column address selects the redundant
`cell. A redundancy column decoder 42b is activated in
`response to the redundancy control signal RED, re-decoding
`an output signal of the redundancy column fuse boX 42a, and
`addressing a column line of the redundant cells RA13 and
`CA13.
`The ?rst control signal PRP1D is a pulse signal Which is
`enabled by an external input roW address strobe signalRAS,
`the second control signal WCBRSET is a combination signal
`of a chip select signal“, a column address strobe signal CAS,
`and a Write enable signal WE. The third control signal
`PVCCH is a precharge signal.
`FIG. 3 is a block diagram that shoWs memory cells for the
`semiconductor memory device in FIG.2. The memory cells
`
`10
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`5,808,948
`
`4
`44 of FIG. 2 have tWo banks. The MSB of the address input
`from the input pad A13 is used as a bank select bit. Anormal
`cell 50 for a ?rst bank 50 in the memory cell array is selected
`When the MSB of the address is at a “loW” level (A13B).
`RoW and column redundant cells 52 and 54 for the ?rst bank
`are selected When the MSB of the address is at a “high” level
`(A13).
`A normal cell 56 for a second bank is selected When the
`MSB of the address is at a “high” level (A13). RoW and
`column redundant cells 60 and 58 for the second bank are
`selected When the MSB of the address is at a “loW” level
`(A13B).
`FIG. 4 is a detailed circuit diagram of the test mode
`determining means for the semiconductor memory device of
`the present invention shoWn in FIG. 2. A transfer means
`TM1 transfers an address or address combination signal Ai
`in response to the ?rst control signal PRP1D. A latch 62
`stores a signal transferred by the transferring means TM1.
`Inverting means I4 inverts an output signal of the latch 62.
`Transfer means TM2 transfers an output signal of the
`inverting means 14 in response to the second control signal
`WCBRSET. A latch 64 stores the signal transferred by the
`transferring means TM2. Inverting means 17 inverts an
`output signal of the latch 64 and outputs a test mode signal
`PRCT that sets a test mode.
`Precharge means MP1 precharges an input terminal of the
`latch 62 in response to the third control signal PVCCH.
`Precharge means MP2 precharges an input terminal of the
`latch 64. The transfer means TM1 comprises a transmission
`gate and is activated When control signal PRP1D is logic
`“high” . The transferring means TM2 comprises a transmis
`sion gate activated When control signal WCBRSET is logic
`“high”. The latch 62 comprises tWo inverters I2 and I3 and
`the latch 64 comprises tWo inverters I5 and I6. The inverting
`means I4 and I7 each comprise inverters. The precharge
`means MP1 and MP2 each comprise PMOS transistors.
`FIG. 5 is a timing diagram shoWing hoW the memory cell
`array of the semiconductor memory device shoWn in FIG. 2
`is tested. The chip selecting signal“, the roW address strobe
`signalRAS, the column address strobe signal CA5, the Write
`enable signalWE, and the clock signal CLK are all input at
`“loW” levels to the memory device of FIG. 2. In a mode
`register set (MRS) cycle, the ?rst and second control signals
`PRP1D and WCBRSET of FIG. 4 are driven “high”. The test
`mode signal PRCT is activated by an address or address
`combination Ai (FIG. 4). If a bank select bit B, Which is the
`MSB (A13) of an address input during the MRS cycle, is
`high, the ?rst bank of FIG. 3 is selected. When the bank
`select bit B is “loW”, the second bank of FIG. 3 is selected.
`After the MRS cycle, When the chip select signalCS and the
`roW address strobe signal RAS are driven to loW levels, and
`the column address strobe signalCAS and the Write enable
`signalWE are driven to “high” levels, an active cycle is set.
`When the ?rst bank is selected during the MRS cycle and
`the bank select bit B input during the active cycle is “loW”,
`the roW and column decoding means 34 and 40 of FIG. 2 are
`activated by the redundancy control signal RED. Thus, the
`normal cell 50 of the ?rst bank is selected. When the ?rst
`bank is selected during the MRS cycle and the bank select
`bit B input during the active cycle is “high”, the redundancy
`roW and redundancy column decoding means 36 and 42 are
`activated by the redundant control signal RED. Thus, the
`redundant cells 52 and 54 of the ?rst bank are selected.
`When the second bank is selected during the MRS cycle
`and the bank select bit B input during the active cycle is
`“loW”, the redundancy roW and redundancy column decod
`
`7
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`

`
`5,808,948
`
`5
`ing means 36 and 42 are activated. Thus, the redundant cells
`58 and 60 of the second bank are selected. When the second
`bank is selected during the MRS cycle and the bank select
`bit B input during the active cycle is “high”, the roW and
`column decoding means 34 and 40 are activated by the
`redundancy control signal RED. Thus, the normal cell 56 of
`the second bank is selected.
`Therefore, the semiconductor memory device of the
`present invention has an advantage in that the normal or
`redundant cells are sequentially selected by using the same
`input pad A13 used for bank selection.
`It should be understood that the present invention is not
`limited to the particular embodiment disclosed herein as the
`best mode contemplated for carrying out the present
`invention, but rather that the present invention is not limited
`to the speci?c embodiments described in this speci?cation
`except as de?ned in the appended claims.
`What is claimed is:
`1. A semiconductor memory device comprising:
`a ?rst and second memory bank each having a normal cell
`array and an associated redundant cell array;
`a decoder circuit addressing one of the ?rst and second
`memory banks and the redundant cell array for the
`nonaddressed one of the memory banks in response to
`a bank select signal generated from an external address;
`and
`a test mode determining means coupled to the decoder
`circuit for generating a test mode signal in response to
`the external address and one or more memory device
`control signals,
`the test mode signal in combination With the bank select
`signal activating one of the normal and redundant cell
`arrays for the addressed memory bank among the
`plurality of banks alloWing testing of both the normal
`cell array and redundant cell array using the same
`external address.
`2. A semiconductor memory device as claimed in claim 1
`Wherein the test mode determining means includes latching
`circuitry that selectively sWitches back and forth betWeen
`activating the normal and redundant cell array for the
`addressed memory bank.
`3. A semiconductor memory device as claimed in claim 2
`Wherein the decoder circuitry includes the folloWing:
`a normal predecoder receiving the external address;
`a normal decoder receiving an output of the normal
`predecoder and the test node signal for selectively
`activating a memory cell in the normal cell array;
`a redundancy roW fuse box receiving the external address;
`and
`a redundancy roW decoder receiving an output of the
`redundancy roW fuse box and the test signal for selec
`tively activating a memory cell in the redundancy cell
`array.
`4. A semiconductor memory device as claimed in claim 1
`Wherein the test mode determining means comprises:
`a ?rst transferring circuit for transferring the address in
`response to a ?rst one of the control signals;
`a ?rst latch for storing a signal transferred by the ?rst
`transferring circuit;
`a ?rst inverting circuit for inverting an output signal of the
`?rst latch;
`a second transferring circuit transferring an output signal
`of the ?rst inverting circuit in response to a second one
`of the control signals;
`a second latch for storing the signal transferred by the
`second transferring circuit;
`
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`a second inverting circuit for inverting an output signal of
`the second latch and outputting the test mode signal;
`a ?rst precharge circuit for precharging an input terminal
`of the ?rst latch; and
`a second precharge circuit for precharging an input ter
`minal of the second latch.
`5. A semiconductor memory device having a plurality of
`banks each including normal and redundant cell arrays, the
`semiconductor memory device comprising:
`a roW decoder for addressing roWs in the normal cell
`arrays and a redundant roW decoder for addressing
`roWs in the redundant cell arrays , one of the roW
`decoder and redundant roW decoder activated in
`response to a redundancy control signal in combination
`With a bank select signal generated from an external
`address;
`a column decoder for addressing columns in the normal
`cell arrays and a redundant column decoder for
`addressing columns in the redundant cell arrays, one of
`the column decoder and redundant column decoder
`activated in response to the redundancy control signal
`in combination With the bank select signal;
`a test mode circuit generating a test mode signal in
`response to memory device control signals and the
`external address signals, the test mode signal used in
`combination With the bank select signals for and
`generating the redundancy control signal so that the same
`external address is used for addressing one of the
`plurality of banks and also testing both the normal cell
`arrays and redundant cell arrays in the addressed bank.
`6. A semiconductor memory device as claimed in claim 5
`Wherein the redundancy control signal is selectively latched
`on and off by the test mode circuit thereby selectively
`sWitching back and forth betWeen activating the normal and
`redundant cell arrays using the same external address.
`7. A semiconductor memory device as claimed in claim 6
`Wherein the redundancy control signal is selectively latched
`on and off according to a chip select signal, a column address
`strobe signal, and a Write enable signal.
`8. A semiconductor memory device as claimed in claim 5
`Wherein the test mode circuit comprises:
`a sWitching circuit for selectively transferring the address
`in response to the ?rst control signal; and
`a latch for storing a signal transferred by the sWitching
`circuit.
`9. The semiconductor memory device according to claim
`5 Wherein the roW decoder, redundant roW decoder, column
`decoder and redundant column decoder in combination
`select the normal cell array for a ?rst one of the memory
`banks and select the redundant cell array for a second one of
`the memory banks When the bank select signal is asserted
`and select the redundant cell array for the ?rst one of the
`memory banks and select the normal cell array for the
`second one of the memory banks When the bank select signal
`is deasserted.
`10. A method for activating cells in a semiconductor
`memory device With multiple banks each having a normal
`cell array and a redundant cell array, comprising:
`initiating a mode register set cycle by asserting a ?rst
`combination of control signals in the memory device;
`selecting one of the multiple banks during the mode
`register set cycle according to a bank select signal
`generated from an external address;
`setting the selected one of the banks and starting active
`cycle by asserting a second combination of the control
`signals;
`
`8
`
`

`
`5,808,948
`
`7
`generating a test mode signal during the active cycle
`according to the bank select signal and the memory
`control signals; and
`selectively sWitching betWeen activating one of the nor
`mal cell array and redundant cell array for the selected 5
`bank during the active cycle by asserting and deassert
`ing the test mode signal there using the same eXternal
`address for both selecting one of the multiple banks and
`selectively enabling testing of the normal cell array and
`the redundant cell array for the selected one of the 10
`multiple banks.
`
`8
`11. A method according to claim 10 including selecting
`the normal cell array for a ?rst one of the memory banks and
`selecting the redundant cell array for a second one of the
`memory banks When the bank select signal is asserted and
`selecting the redundant cell array for the ?rst one of the
`memory banks and selecting the normal cell array for the
`second one of the memory banks When the bank select signal
`is deasserted.
`
`9
`
`

`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`
`PATENT NO.
`: 5,808,948
`: September 15, 1998
`DATED
`INVENTOR(S) : Kim et al.
`
`Page 1 of 1
`
`It is certified that error appears in the above-identi?ed patent and that said Letters Patent is
`hereby corrected as shown below:
`
`Column 4
`Line 21, “14” should read -- I4 --;
`Line 23, “17” should read -- I7 --;
`
`Column 6
`Lines 26-27, “for and 1t generating” should read -- for generating --;
`
`Column 7
`Line 7, “there” should read -- thereby
`
`Signed and Sealed this
`
`Eleventh Day of February, 2003
`
`JAMES E. ROGAN
`Director ofthe United States Patent and Trademark O?‘i'ce
`
`10