Trials@uspto.gov
`571.272.7822
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`Paper 6
`Filed: April 11, 2017
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`PROMOS TECHNOLOGIES, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-00038
`Patent 6,195,302 B1
`____________
`
`
`
`Before JAMESON LEE, KEVIN F. TURNER, and
`JOHN A. HUDALLA, Administrative Patent Judges.
`
`TURNER, Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`
`
`571.272.7822
`
`
`
`
`
`Paper 6
`Filed: April 11, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`PROMOS TECHNOLOGIES, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-00038
`Patent 6,195,302 B1
`____________
`
`
`
`Before JAMESON LEE, KEVIN F. TURNER, and
`JOHN A. HUDALLA, Administrative Patent Judges.
`
`TURNER, Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`
`
`
`IPR2017-00038
`Patent 6,195,302 B1
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`
`I. INTRODUCTION
`
`A. Background
`Petitioner, Samsung Electronics Co., Ltd. (“Petitioner”), filed a
`Petition (Paper 2, “Pet.”) requesting an inter partes review of claims 1–6 and
`10–12 of U.S. Patent No. 6,195,302 B1 (Ex. 1001, “the ’302 Patent”).
`Patent Owner, ProMOS Technologies, Inc. (“Patent Owner”), did not file a
`Preliminary Response.
`To institute an inter partes review, we must determine that the
`information presented in the Petition shows “that there is a reasonable
`likelihood that the petitioner would prevail with respect to at least 1 of the
`claims challenged in the petition.” 35 U.S.C. § 314(a). Having considered
`the Petition, we determine that Petitioner has demonstrated a reasonable
`likelihood that it would prevail in showing the unpatentability of each of
`claims 1–6 and 10–12 of the ’302 Patent.
`Related Matters
`B.
`Petitioner and Patent Owner indicate that the ’302 Patent has been
`asserted by Patent Owner in ProMOS Technologies, Inc. v. Samsung
`Electronics Co., Ltd., et al., No. 1:15-cv-898-SLR-SRF (D. Del.). Pet. 1;
`Paper 5, 1. The ’302 Patent is also the subject of another petition, also filed
`by Petitioner, seeking inter partes review of claims 1–6 and 10–18 under
`different grounds of unpatentability, IPR2017-00039, being considered
`concurrently.
`Petitioner and Patent Owner indicate that these patents are related to
`the ’302 patent: U.S. Patent Nos. 5,761,112; 6,849,897; 6,020,259;
`6,088,270; and 6,699,789. Id. Patent Owner identifies these inter partes
`review proceedings for the related patents: IPR2017-00032 (Patent No.
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`IPR2017-00038
`Patent 6,195,302 B1
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`6,849,897); IPR2017-00033 and IPR2017-00035 (Patent No. 6,020,259);
`IPR2017-00036 (Patent No. 6,088,270); IPR2017-00037 (Patent No.
`6,699,789); and IPR2017-00040 (Patent No. 5,761,112). Paper 5, 1.
`
`The ’302 Patent
`C.
`The ’302 patent is directed to a random access memory and the
`operations within a random access memory for reading or refreshing
`memory cells, specifically applied to sense amplifiers. Ex. 1001, 1:8–10.
`The ’302 Patent discloses a memory device with sense amplifiers, as
`illustrated in Figure 1, reproduced below:
`
`Figure 1 illustrates a memory device according to an embodiment of the
`’302 Patent.
`Sense amplifiers 101a–101c are coupled to high voltage line Vcc and
`ground via driver transistors 104 and 106, respectively. Id. at 4:40–5:4.
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`Driver transistors 104, which are PMOS pull-up transistors, and driver
`transistors 106, which are NMOS pull-down transistors, are controlled by
`control signals LPB and LNB, respectively. Id. The ’302 Patent illustrates
`the functionalities of the sense amplifiers with respect to Figure 2,
`reproduced below:
`
`
`
`Figure 2 illustrates a portion of a memory device according to an
`embodiment of the ’302 Patent.
`The ’302 Patent discloses that storage capacitors 201 are selectively
`coupled to bit lines 202 through access switches 203 in response to address
`signals supplied to word lines 204. Id. at 5:5–9. Prior to a read operation, a
`pair of bit lines 202 are “equalized at some voltage between a logic high and
`a logic low signal,” and a word line (WL) signal is activated. Id. at 5:18–21,
`5:35–37. After the WL signal is activated, “the LPB signal is driven to a
`logic low[,] coupling VCCI to sense amp 101 through drive transistor 104
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`[and] [s]imilarly, the LNB signal is driven high to couple sense amp 101 to
`ground or VSS through drive transistor 106.” Id. at 5:38–42. The ’302 Patent
`also provides that “LNB and LPB are generated by a circuit such as that
`shown in FIG. 3 that generates LNB and LBP both as dual slope signals.”
`Id. at 5:45–47. Figure 3 of the ’302 Patent is reproduced below:
`
`
`
`Figure 3 illustrates a timer circuit according to an embodiment of the
`’302 Patent.
`The ’302 Patent discloses that when sensing is to begin, “one of the
`input signals SENR or SENL will go to a logic high,” which causes
`signal 302 to transition to a logic low because of NOR gate 301 and
`inverter 304. Id. at 5:66–6:6. Signal LPB is disclosed as being generated as
`follows:
`[S]hortly after either SENR or SENL goes high, transistor 303 is
`turned on pulling the LPB signal low through resist[o]r 306. . . .
`Resistor 316 controls the rate of change or dv/dt of LNB while
`resistor 306 controls the dv/dt of LPB. After a delay determined
`by delay element 307, transistor 308 will be turned on pulling
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`LPB to ground with a much lower resistance. When transistor
`308 is turned on, LPB will fall to the ground voltage with a high
`dv/dt.
`Id. at 6:8–18.
`Signal LNB is generated in a similar manner (i.e., a first pull-up path
`corresponding to transistor 313 is enabled, and then after a delay, a second
`pull-up path corresponding to transistor 318 is enabled, while the first pull-
`up path is still enabled), id. at 6:33–36, with both signals, LNB and LPB,
`being generated as “dual slope signals.” Id. at 5:45–47.
`
`Claims 1 and 10 of the challenged claims of the ’302 Patent are
`independent and reproduced below:
`1. A memory device comprising:
`a plurality of sense amplifiers distributed about an integrated circuit chip,
`each sense amplifier having a power node for receiving current;
`a low-impedance power supply conductor;
`at least one drive transistor having a first current carrying electrode
`coupled to the power supply conductor, a second current carrying
`electrode coupled to the power nodes of a preselected number of the
`sense amplifiers, and a control electrode;
`a control line coupled to the control electrode;
`a timer unit having an output coupled to the control electrode and
`generating a control signal;
`a first component within the timer unit causing the control signal to
`change from a first logic level towards a second logic level at a first
`rate; and
`a second component within the timer unit causing the control signal to
`change to the second logic level at a second rate, wherein the second
`rate is greater than the first rate such that the first component and the
`second component are concurrently activated to cumulatively affect
`the rate of change to the second logic level.
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`10. A sense amplifier clock driver circuit for an integrated circuit
`memory, the driver circuit providing at least one clock signal for
`controlling the operation of sense amplifier driver transistors and
`comprising:
`a sense control signal node receiving an externally generated sense
`control signal indicating when sensing is to occur;
`a first impedance having a terminal coupled to a selected logic level
`signal;
`a first switch having current carrying electrodes coupled to drive the
`clock signal to a selected logic level through the first impedance, the
`first switch controlled by the sense control signal;
`a delay unit coupled to the sense control signal node and generating a
`delayed sense control signal;
`a second impedance having a terminal coupled to the selected logic level
`signal; and
`a second switch having current carrying electrodes coupled to drive the
`clock signal to the selected logic level through the second impedance,
`the second switch controlled by the delayed sense control signal such
`that the first switch and the second switch are concurrently activated
`after the delayed sense control signal is generated.
`Ex. 1001, 8:11–33, 9:10–34.
`
`Evidence Relied Upon
`D.
`Petitioner relies on the following references:
`
`
`
`Exhibit
`Date
`Reference
`Ex. 1004
`issued Aug. 18, 1992
`U.S. Patent No. 5,140,199
`Seo
`UK Patent No. GB2246005B published Aug. 31, 1994 Ex. 1005
`Min
`Schuster “A 15-ns CMOS 64K
`published Oct. 1986
`Ex. 1007
`RAM,” IEEE J. of Solid-
`State Circuits, Vol. SC-21,
`No. 5, pp.704-12
`
`
`Petitioner also relies on the Declaration of Dr. R. Jacob Baker. Ex. 1002.
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`E. The Asserted Grounds
`Petitioner asserts the following grounds of unpatentability:
`References
`Basis
`Claim(s) Challenged
`Seo and Min
`§ 103(a)
`1–5 and 10–12
`Seo
`§ 102(b)
`10–12
`Seo, Min, and Schuster
`§ 103(a)
`6
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`
`II. ANALYSIS
`Claim Construction
`A.
`In an inter partes review, claim terms in an unexpired patent are
`interpreted according to their broadest reasonable construction in light of the
`specification of the patent in which they appear. See 37 C.F.R. § 42.100(b);
`Cuozzo Speed Techs., LLC v. Lee, 136 S. Ct. 2131, 2142–46 (2016).
`Consistent with that standard, we assign claim terms their ordinary and
`customary meaning, as would be understood by one of ordinary skill in the
`art at the time of the invention, in the context of the entire patent disclosure.
`See In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).
`There are, however, two exceptions: “1) when a patentee sets out a
`definition and acts as his own lexicographer,” and “2) when the patentee
`disavows the full scope of a claim term either in the specification or during
`prosecution.” Thorner v. Sony Comp. Entm’t Am. LLC, 669 F.3d 1362, 1365
`(Fed. Cir. 2012). It is inappropriate to limit a claim to a preferred
`embodiment without a clear intent in the specification to redefine a claim
`term or a clear disavowal of claim scope. See id. Limitations that are not a
`part of the claim should not be imported into the claim. See SuperGuide
`Corp. v. DirecTV Enters., Inc., 358 F.3d 870, 875 (Fed. Cir. 2004).
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`Petitioner asserts that certain claim terms should be interpreted
`according to 35 U.S.C. § 112, sixth paragraph, making specific arguments
`with respect to “timer unit,” “first component,” “second component,” and
`“delay unit.” Pet. 17–25 (citing Williamson v. Citrix Online LLC, 792 F.3d
`1339, 1349 (Fed. Cir. 2015)). Petitioner asserts that “unit” and “component”
`are nonce words that do not connote any structures and that the subject claim
`elements are specified using purely functional language. Id. We do not
`agree.
`Petitioner’s focus on the word “unit” is misplaced. Petitioner has not
`represented, much less explained, that one with ordinary skill in the art
`would not have recognized that “timer” is a recognized term of art and
`would not have recognized what structure is conveyed by “timer.”
`In considering whether a claim term recites sufficient
`structure to avoid application of section 112 ¶ 6, we have not
`required the claim term to denote a specific structure. Instead,
`we have held that it is sufficient if the claim term is used in
`common parlance or by persons of skill in the pertinent art to
`designate structure, even if the term covers a broad class of
`structures and even if the term identifies the structures by their
`function. See Greenberg v. Ethicon Endo-Surgery, Inc., 91
`F.3d 1580, 1583 (Fed. Cir. 1996).
`Lighting World, Inc. v. Birchwood Lighting, Inc. 382 F.3d 1354, 1359–60
`(Fed. Cir. 2004) (additional citations omitted). Additionally, Petitioner’s
`proposed corresponding structure would itself be formulated in functional
`terms, which is not illuminating.
`Similarly, with respect to “delay unit,” Petitioner goes further, arguing
`that “the ’302 patent does not specify delay 307 and delay 317 as anything
`more than a black box,” and that claim 10 may not be capable of
`construction. Id. at 24–25. Based on the record before us, however, we do
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`not agree and we determine that one of ordinary skill in the art, would have
`understood the structure of a delay unit. Petitioner has not represented,
`much less explained, that one with ordinary skill in the art would not have
`recognized that “delay unit” is a recognized term of art and would not have
`recognized what structure is conveyed by “delay unit.” Additionally, as
`discussed above, we are also not persuaded that Petitioner’s proffered
`structure of “‘one or more circuit components that delay a signal’ and its
`equivalents” would provide any greater clarity in construing the claim term,
`or claim 10 as a whole.
`Only terms which are in controversy need to be construed, and only to
`the extent necessary to resolve the controversy. See Wellman, Inc. v.
`Eastman Chem. Co., 642 F.3d 1355, 1361 (Fed. Cir. 2011); Vivid Techs.,
`Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999). Based on
`the discussion above, we are persuaded that no term requires an express
`construction at this time.
`
`Level of Ordinary Skill in the Art
`B.
`With regard to the level of ordinary skill in the art, Petitioner states:
`
`“A person of ordinary skill in the art at the time of the alleged invention of
`the ’302 patent would have had at least a Bachelor’s degree in electrical
`engineering, or equivalent thereof, and at least two to three years of
`experience in design of semiconductor memory circuits.” Pet. 5. Petitioner
`further states that “[m]ore education can supplement practical experience
`and vice versa.” Id. Petitioner’s position is supported by the Declaration of
`Dr. Baker. Ex. 1002 ¶ 19. On this record, we adopt Petitioner’s articulation
`of the level of ordinary skill.
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`Principles of Law
`C.
`To establish anticipation, each and every element in a claim, arranged
`as recited in the claim, must be found in a single prior art reference.
`Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1369 (Fed. Cir. 2008);
`Karsten Mfg. Corp. v. Cleveland Golf Co., 242 F.3d 1376, 1383 (Fed. Cir.
`2001). While the elements must be arranged in the same way as is recited in
`the claim, “the reference need not satisfy an ipsissimis verbis test.” In re
`Gleave, 560 F.3d 1331, 1334 (Fed. Cir. 2009); In re Bond, 910 F.2d 831,
`832–33 (Fed. Cir. 1990)). Thus, identity of terminology between the prior
`art reference and the claim is not required. “A reference anticipates a claim
`if it discloses the claimed invention ‘such that a skilled artisan could take its
`teachings in combination with his own knowledge of the particular art and
`be in possession of the invention.’” In re Graves, 69 F.3d 1147, 1152 (Fed.
`Cir. 1995). That means prior art references must be “considered together
`with the knowledge of one of ordinary skill in the pertinent art.” In re
`Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994). Also, “it is proper to take
`into account not only specific teachings of the reference but also the
`inferences which one skilled in the art would reasonably be expected to draw
`therefrom.” In re Preda, 401 F.2d 825, 826 (CCPA 1968).
`A claim is unpatentable under 35 U.S.C. § 103 if “the differences
`between the subject matter sought to be patented and the prior art are such
`that the subject matter as a whole would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
`subject matter pertains.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007). The question of obviousness is resolved on the basis of underlying
`factual determinations, including: (1) the scope and content of the prior art;
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`(2) any differences between the claimed subject matter and the prior art;
`(3) the level of skill in the art; and (4) objective evidence of nonobviousness,
`i.e., secondary considerations. See Graham v. John Deere Co. of Kansas
`City, 383 U.S. 1, 17–18 (1966).
`“In an [inter partes review], the petitioner has the burden from the
`onset to show with particularity why the patent it challenges is
`unpatentable.” Harmonic Inc. v. Avid Tech., Inc., 815 F.3d 1356, 1363 (Fed.
`Cir. 2016) (citing 35 U.S.C. § 312(a)(3) (requiring inter partes review
`petitions to identify “with particularity . . . the evidence that supports the
`grounds for the challenge to each claim”)). This burden never shifts to
`Patent Owner. See Dynamic Drinkware, LLC v. Nat’l Graphics, Inc., 800
`F.3d 1375, 1378 (Fed. Cir. 2015) (citing Tech. Licensing Corp. v. Videotek,
`Inc., 545 F.3d 1316, 1326–27 (Fed. Cir. 2008)) (discussing the burden of
`proof in inter partes review). Furthermore, Petitioner cannot satisfy its
`burden of proving obviousness by employing “mere conclusory statements.”
`In re Magnum Oil Tools Int’l, Ltd., 829 F.3d 1364, 1380 (Fed. Cir. 2016).
`D. Alleged Obviousness of
`Claims 1–5 and 10–12 over Seo and Min
`We have reviewed the Petition and determine that Petitioner has
`
`shown a reasonable likelihood that it would prevail in establishing
`unpatentability of each of claims 1–5 and 10–12 as obvious over Seo and
`Min.
`
`Seo
`1.
`Seo relates to semiconductor memory devices, and more particularly to
`sense amplifier circuitry for sensing data from memory cells. Ex. 1004, 1:7–
`8. Figure 5 of Seo is reproduced below:
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`Figure 5 illustrates the circuitry of a sense amplifier driver according to one
`embodiment. Id. at 3:22–23.
`
`Sensing clock driver 10 generates a signal at node LAG that drives the
`gate of the NMOS transistor Ts to a high value, which turns on transistor Ts
`and connects sense amplifier 40 to Vss. Id. at 5:55–58, 7:4–10. Seo
`discloses that “[i]f a sensing enable state is established by the equalization
`control clock Qeq being at the Vss level and the sensing clock signal Qs
`being at the Vcc level, then node ‘d’ of sensing clock driver 10 [falls] to Vss
`level immediately owing to the function of n-channel MOS transistor Th of
`inverter IV10,” causing transistor Te to immediately turn on. Id. at 6:56–63.
`Seo continues that transistor Ts is not turned on completely because
`transistor Te has a small current driving capability and is unable to pull up
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`signal LAG immediately to the Vcc level to completely turn on transistor Ts.
`Id. at 6:63–66. Thereafter, node “e” is lowered to Vss level after having
`been delayed for a certain period due to resistor R3 of inverter IV10 and
`transistor Td turns on. Id. at 6:67–7:4. “Therefore, the potential of node
`LAG raises to Vcc level with a multi-slope characteristics, so that it can
`completely turn on the n-channel MOS sense transistor Ts.” Id. at 7:4–7.
`The resultant sensing signal LAB of the Vss level carries out the sensing
`operation for the data stored in the memory cell. Id. at 7:7–10. This process
`is also illustrated in Figure 6 of Seo, with Petitioner’s annotations,
`reproduced below:
`
`
`See Pet. 13; Ex. 1002 ¶ 56. Figure 6 provides a timing chart illustrating the
`operations of the circuit. Id. at 3:24–26.
`2. Min
`Min describes a “sense amplifier driving circuit which is suitable for
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`use in a high density semiconductor memory device.” Ex. 1005, 1:6–8. Min
`discloses a prior art sense amplifier driver circuit in Figure 1A, which is
`reproduced below:
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`
`
`Figure 1A provides schematic diagram of a first conventional sense
`amplifier driving circuit. Id. at 1:28–29.
`The sense amplifiers SA1–SAn are connected to one another at node
`LAP and at LAN, respectively, and are connected to Vcc and Vss by driving
`transistors Q1 and Q2, respectively. Min discloses a variation of the
`Figure 1A sense amplifier driving circuit arrangement in Figure 1B, which is
`reproduced below:
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`Figure 1B provides schematic diagram of a second conventional sense
`amplifier driving circuit. Id. at 1:31–32. In this circuit, each sense amplifier
`is provided with its own respective driving transistor, with Q1i connected to
`Vcc and Q2i connected to VSS, as illustrated.
`Figure 9 of Min depicts an improved driver circuit, which is
`reproduced below with a corresponding timing diagram:
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`Figure 9 is a schematic circuit diagram of and a timing chart for a sense
`amplifier driving circuit according to one embodiment. Id. at 13:5–9.
`Min details that a dual slope characteristic for signal ϕLAP (voltage at
`node LAP) is achieved by a sequential pull-down approach by which a first
`pull-down path is activated to pull down the voltage at the gate of PMOS
`transistor Q110, and then after a delay a second pull-down path is activated.
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`Id. at 29:18–30:3. Min also discloses that “signal ϕSP1 is set to have a high
`level,” which turns on NMOS transistor Q112, and after a certain period of
`time, the second active restore signal ϕSP2 goes to a high level and transistor
`Q115 is turned on so that the current Icca flowing through the driving
`transistor is increased. Id. at 29:21–34. Turning on transistor Q112
`activates a first pull-down path for pulling down the voltage at the gate of
`transistor Q110, and subsequently turning on transistor Q115 activates a
`second pull-down path for pulling down that same gate voltage. See
`Ex. 1002 ¶ 67.
`Independent claims 1 and 10
`3.
`Following the order of the Petition, we first discuss claim 10, and then
`claim 1. Claim 1 is directed to a memory device, whereas claim 10 is
`directed to a sense amplifier clock driver circuit, which makes up a portion
`of an integrated circuit memory. As such, the discussion of the elements of
`claim 10 simplifies the discussion with respect to claim 1.
`Petitioner asserts that Seo discloses a sensing clock driver 10 (“sense
`amplifier clock driver circuit”) for a CMOS DRAM cell (“integrated circuit
`memory”), the sensing clock driver 10 providing a clock signal at node LAG
`(“at least one clock signal”) for controlling operation of an NMOS transistor
`Ts (“sense amplifier driver transistor”), as shown in Fig. 5. Pet. 25–26
`(citing Ex. 1002 ¶¶ 77–78). Petitioner acknowledges that Seo fails to
`explicitly disclose multiple “sense amplifier driver transistors,” or that they
`are controlled by a single signal, as recited in claim 10, but argues that Min
`discloses multiple sense amplifier driver transistors, and that it would have
`been obvious to one of ordinary skill in the art to implement Seo’s sense
`amplifier clock driver to provide a signal for controlling the operation of
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`multiple transistors, as disclosed in Min. Id. at 29–30. Petitioner continues
`that one of ordinary skill in the art would have looked to Min for guidance
`regarding possible implementations and uses of sense amplifier driver
`circuits, where the latter discloses that the use of and control over multiple
`sense amplifiers would have been conventional, as illustrated in Min’s
`Figures 1A and 1B. Id. at 30–34 (citing Ex. 1002 ¶¶ 85–89, Ex. 1005,
`Figs. 1A, 1B). Additionally, Petitioner asserts that one of ordinary skill
`would have recognized that the modification would have improved the
`performance of Seo’s memory device by increasing the number of sense
`amplifiers as taught by Min, which would have enabled Seo’s technique of
`driving a sense amplifier to be implemented in a memory device having
`many columns of memory cells, as was common at the time of the alleged
`invention of the ’302 Patent. Id. at 35 (citing Ex. 1002 ¶91).
`Petitioner also asserts that Seo discloses that a node at the input to
`inverter IV10 (“sense control signal node”) receives sensing clock signal Qs
`(“externally generated sense control signal”) indicating when sensing is to
`occur. Id. at 36 (citing Ex. 1002 ¶¶ 92–95, Ex. 1004, 6:56–7:10). Petitioner
`also argues that one of ordinary skill would have understood that sensing
`clock signal Qs is an “externally generated sense control signal” because it
`is received by and generated externally relative to the sensing clock driver
`10 shown in FIG. 5 of Seo. Id. at 37 (citing Ex. 1002 ¶ 95).
`Petitioner also asserts that Seo discloses that the resistance (“first
`impedance”) of transistor Te has a terminal coupled to Vcc (“a selected logic
`level signal”). Id. at 37–38 (citing Ex. 1002 ¶¶ 96–101). Petitioner asserts
`as well that one of ordinary skill would have known that every MOSFET has
`associated parasitic resistance and a channel resistance, so that the total
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`device resistance of transistor Te is the sum of a parasitic impedance Rsd
`across the source and drain terminals of transistor Te and a channel
`resistance Rch, with the total device resistance of transistor Te is equivalent
`to the “first impedance” recited in claim 10. Id. at 38–41 (citing Ex. 1002
`¶¶ 98–101; Ex. 1008, 205–06).
`Petitioner also asserts that Seo discloses that transistor Te (“a first
`switch”) has a source and drain (“current carrying electrodes”) coupled to
`drive the signal on line LAG (“clock signal”) to Vcc (“selected logic level”)
`when transistor Te is turned on by Qs (“sense control signal”) being at Vcc.
`Id. at 42–44 (citing Ex. 1002 ¶¶ 102–105; Ex. 1004, 6:56–66). Petitioner
`also asserts that Seo discloses that a resistance R3 (“delay unit”) that a
`skilled artisan would have understood is coupled, via node d, to the node at
`which Qs is received (“coupled to the sense control signal”), because when
`Qs is at Vcc (high), node d falls to Vss immediately. Id. at 44–46 (citing Ex.
`1002 ¶¶ 106–109; Ex. 1004, 6:56–61, Fig. 5).
`Petitioner also asserts that Seo discloses that the resistance (“a second
`impedance”) of transistor Td has a terminal coupled to Vcc (“having a
`terminal coupled to the selected logic level signal”), relying on an intrinsic
`impedance of Td, similar to the impedance of Te, discussed above. Id. at
`46–49 (citing Ex. 1002 ¶¶ 110–112; Ex. 1004, Fig. 5). With respect to the
`second switch limitation, Petitioner asserts that Seo discloses that transistor
`Td (“a second switch”) has a source and drain (“current carrying
`electrodes”) coupled to drive the signal on line LAG (“clock signal”) to Vcc
`(“selected logic level”) when transistor Td is turned on by the delayed sense
`control signal at node e. Id. at 49–52 (citing Ex. 1002 ¶¶ 113–115;
`Ex. 1004, 6:67–7:7, Fig. 5). With respect to the last element of claim 10,
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`Petitioner asserts that the signal at node e (i.e., the gate of transistor Td) of
`Seo is a “delayed sense control signal,” as discussed above. Id. at 49–52
`(citing Ex. 1002 ¶¶ 116–118; Ex. 1004, Fig. 5).
`We are sufficiently persuaded that Petitioner has demonstrated, based
`on the present record, that Seo and Min accounts for all of the elements of
`claim 10, and that Petitioner has also provided sufficient rationale to
`combine Seo and Min to account for of the limitations of claim 10.
`With respect to claim 1, as discussed above, Seo discloses a memory
`device, and Min discloses a plurality of sense amplifiers, with each having a
`power node that receives current. Id. at 57–61 (citing Ex. 1002 ¶¶ 123–127;
`Ex. 1004, Abstract, 7:7–10; Ex. 1005, Fig. 1B). Petitioner asserts that one of
`ordinary skill would have understood that the sense amplifiers SA1-SAn of
`Min would have to be “distributed” about the memory device because these
`circuits would be provided in a distributed manner on a circuit chip, and that
`one of ordinary skill would have turned to Min for guidance regarding
`implementation of Seo’s sense amplifier driver circuitry to a plurality of
`sense amplifiers. Id. at 61–63 (citing Ex. 1002 ¶¶ 128–131).
`Further with respect to claim 1, Petitioner asserts that the line
`conducting Vss in both Seo (Ex. 1004, Fig. 5) and Min (Ex. 1005, Fig. 1B)
`is a “power supply conductor” because one of ordinary skill understood that
`“Vcc” and “Vss” are traditionally used as labels for power supply lines
`corresponding to positive power and ground, respectively. Pet. 64 (citing
`Ex. 1002 ¶ 133). As well, Petitioner asserts that one of ordinary skill would
`have been motivated to use a “low-impedance” power supply conductor
`(e.g., a conductor with a lower parasitic resistance) for the Vss power supply
`conductor given that a high impedance conductor would have caused
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`parasitic resistance issues discussed above. Id. at 66 (citing Ex. 1002 ¶ 135).
`The “at least one drive transistor” element of claim 1 is argued by
`Petitioner as being taught by a combination of Seo and Min as illustrated in
`an annotated version of Min’s Figure 1B, which is reproduced below:
`
`
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`Id. at 67. Annotated Fig. 1B of Min combined with elements of Seo.
`Petitioner asserts that in the combined Seo-Min system, each of
`driving transistors Q21–Q2n (“at least one drive transistor”) has a source
`terminal (“first current carrying electrode”) coupled to Vss (“power supply
`conductor”), and the drain terminal (“second current carrying electrode”) of
`each transistor Q21–Q2n is coupled to respective latch nodes LAN (“power
`nodes”) of n sense amplifiers SA1–SAn (“preselected number of the sense
`amplifiers”). Id. (citing Ex. 1002 ¶ 137). Petitioner also asserts that each
`transistor Q21–Q2n has a gate terminal (“control electrode”) coupled to the
`LAG signal. Id.
`Further with respect to “a control line,” of claim 1, Petitioner argues
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`that the line along which the LAG signal is provided, in the combined Seo-
`Min system, is a “control line.” Id. at 68. With respect to the “timer unit”
`limitation, Petitioner argues that in the combined Seo-Min system, the signal
`at node LAG is generated by clock driver 10 shown in FIG. 5 of Seo that
`includes transistors Td and Te and resistor R3, which delays a signal at node
`d to generate a signal at node e. Id. at 68–69 (citing Ex. 1004, FIG. 5;
`Ex. 1002, ¶ 139). Petitioner regards the transistors Td and Te, and resistor
`R3, as the structure that constitutes the “timer unit,” as it causes a delay in
`lowering of the potential of node “e” to the Vss level. Id. at 69 (citing Ex.
`1004, 6:54-7:10, Figs. 5, 6).
`With respect to the first and second components with the timer unit of
`claim 1, Petitioner argues that the LAG signal is generated by clock driver
`10, which includes transistor Te causing the LAG signal (“control signal”) to
`change from Vss towards Vcc at a rate corresponding to the current driving
`capability of transistor Te (“causing the control signal to change from a first
`logic level towards a second logic level at a first rate”). Id. at 70 (citing
`Ex. 1004, 6:56–66, Figs. 5 (showing transistor Te), 6 (showing change over
`time for signal LAG); Ex. 1002 ¶142). Additionally, the clock driver 10
`includes transistor Td, which causes the LAG signal to change to Vcc at a
`rate corresponding to its current driving capability (“causing the control
`signal to change to the second logic level at a second rate”). Id. at 70 (citing
`Ex. 1002 ¶ 144; Ex. 1004, Figs. 5, 6, 6:67–7:7).
`
`We are sufficiently persuaded that Petitioner has demonstrated, based
`on the present record, that Seo and Min account for all of the elements of
`claim 1, and that Petitioner has also provided sufficient rationale to combine
`Seo and Min to account for all of the limitations of claim 1. For the
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`foregoing reasons, Petitioner has shown a reasonable likelihood that it would
`establish unpatentability of claims 1 and 10 as being obvious over Seo and
`Min.
`
`Claims 2–5, 11, and 12
`4.
`Claims 2–5 depend from claim 1, and claims 11 and 12 depend from
`
`claim 10. We have reviewed the Petition and determine that Petitioner has
`shown a reasonable likelihood that it would prevail in establishing the
`unpatentability of each of claims 2–5, 11, and 12 as obvious over Seo and
`Min.
`
`Petitioner accounts for the added limitation of claim 2 relative to base
`claim 1. Pet. 73. Petitioner accounts for the added limitation of claim 3
`relative to claim 2, from which is dep
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