Paper No. 15
`Trials@uspto.gov
`Filed: April 4, 2018
`571.272.7822
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`PROMOS TECHNOLOGIES, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-00039
`Patent 6,195,302 B1
`____________
`
`
`
`Before JAMESON LEE, KEVIN F. TURNER, and
`JOHN A. HUDALLA, Administrative Patent Judges.
`
`TURNER, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`Inter Partes Review
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`
`Trials@uspto.gov
`Filed: April 4, 2018
`571.272.7822
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`PROMOS TECHNOLOGIES, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-00039
`Patent 6,195,302 B1
`____________
`
`
`
`Before JAMESON LEE, KEVIN F. TURNER, and
`JOHN A. HUDALLA, Administrative Patent Judges.
`
`TURNER, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`Inter Partes Review
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`
`
`IPR2017-00039
`Patent 6,195,302 B1
`Petitioner, Samsung Electronics Co., Ltd. (“Petitioner”), filed a
`Petition (Paper 2, “Pet.”) requesting an inter partes review of claims 1–6,
`10–12, and 14–18 of U.S. Patent No. 6,195,302 B1 (Ex. 1001, “the
`’302 Patent”) pursuant to 35 U.S.C. §§ 311–319. Patent Owner, ProMOS
`Technologies, Inc. (“Patent Owner”), did not file a Preliminary Response.
`We determined that the information presented in the Petition established that
`there is a reasonable likelihood that Petitioner would prevail in challenging
`claims 1–6, 10–12, and 14–18 of the ’302 Patent under 35 U.S.C. § 103(a).
`Pursuant to 35 U.S.C. § 314, we instituted this proceeding on April 11,
`2017, as to the challenged claims of the ’302 Patent. Paper 6 (“Institution
`Decision” or “Dec. on Inst.”).
`During the course of trial, Patent Owner filed a Patent Owner
`Response (Paper 10, “PO Resp.”), and Petitioner filed a Reply to the Patent
`Owner Response (Paper 12, “Reply”). The parties filed a “Joint Stipulation
`Regarding Scheduling Order” (Paper 13) in which “the parties waive[d] oral
`argument in this proceeding,” so no oral hearing was held. See Paper 14.
`We have jurisdiction under 35 U.S.C. § 6. This decision is a Final
`Written Decision under 35 U.S.C. § 318(a) as to the patentability of claims
`1–6, 10–12, and 14–18 of the ’302 Patent. For the reasons discussed below,
`Petitioner has demonstrated by a preponderance of the evidence that the
`challenged claims are unpatentable.
`
`
`I. BACKGROUND
`
`Related Proceedings
`A.
`Petitioner and Patent Owner indicate that the ’302 Patent has been
`
`asserted by Patent Owner in ProMOS Technologies, Inc. v. Samsung
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`2
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`IPR2017-00039
`Patent 6,195,302 B1
`Electronics Co., Ltd., et al., No. 1:15-cv-898-SLR-SRF (D. Del.). Pet. 1;
`Paper 5, 1. The ’302 Patent is also the subject of another petition, also filed
`by Petitioner, seeking inter partes review of claims 1–6 and 10–12 under
`different grounds of unpatentability, IPR2017-00038, where a trial was
`instituted in that proceeding as well.
`Petitioner and Patent Owner indicate that these patents are related to
`the ’302 patent: U.S. Patent Nos. 5,761,112; 6,849,897; 6,020,259;
`6,088,270; and 6,699,789. Id. Patent Owner identifies these inter partes
`review proceedings for the related patents: IPR2017-00032 (Patent No.
`6,849,897); IPR2017-00033 and IPR2017-00035 (Patent No. 6,020,259);
`IPR2017-00036 (Patent No. 6,088,270); IPR2017-00037 (Patent No.
`6,699,789); and IPR2017-00040 (Patent No. 5,761,112). Paper 5, 1.
`
`The ’302 Patent
`The ’302 Patent is directed to a random access memory and the
`operations within a random access memory for reading or refreshing
`memory cells, specifically applied to sense amplifiers. Ex. 1001, 1:7–9.
`
`B.
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`3
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`IPR2017-00039
`Patent 6,195,302 B1
`The ’302 Patent discloses a memory device with sense amplifiers, as
`illustrated in Figure 1, reproduced below:
`
`
`
`Figure 1 illustrates a memory device according to an embodiment of the
`’302 Patent.
`Sense amplifiers 101a–101c are coupled to high voltage line Vcc and
`ground via driver transistors 104 and 106, respectively. Id. at 4:40–5:4.
`Driver transistors 104, which are PMOS pull-up transistors, and driver
`transistors 106, which are NMOS pull-down transistors, are controlled by
`control signals LPB and LNB, respectively. Id. The ’302 Patent illustrates
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`4
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`IPR2017-00039
`Patent 6,195,302 B1
`the functionalities of the sense amplifiers with respect to Figure 2,
`reproduced below:
`
`
`
`Figure 2 illustrates a portion of a memory device according to an
`embodiment of the ’302 Patent.
`The ’302 Patent discloses that storage capacitors 201 are selectively
`coupled to bit lines 202 through access switches 203 in response to address
`signals supplied to word lines 204. Id. at 5:5–9. Prior to a read operation, a
`pair of bit lines 202 are “equalized at some voltage between a logic high and
`a logic low signal,” and a word line (WL) signal is activated. Id. at 5:18–21,
`5:35–37. After the WL signal is activated, “the LPB signal is driven to a
`logic low[,] coupling VCCI to sense amp 101 through drive transistor 104
`[and] [s]imilarly, the LNB signal is driven high to couple sense amp 101 to
`ground or VSS through drive transistor 106.” Id. at 5:38–42. The ’302 Patent
`also provides that “LNB and LPB are generated by a circuit such as that
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`5
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`IPR2017-00039
`Patent 6,195,302 B1
`shown in FIG. 3 that generates LNB and LBP both as dual slope signals.”
`Id. at 5:45–47. Figure 3 is reproduced below:
`
`
`
`Figure 3 illustrates timer circuit according to an embodiment of the ’302
`Patent.
`The ’302 Patent discloses that when sensing is to begin, “one of the
`input signals SENR or SENL will go to a logic high,” which causes
`signal 302 to transition to a logic low because of NOR gate 301 and
`inverter 304. Id. at 5:66–6:6. Signal LPB is disclosed as being generated as
`follows:
`
`[S]hortly after either SENR or SENL goes high,
`transistor 303 is turned on pulling the LPB signal low through
`resist[o]r 306. . . . Resistor 316 controls the rate of change or
`dv/dt of LNB while resistor 306 controls the dv/dt of LPB. After
`a delay determined by delay element 307, transistor 308 will be
`turned on pulling LPB to ground with a much lower resistance.
`When transistor 308 is turned on, LPB will fall to the ground
`voltage with a high dv/dt.
`Id. at 6:8–18.
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`6
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`IPR2017-00039
`Patent 6,195,302 B1
`Signal LNB is generated in a similar manner (i.e., a first pull-up path
`corresponding to transistor 313 is enabled, and then after a delay, a second
`pull-up path corresponding to transistor 318 is enabled, while the first pull-
`up path is still enabled), id. at 6:33–36, with both signals, LNB and LPB,
`being generated as “dual slope signals.” Id. at 5:45–47.
`Claims 1, 10, and 14 of the challenged claims of the ’302 Patent are
`independent and reproduced below:
`1. A memory device comprising:
`a plurality of sense amplifiers distributed about an integrated circuit chip,
`each sense amplifier having a power node for receiving current;
`a low-impedance power supply conductor;
`at least one drive transistor having a first current carrying electrode
`coupled to the power supply conductor, a second current carrying
`electrode coupled to the power nodes of a preselected number of the
`sense amplifiers, and a control electrode;
`a control line coupled to the control electrode;
`a timer unit having an output coupled to the control electrode and
`generating a control signal;
`a first component within the timer unit causing the control signal to
`change from a first logic level towards a second logic level at a first
`rate; and
`a second component within the timer unit causing the control signal to
`change to the second logic level at a second rate, wherein the second
`rate is greater than the first rate such that the first component and the
`second component are concurrently activated to cumulatively affect
`the rate of change to the second logic level.
`
`
`10. A sense amplifier clock driver circuit for an integrated circuit
`memory, the driver circuit providing at least one clock signal for
`controlling the operation of sense amplifier driver transistors and
`comprising:
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`IPR2017-00039
`Patent 6,195,302 B1
`a sense control signal node receiving an externally generated sense
`control signal indicating when sensing is to occur;
`a first impedance having a terminal coupled to a selected logic level
`signal;
`a first switch having current carrying electrodes coupled to drive the
`clock signal to a selected logic level through the first impedance, the
`first switch controlled by the sense control signal;
`a delay unit coupled to the sense control signal node and generating a
`delayed sense control signal;
`a second impedance having a terminal coupled to the selected logic level
`signal; and
`a second switch having current carrying electrodes coupled to drive the
`clock signal to the selected logic level through the second impedance,
`the second switch controlled by the delayed sense control signal such
`that the first switch and the second switch are concurrently activated
`after the delayed sense control signal is generated.
`after the delayed sense control signal is generated.
`
`
`14. A method for generating a control signal for controlling the operation
`of sense amplifier driver transistors in an integrated circuit memory
`device comprising:
`providing a sense amplifier drive transistor having a control terminal
`coupled to receive the control signal and having a power node for
`supplying current to a preselected number of sense amplifiers;
`placing the control signal at a level selected to turn off the driver
`transistors;
`coupling a signal to be sensed to a latch node of the sense amplifier;
`supplying the charge from an external power supply to the sense
`amplifier driver transistor through a first impedance at a first rate; and
`after a delay, supplying charge to the sense amplifier driver transistor
`through a second impedance at a second rate in addition to continuing
`to supply charge through the first impedance.
`Ex. 1001, 8:11–33, 9:10–34, 10:12–31.
`
`8
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`IPR2017-00039
`Patent 6,195,302 B1
`
`C.
`
`Instituted Grounds
`We instituted trial based on the following grounds (Dec. on Inst. 32):
`Reference(s)
`Basis
`Claim(s) Challenged
`
`Min1
`
`Min and Seo2
`
`§ 103(a)
`
`§ 103(a)
`
`14 and 15
`
`1–5 and 10–12
`
`Min, Seo, and Schuster3
`
`§ 103(a)
`
`6
`
`Min and Tobita4
`
`§ 103(a)
`
`16 and 17
`
`Min and Schuster
`
`18
`
`§ 103(a)
`
`II. ANALYSIS
`Post-Institution Analysis
`In our Decision on Institution, we concluded that the argument and
`evidence adduced by Petitioner demonstrated a reasonable likelihood that
`claims 1–6, 10–12, and 14–18 are unpatentable as anticipated or obvious
`based on the challenges identified in the table in Section I.C above. Dec. on
`Inst. 32. We must now determine whether Petitioner has established by a
`preponderance of the evidence that the specified claims are unpatentable
`over the cited prior art. 35 U.S.C. § 316(e). In this regard, we previously
`instructed Patent Owner that “any arguments for patentability not raised in
`
`A.
`
`
`1 UK Patent No. GB2246005B, published Aug. 31, 1994 (Ex. 1005, “Min”).
`2 U.S. Patent No. 5,140,199, issued Aug. 18, 1992 (Ex. 1004, “Seo”).
`3 Stanley E. Schuster et al., “A 15-ns CMOS 64K RAM,” IEEE J. of Solid-
`State Circuits, Vol. SC-21, No. 5, pp.704–12 (Oct. 1986) (Ex. 1007,
`“Schuster”).
`4 U.S. Patent No. 4,980,799, issued Dec. 25, 1990 (Ex. 1009, “Tobita”).
`9
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`IPR2017-00039
`Patent 6,195,302 B1
`the [Patent Owner Response] will be deemed waived.” Paper 7, 3; see also
`In re Nuvasive, Inc., 842 F.3d 1376, 1381 (Fed. Cir. 2016) (holding that
`patent owner’s failure to proffer argument at trial as instructed in scheduling
`order constitutes waiver). Additionally, the Board’s Trial Practice Guide
`states that the Patent Owner Response “should identify all the involved
`claims that are believed to be patentable and state the basis for that belief.”
`Office Patent Trial Practice Guide, 77 Fed. Reg. 48,756, 48,766 (Aug. 14,
`2012).
`Patent Owner’s Response to the Petition is limited to a reservation of
`its rights, noting that the “Supreme Court granted certiorari in Oil States
`Energy Servs., LLC v. Greene’s Energy Grp., LLC, No. 16-712, 2017 WL
`2507340 (U.S. June 12, 2017)” to consider the constitutionality of inter
`partes review proceedings, and Patent Owner reserves its right to argue that
`any ruling be applicable to the instant proceeding. PO Resp. 1. Petitioner
`responds that “Patent Owner does not submit any arguments contesting the
`merits of the Decision or the evidence set forth by Petitioner.” Reply 1. We
`agree that Patent Owner has not contested the instituted grounds and
`evidence. As such, the arguments and evidence presented by Petitioner,
`which we deemed to show a reasonable likelihood of Petitioner
`demonstrating unpatentability of the challenged claims, must now
`demonstrate unpatentability by a preponderance of the evidence.
`
`Level of Ordinary Skill in the Art
`In determining the level of skill in the art, various factors may be
`considered, including the “type of problems encountered in the art; prior art
`solutions to those problems; rapidity with which innovations are made;
`
`B.
`
`10
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`IPR2017-00039
`Patent 6,195,302 B1
`sophistication of the technology; and educational level of active workers in
`the field.” In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995) (citing
`Custom Accessories, Inc. v. Jeffrey-Allan Indus., Inc., 807 F.2d 955, 962
`(Fed. Cir. 1986)). In addition, the prior art of record in this proceeding—
`namely, Inoue, Ogawa, and Okamura—is indicative of the level of skill in
`the art. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001);
`GPAC, 57 F.3d at 1579; In re Oelrich, 579 F.2d 86, 91 (CCPA 1978).
`With regard to the level of ordinary skill in the art, Petitioner states:
`“A person of ordinary skill in the art at the time of the alleged invention
`(‘POSITA’) of the ’302 patent would have had at least a Bachelor’s degree
`in electrical engineering or equivalent thereof, and at least two to three years
`of experience in design of semiconductor memory circuits.” Pet. 5–6.
`Petitioner further states that “[m]ore education can supplement practical
`experience and vice versa.” Id. at 6. Petitioner’s position is supported by
`the Declaration of Dr. Baker. Ex. 1002 ¶ 19. We applied this definition of
`the level of ordinary skill in the art in our Institution Decision. See Dec. on
`Inst. 11.
`We discern no reason to change our determination that Petitioner’s
`proposed definition comports with the qualifications a person would need to
`understand and implement the teachings of the ’302 Patent and the prior art
`of record. Accordingly, we apply Petitioner’s definition of the level of
`ordinary skill in the art.
`
`Claim Interpretation
`In an inter partes review, claim terms in an unexpired patent are
`interpreted according to their broadest reasonable construction in light of the
`
`C.
`
`11
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`IPR2017-00039
`Patent 6,195,302 B1
`specification of the patent in which they appear. See 37 C.F.R. § 42.100(b);
`Cuozzo Speed Techs., LLC v. Lee, 136 S. Ct. 2131, 2142–46 (2016).
`Consistent with that standard, we assign claim terms their ordinary and
`customary meaning, as would be understood by one of ordinary skill in the
`art at the time of the invention, in the context of the entire patent disclosure.
`See In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).
`There are, however, two exceptions: “1) when a patentee sets out a
`definition and acts as his own lexicographer,” and “2) when the patentee
`disavows the full scope of a claim term either in the specification or during
`prosecution.” Thorner v. Sony Comp. Entm’t Am. LLC, 669 F.3d 1362, 1365
`(Fed. Cir. 2012). It is inappropriate to limit a claim to a preferred
`embodiment without a clear intent in the specification to redefine a claim
`term or a clear disavowal of claim scope. See id. Limitations that are not a
`part of the claim should not be imported into the claim. See SuperGuide
`Corp. v. DirecTV Enters., Inc., 358 F.3d 870, 875 (Fed. Cir. 2004).
`In our Institution Decision, we considered Petitioner’s proposal (see
`Pet. 8–15) to construe specific claim terms according to 35 U.S.C. § 112,
`sixth paragraph. Dec. on Inst. 9–10. We determined that persons of
`ordinary skill in the art would have understood the structures recited in the
`specific claim terms such that those terms would have not been understood
`as nonce words, implicating 35 U.S.C. § 112, sixth paragraph. Id. (citing
`Lighting World, Inc. v. Birchwood Lighting, Inc. 382 F.3d 1354, 1359–60
`(Fed. Cir. 2004)). We additionally determined that no claim term required
`an express construction. Id. at 11. In the absence of any reason to change
`our findings, we maintain our determination that no express claim
`construction is necessary.
`
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`
`D. Obviousness Ground Based on Min
`Petitioner contends claims 14 and 15 are obvious over Min. Pet. 16–
`35. We begin with a review of the cited reference and then address
`Petitioner’s contentions.
`1. Min
`Min describes a “sense amplifier driving circuit which is suitable for
`use in a high density semiconductor memory device.” Ex. 1005, 1:6–8. Min
`discloses a prior art sense amplifier driver circuit in Figure 1A, which is
`reproduced below:
`
`
`
`Figure 1A provides schematic diagram of a first conventional sense
`amplifier driving circuit. Id. at 1:28–29.
`The sense amplifiers SA1–SAn are connected to one another at node
`LAP and at LAN, respectively, and are connected to Vcc and Vss by driving
`transistors Q1 and Q2, respectively. Min discloses a variation of the
`Figure 1A sense amplifier driving circuit arrangement in Figure 1B, which is
`reproduced below:
`
`13
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`IPR2017-00039
`Patent 6,195,302 B1
`
`
`Figure 1B provides schematic diagram of a second conventional sense
`amplifier driving circuit. Id. at 1:31–32. In this circuit, each sense amplifier
`is provided with its own respective driving transistor, with Q1i connected to
`Vcc and Q2i connected to VSS, as illustrated.
`Min also discloses an improved driver circuit, which is reproduced
`below with a corresponding timing diagram as illustrated in Figure 9:
`
`14
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`IPR2017-00039
`Patent 6,195,302 B1
`
`
`Figure 9 is a schematic circuit diagram of and a timing chart for a sense
`amplifier driving circuit according to one embodiment. Id. at 13:5–9.
`Min details that a dual slope characteristic for signal ϕLAP (voltage at
`node LAP) is achieved by a sequential pull-down approach by which a first
`pull-down path is activated to pull down the voltage at the gate of PMOS
`transistor Q110, and then after a delay a second pull-down path is activated.
`Id. at 29:18–30:3. Min also discloses that “signal ϕSP1 is set to have a high
`level,” which turns on NMOS transistor Q112, and after a certain period of
`time, the second active restore signal ϕSP2 goes to a high level and transistor
`15
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`IPR2017-00039
`Patent 6,195,302 B1
`Q115 is turned on so that the current Icca flowing through the driving
`transistor is increased. Id. at 29:21–34. Turning on transistor Q112
`activates a first pull-down path for pulling down the voltage at the gate of
`transistor Q110, and subsequently turning on transistor Q115 activates a
`second pull-down path for pulling down that same gate voltage. See
`Ex. 1002 ¶ 67.
`Independent claim 14
`2.
`With respect to the preamble of claim 14, Petitioner asserts that Min
`discloses a driving circuit that controls “the current Icca flowing through the
`driver transistor Q110,” which controls the voltage at node LAP. Pet. 16
`(citing Ex. 1005, 29:15–30:3, Fig. 9; Ex. 1002 ¶ 76). Petitioner argues that
`one of ordinary skill in the art would have understood that Min’s disclosure
`of a “sense amplifier driving circuit which is suitable for use in a high
`density semiconductor memory device” is equivalent to “an integrated
`circuit memory device,” as claimed. Id. at 17 (citing Ex. 1005, 1:4–9;
`Ex. 1002 ¶ 78).
`With respect to the providing step of claim 14, Petitioner asserts that
`Min discloses that the driving circuit of Figure 9 controls the gate voltage of
`driving transistors. Id. at 17 (citing Ex. 1005, 27:28–30, 28:4–8, Fig. 9;
`Ex. 1002 ¶ 79). Petitioner continues that one of ordinary skill in the art
`would have known how to combine the driving circuit of Figure 9 with the
`sense amplifier configuration of Figure 1B because driving transistor Q110
`in Figure 9 drives latch node LAP, which is also the latch node that is driven
`by the “plurality of driving transistors Q11–Q1N” in Figure 1B. Id. at 18
`(Ex. 1002 ¶ 80; Ex. 1005, 4:13–23, 29:21–29, Figs. 1B, 9). Petitioner argues
`one of ordinarily skill would have been motivated to combine the teachings
`
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`of Figures 1B and 9 in order to solve some of the problems associated with
`conventional driving circuits, and to allow for stable and rapid operation. Id.
`at 20 (Ex. 1002 ¶ 81). Petitioner also identifies the node LAP as supplying
`current and power to the sense amplifiers. Id. at 22 (Ex. 1002 ¶ 84).
`With respect to the placing step of claim 14, Petitioner asserts that
`Min discloses turning on the driving transistor Q110, which was previously
`off, as illustrated in Figure 9, demonstrating that the transistor can be turned
`off using a low voltage level. Id. at 22–24 (Ex. 1002 ¶¶ 85–86). With
`respect to the coupling step of claim 14, Petitioner asserts that Min discloses
`that each sense amplifier SA1–SAn in Figure 1B is coupled to a pair of bit
`lines BLL and BLR. Id. at 24 (citing Ex. 1005, 2:8–13, Fig. 1B). Petitioner
`further asserts that one of ordinary skill in the art would have understood
`that the nodes at which the bit lines are coupled to the sense amplifiers are
`“latch nodes.” Id. at 25 (Ex. 1002 ¶ 88).
`With respect to the supplying step of claim 14, Petitioner asserts that
`Min discloses that signal “ϕSP1 is set to have a high level,” which turns on
`NMOS transistor Q112. Id. at 26 (citing Ex. 1005, 28:21–27, 29:21–24,
`Fig. 9; Ex. 1002 ¶ 91). Thereafter, transistor Q112 starts conducting current,
`and because NMOS transistor Q113 is a “constant current source” as a result
`of the voltage Vbias applied to its gate, Q113 is also on, and current IP1
`flows through Q112 and Q113 to VSS as shown in Figure 9. Id. Petitioner
`further asserts that a person of ordinary skill in the art would have
`understood from the disclosure of Min that the resistance of transistor Q112
`is a “first impedance” and that the current IP1 and thus the flow of electrons
`through that transistor flows through that resistance. Id. at 28–29 (citing
`Ex. 1002 ¶ 97).
`
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`With respect to supplying charge after a delay in claim 14, Petitioner
`focuses on the situation in Min where signal ϕSP1 is set to have a high level
`and transistor Q112 turns on. See id. at 29. Petitioner asserts that, after a
`certain period of time with ϕSP1 set high, “the second active restore enable
`signal ϕSP2 goes to a high level, and the transistor Q115” is turned on,
`meaning transistor Q115 is delayed for a certain period of time after
`transistor Q112 turns on. Id. at 29 (citing Ex. 1005, 29:21–34, Fig. 9;
`Ex. 1002 ¶ 98). Petitioner further asserts that a person of ordinary skill in
`the art would have understood from the disclosure of Min that the resistance
`of transistor Q115 is a “second impedance” and that the current IP2 and thus
`the flow of electrons through that transistor flows through that resistance.
`Id. at 31–32 (citing Ex. 1002 ¶¶ 100–102; Ex. 1005, Fig. 9).
`We have reviewed Petitioner’s arguments and the underlying evidence
`cited in support and are persuaded Petitioner sufficiently establishes that
`Petitioner’s proposed modification of Min teaches all of the limitations of
`claim 14 and that Petitioner has provided a sufficient rationale to modify
`Min to account for all the limitations of claim 14. Thus, we determine
`Petitioner has shown by a preponderance of the evidence that claim 14 is
`rendered obvious over Min.
`Dependent Claim 15
`3.
`With respect to claim 15, which depends from independent claim 14,
`
`Petitioner argues that Min discloses a “first rate” through current IP1 and
`“second rate” through current IP2, and that Figure 9 of Min illustrates that
`“the first current mirror circuit is activated first and is arranged to provide a
`smaller current than that of the second current mirror circuit which is
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`activated later.” Id. at 34–35 (citing Ex. 1005, 27:31–34, 28:10–14, 32:31–
`35, Fig. 9; Ex. 1002 ¶¶ 105–106).
`We have reviewed Petitioner’s arguments and the underlying evidence
`cited in support and are persuaded Petitioner sufficiently establishes that
`Min teaches all of the limitations of claim 15 and that the proffered rationale
`for modification of Min is sufficient, as discussed above. Thus, we
`determine Petitioner has shown by a preponderance of the evidence that
`claim 15 is rendered obvious over Min.
`
`D. Obviousness Ground Based on Min and Seo
`Petitioner contends claims 1–5 and 10–12 as obvious over Min and
`Seo. Pet. 35–73. We begin with a review of Seo and then address
`Petitioner’s contentions.
`Seo
`1.
`Seo relates to semiconductor memory devices, and more particularly to
`sense amplifier circuitry for sensing data from memory cells. Ex. 1004, 1:7–
`8. Figure 5 of Seo is reproduced below:
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`Figure 5 illustrates the circuitry of a sense amplifier driver according to one
`embodiment. Id. at 3:22–23.
`Sensing clock driver 10 generates a signal at node LAG that drives the
`gate of the NMOS transistor Ts to a high value, which turns on transistor Ts
`and connects sense amplifier 40 to Vss. Id. at 5:55–58, 7:4–10. Seo
`discloses that “[i]f a sensing enable state is established by the equalization
`control clock Qeq being at the Vss level and the sensing clock signal Qs
`being at the Vcc level, then node ‘d’ of sensing clock driver 10 [falls] to Vss
`level immediately owing to the function of n-channel MOS transistor Th of
`inverter IV10,” causing transistor Te to immediately turn on. Id. at 6:56–63.
`Seo continues that transistor Ts is not turned on completely because
`transistor Te has a small current driving capability and is unable to pull up
`signal LAG immediately to the Vcc level to completely turn on transistor Ts.
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`Id. at 6:63–66. Thereafter, node “e” is lowered to Vss level after having
`been delayed for a certain period due to resistor R3 of inverter IV10 and
`transistor Td turns on. Id. at 6:67–7:4. “Therefore, the potential of node
`LAG raises to Vcc level with a multi-slope characteristics, so that it can
`completely turn on the n-channel MOS sense transistor Ts.” Id. at 7:4–7.
`The resultant sensing signal LAB of the Vss level carries out the sensing
`operation for the data stored in the memory cell. Id. at 7:7–10. This process
`is also illustrated in Figure 6 of Seo, with Petitioner’s annotations,
`reproduced below:
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`See Pet. 13; Ex. 1002 ¶ 56. Figure 6 provides a timing chart illustrating the
`operations of the circuit. Id. at 3:24–26.
`Independent claim 10
`2.
`Following the order of the Petition, we first discuss claim 10, and then
`claim 1. Claim 1 is directed to a memory device, whereas claim 10 is
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`directed to a sense amplifier clock driver circuit, which makes up a portion
`of an integrated circuit memory. As such, the discussion of the limitations
`of claim 10 simplifies the discussion with respect to claim 1.
`Petitioner asserts that Min’s transistor Q110 drives a plurality of sense
`amplifiers, and that Figure 9 of Min illustrates that the driving circuit that
`controls “the current Icca flowing through the driver transistor Q110,” which
`controls the voltage at node LAP. Pet. 35–36 (citing Ex. 1005, 27:22–30,
`29:15–30:3, Fig. 9; Ex. 1002 ¶¶ 108–109). Petitioner argues that a person of
`ordinary skill in the art would have understood that the timing of the rise and
`fall of the gate voltage of Q110 corresponds to the rise and fall of ϕEN, which
`Min discloses is a “driving control clock.” Id. at 37–38 (citing Ex. 1005,
`1:4–9, 12:12–13; Ex. 1002 ¶¶ 110–112).
`Petitioner also asserts that Min discloses turning on multiple driving
`transistors to determine when sensing is to occur. Id. at 39–40 (citing
`Ex. 1005, 27:29–30, 29:18–25; Ex. 1002 ¶ 114). Petitioner also argues that
`one of ordinary skill would have understood that the circuitry for generating
`signal ϕSP1 is not shown in Figure 9 and thus considered as an “externally
`generated sense control signal.” Id. at 40 (citing Ex. 1005, Fig. 9, Ex. 1002
`¶ 115). Petitioner also asserts that Min discloses that the resistance of
`transistor Q112 has a terminal coupled to Vss through transistor Q113. Id. at
`40–41 (citing Ex. 1002 ¶ 118).
`Petitioner notes that Min’s transistor Q112 has source and drain
`terminals. Id. at 41–42 (citing Ex. 1005, Fig. 9). Petitioner asserts that, in
`order for Q112 to draw current IP1, the gate of transistor Q111, which is
`connected to the gate of Q110, has to be pulled towards Vss across the
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`source and drain terminals and through the resistance of transistor Q112. Id.
`at 42–43 (citing Ex. 1005, Fig. 9; Ex. 1002 ¶¶ 119–122).
`With respect to the delay unit element of claim 10, Petitioner asserts
`that Min and Seo account for that element. Id. at 43–47. Petitioner argues
`that there is a delay between ϕSP1 and ϕSP2 in Min, and that Min discloses the
`function of “generating a delayed sense control signal,” but that Min does
`not explicitly disclose the corresponding structure that generates the delayed
`sense control signal. Id. at 44–45 (citing Ex. 1002 ¶¶ 126–127). Petitioner
`argues that a skilled artisan would have understood that a resistance R3
`(“delay unit”), in Seo, is coupled, via node d, to the node at which Qs is
`received (“coupled to the sense control signal”). Id. at 44–46 (citing
`Ex. 1002 ¶ 128; Ex. 1005, 6:59–7:2, Fig. 5). Petitioner argues that occurs
`because when Qs is at Vcc (high), node d falls to Vss immediately. Id.
`Petitioner continues that a person of ordinary skill in the art would have
`looked to Seo to refine the teachings of Min because both references are
`directed to sense amplifiers for memory and the specific structure recited in
`Seo would have allowed for the delaying resistance to be implemented. Id.
`at 46–47 (citing Ex. 1002 ¶ 129).
`Petitioner asserts that Min discloses that the resistance of transistor
`Q115 has a terminal coupled to Vss through transistor Q116. Id. at 48
`(citing Ex. 1005, Fig. 9; Ex. 1002 ¶¶ 131–133). Petitioner also asserts that
`Min’s transistor Q115 acts as a “second switch” having source and drain
`terminals. Id. at 48–49 (citing Ex. 1005, Fig. 9; Ex. 1002 ¶¶ 134–136).
`Petitioner continues that one of ordinary skill would have understood that in
`order for Q115 to draw current IP2, it has to pull the gate of Q114 (which is
`connected to the gate of Q110) towards Vss (“to a selected logic level”)
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`through the resistance of transistor Q115 (“second impedance”). Id. at 50
`(citing Ex. 1002 ¶ 136).
`With respect to the second switch element of claim 10, Petitioner
`asserts that Min discloses that transistor Q115 (“second switch”) is
`controlled by signal ϕSP2 (“controlled by the delayed sense control signal”),
`and that the paths through Q112 and Q115 are concurrently active. Id. at
`51–53 (citing Ex. 1005, 29:29–34, Fig. 9; Ex. 1002 ¶¶ 137–140).
`We have reviewed Petitioner’s arguments and the underlying evidence
`cited in support and are persuaded Petitioner sufficiently establishes that the
`combination of Min and Seo teaches all of the limitations of claim 10, and
`that Petitioner has also provided a sufficient rationale to combine Min and
`Seo to account for all the limitations of claim 10. Thus, we determine
`Petitioner has shown by a preponderance of the evidence that claim 10 is
`rendered obvious over the combination of Min and Seo.
`Independent claim 1
`3.
`With respect to claim 1, as discussed above, Petitioner argues that one
`of ordinary skill in the art would have understood that Min’s disclosure of a
`“sense amplifier driving circuit which is suitable for use in a high density
`semiconductor memory device” is equivalent to “an integrated circuit
`memory device,” as claimed. Id. at 56 (citing Ex. 1005, 1:4–9; Ex. 1002
`¶
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