Paper 31
`Trials@uspto.gov
`571-272-7822 Entered: February 13, 2018
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`KINGSTON TECHNOLOGY COMPANY, INC.,
`Petitioner,
`
`v.
`
`POLARIS INNOVATIONS LTD.,
`Patent Owner.
`____________
`
`Case IPR2017-00116
`Patent 7,334,150 B2
`____________
`
`
`
`Before SALLY C. MEDLEY, BARBARA A. PARVIS, and
`MATTHEW R. CLEMENTS, Administrative Patent Judges.
`
`PARVIS, Administrative Patent Judge.
`
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`I. INTRODUCTION
`
`Kingston Technology Company, Inc. (“Petitioner”) filed a Petition for
`
`inter partes review of claims 1–3, 5, 6, and 8–11 (“challenged patents”) of
`
`U.S. Patent No. 7,334,150 B2 (Ex. 1001, “the ’150 Patent”). Paper 2
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`

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`IPR2017-00116
`Patent 7,334,150 B2
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`(“Pet.”). In support of its Petition, Petitioner proffers a Declaration of Dr.
`
`Vivek Subramanian. Ex. 1011. Polaris Innovations Ltd. (“Patent Owner”)
`
`filed a Preliminary Response. Paper 6 (“Prelim. Resp.”). Upon
`
`consideration of the parties’ contentions and supporting evidence, we
`
`instituted an inter partes review pursuant to 35 U.S.C. § 314, as to claims 1–
`
`3, 5, 6, and 8–11 of the ’150 Patent. Paper 9 (“Dec.”).
`
`Subsequent to institution, Patent Owner filed a Patent Owner
`
`Response (Paper 17, “PO Resp.”). In support of its Patent Owner Response,
`
`Patent Owner proffers the Declaration of Dr. Joseph Bernstein. Ex. 2019.
`
`Petitioner filed a Reply to Patent Owner’s Response (Paper 20, “Pet.
`
`Reply”). On December 6, 2017, we held an oral hearing. Paper 30 (“Tr.”).
`
`This Final Written Decision is entered pursuant to 35 U.S.C. § 318(a).
`
`For the reasons that follow, we determine that Petitioner has demonstrated
`
`by a preponderance of the evidence that claims 1–3, 5, 6, and 8–11 of the
`
`’150 Patent are unpatentable.
`
`A. Related Matters
`
`The parties state that the ’150 Patent is the subject of a pending
`
`lawsuit in the Central District of California, i.e., Polaris Innovations Ltd. v.
`
`Kingston Tech. Co., Case No. 8:16–cv-300 (C.D. Cal.),1 and the lawsuit
`
`includes assertions against Petitioner. Pet. 2; Paper 3 (Patent Owner’s
`
`Mandatory Notices), 1; Paper 16 (Patent Owner’s Supplemental Mandatory
`
`Notices).
`
`
`
`1 This lawsuit is referred to herein as the “companion district court lawsuit.”
`
`2
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`

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`IPR2017-00116
`Patent 7,334,150 B2
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`B. The ’150 Patent
`
`The ʼ150 Patent is directed to a semiconductor memory module that
`
`includes a register circuit and a clock signal regeneration circuit. Ex. 1001,
`
`1:9–16. Figure 2 is reproduced below.
`
`Figure 2 shows a top view of a clock signal regeneration circuit
`and register circuit in a common chip packing.
`
`
`
`3
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`IPR2017-00116
`Patent 7,334,150 B2
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`As shown in Figure 2 above, chip packing 11 contains clock signal
`
`regeneration circuit 12 and register circuit 13. Ex. 1001, 4:30–33.
`
`Differential clock signal input line 61 supplies clock signal Cl to common
`
`chip packing 11. Id. at 4:41–43. Line section 71 supplies command and
`
`address input signals “CA.” Id. at 4:43–45. Differential clock signal lines
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`62 from clock signal regeneration circuit 12 supply the conditioned clock
`
`signal to memory chips 4 and 4a. Id. at 4:49–53. Differential clock signal
`
`lines 63 supply the conditioned clock signal to register circuit 13. Id. at
`
`4:54–56. From register circuit 13, temporarily stored command and address
`
`signals are supplied by differential command and address signal lines 72 to
`
`memory chips 4 and 4a. Id. at 4:56–60.
`
`C. Illustrative Claim
`
`Petitioner challenges claims 1–3, 5, 6, and 8–11 of the ’150 Patent.
`
`Claim 1 is an independent claim. Claims 2, 3, 5, 6, and 8–11 depend
`
`directly from claim 1. Independent claim 1, reproduced below, is illustrative
`
`of the claimed subject matter:
`
`1. A memory module comprising:
`
`a plurality of memory chips arranged on the memory module;
`
`a plurality of bus signal lines operable to supply an incoming
`clock signal and incoming command and address signals to at
`least the memory chips;
`
`a clock signal regeneration circuit configured to generate a
`plurality of copies of the incoming clock signal and to supply
`the copies of the incoming clock signal to the memory chips,
`the copies of the incoming clock signal having a same
`frequency as the incoming clock signal; and
`
`a register circuit arrange[d] on the memory module in a common
`chip packing with the clock regeneration circuit and
`configured to receive one of the copies of the incoming clock
`
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`IPR2017-00116
`Patent 7,334,150 B2
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`signal from the clock regeneration circuit, the register circuit
`being further configured to temporarily store the incoming
`command and address signals and to generate a plurality of
`copies of the incoming command and address signals and
`supply the copies of the incoming command and address
`signals to the memory chips, the copies of the incoming
`command and address signals having a same frequency as the
`incoming command and address signals.
`
`Id. at 7:1–25.
`
`D. Instituted Grounds of Unpatentability
`
`Petitioner asserts that claims 1–3, 5, 6, and 8–11 are unpatentable
`
`based on the following grounds (Pet. 4):
`
`Reference(s)
`
`Lee2
`
`Lee and Keeth
`Dodd3
`Dodd and Keeth4
`
`Basis
`
`§ 103(a)
`
`§ 103(a)
`
`§ 103(a)
`
`§ 103(a)
`
`Challenged
`
`Claim(s)
`
`1, 2, 5, 6, and 8–10
`
`3 and 11
`
`1, 2, 5, 6, and 8–10
`
`3 and 11
`
`We instituted on all of the asserted grounds of unpatentability above. Dec.
`
`33.
`
`
`
`2 U.S. Patent No. 6,898,726 B1, issued May 24, 2005 (Ex. 1008) (“Lee”).
`3 U.S. Patent No. 6,530,006 B1, issued Mar. 4, 2003 (Ex. 1003) (“Dodd”).
`4 U.S. Patent No. 7,123,046 B2, issue Oct. 17, 2006 (Ex. 1016) (“Keeth”).
`
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`IPR2017-00116
`Patent 7,334,150 B2
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`II. DISCUSSION
`
`A. Overview
`
`A patent claim is unpatentable if the differences between the claimed
`
`subject matter and the prior art are such that the subject matter, as a whole,
`
`would have been obvious at the time the invention was made to a person
`
`having ordinary skill in the art to which said subject matter pertains.
`
`35 U.S.C. § 103(a). The question of obviousness is resolved on the basis of
`
`underlying factual determinations, including: (1) the scope and content of
`
`the prior art; (2) any differences between the claimed subject matter and the
`
`prior art; (3) the level of skill in the art; and (4) objective evidence of
`
`nonobviousness, i.e., secondary considerations. See Graham v. John Deere
`
`Co., 383 U.S. 1, 17–18 (1966). In that regard, an obviousness analysis
`
`“need not seek out precise teachings directed to the specific subject matter of
`
`the challenged claim, for a court can take account of the inferences and
`
`creative steps that a person of ordinary skill in the art would employ.” See
`
`KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007).
`
`B. Person of Ordinary Skill in the Art
`
`Petitioner proposes that a person of ordinary skill in the art had a
`
`Master’s degree in Electrical Engineering and at least 2 years’ experience
`
`working in the field of semiconductor memory design. Pet. 7 (citing Ex.
`
`1011 ¶¶ 17–19). Patent Owner counters that the person of ordinary skill in
`
`the art “would only have had a Bachelor’s degree, or the equivalent, in the
`
`art of semiconductor memory module design.” PO Resp. 4–5 (citing Ex.
`
`2019 ¶¶ 24–30).
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`IPR2017-00116
`Patent 7,334,150 B2
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`The dispute centers on Patent Owner’s contention that a person of
`
`ordinary skill would have lacked familiarity with components of memory
`
`modules and technical differences between RDIMMs and other memory
`
`modules, and further would have had ordinary creativity that “coexisted”
`
`with “his or her status” as a “junior member of the team.” Id. Patent
`
`Owner’s contention regarding the lack of familiarity of the skilled artisan
`
`with prior art teachings, e.g., technical differences between RDIMMs and
`
`other memory modules, is contrary to legal precedent that a person of
`
`ordinary skill in the art is presumed to be aware of all pertinent prior art.
`
`Standard Oil Co. v. Am. Cyanamid Co., 774 F.2d 448, 454 (Fed. Cir. 1985).
`
`Regarding the level of skill, we consider the level of skill implied by
`
`the disclosures of the prior art references. Okajima v. Bourdeau, 261 F.3d
`
`1350, 1355 (Fed. Cir. 2001) (the prior art itself can reflect the appropriate
`
`level of skill in the art). For the reasons given below, upon consideration of
`
`the Petition, the Patent Owner Response, the Petitioner’s Reply, and the
`
`evidence cited therein, we adopt Petitioner’s proposed level of skill as
`
`consistent with the evidence of record. We credit Dr. Subramanian’s
`
`testimony regarding level of skill as consistent with the evidence of record,
`
`including the disclosures of the prior art references and the level of skill
`
`implied by these disclosures. We, however, note that based on the complete
`
`trial record, our findings and conclusion would be the same under either
`
`proposal.
`
`C. Claim Construction
`
`Petitioner provides proposed constructions for certain terms. Pet. 12–
`
`17. In Patent Owner’s Preliminary Response, Patent Owner countered and
`
`presented additional contentions regarding claim construction. See, e.g.,
`
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`Patent 7,334,150 B2
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`Prelim. Resp. 4–32. In our Institution Decision, we determined that neither
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`“clock signal regeneration circuit” nor “a register . . . configured to . . .
`
`generate a plurality of copies of the incoming command and address signals”
`
`invokes § 112 ¶ 6. 5 Dec. 7–9. We further determined that no express
`
`interpretation was necessary of these phrases. Id. We also were not
`
`persuaded that Petitioner should be held to previous arguments in the
`
`companion district court lawsuit that claim 6 is indefinite. Id. at 9. The
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`parties do not challenge the determinations in the Institution Decision. See
`
`e.g., PO Resp 43–62; Pet. Reply 14–22. Based on the entire trial record
`
`before us, we see no need to change these determinations.
`
`In our Institution Decision, we also made determinations regarding the
`
`terms “having a same frequency” and “RDIMM.” Id. at 10–12. Patent
`
`Owner’s disputes in its Patent Owner Response implicitly pertain to the
`
`construction of these terms, so we provide further analysis regarding
`
`construction of these terms below.
`
`1. “having a same frequency”
`
`In the Petition, Petitioner contends that “having a same frequency”
`
`means “with no intended modification from the frequency of the incoming
`
`signal.” Pet. 13–16. In the Institution Decision, we considered Patent
`
`Owner’s contention that “intended” interjects a vague term and should be
`
`
`
`5 Section 4(c) of the Leahy-Smith America Invents Act, Pub. L. No. 112–29,
`125 Stat. 284 (2011) (“AIA”) re-designated 35 U.S.C. § 112 ¶ 6, as
`35 U.S.C. § 112(f). Because the ’150 Patent has a filing date before
`September 16, 2012, the effective date of § 4(c) of the AIA, we will refer to
`the pre-AIA version of 35 U.S.C. § 112.
`
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`removed from Petitioner’s proposed construction. Dec. 10–12 (citing
`
`Prelim. Resp. 28–31).
`
`At the institution stage, we did not adopt the proposal of either party.
`
`We noted that “same frequency” is within larger phrases recited in
`
`independent claim 1. Dec. 11–12. We declined to construe the phrase
`
`“having a same frequency” such that both the generated copies and the
`
`copies supplied are required to be at the same frequency as the incoming
`
`signals. We explained that our determination was based on embodiments set
`
`forth in the ’150 Patent Specification. Id. (citing Ex. 1001, 2:57–59, 3:61–
`
`63). We further determined no other express construction of the term “same
`
`frequency” is needed to resolve a dispute between the parties.
`
`In its Patent Owner Response, Patent Owner contends “Lee’s
`
`WCLK/2 signal operates at a different frequency from WCLK, so it cannot
`
`be a ‘copy’ of the WCLK having the same frequency as WCLK, as
`
`claimed.” PO Resp. 45. Patent Owner’s contentions in its Patent Owner
`
`Response pertain to only the “signal WCLK/2” that is supplied to register
`
`45. Id. at 43–47. In particular, claim 1 recites “a register circuit arrange[d]
`
`on the memory module in a common chip packing with the clock
`
`regeneration circuit and configured to receive one of the copies of the
`
`incoming clock signal from the clock regeneration circuit.” Ex. 1001, 7:14–
`
`18 (emphases added). Patent Owner’s contentions are premised on “one of
`
`the copies of the incoming clock signal” having antecedent basis in “the
`
`copies of the incoming clock signal having a same frequency as the
`
`incoming clock signal.” Id.
`
`Petitioner contends that the “clock signal regeneration circuit”
`
`limitation requires only the copies supplied to the memory chips to “hav[e] a
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`same frequency as the incoming clock signal,” and that the omission of that
`
`language from the “register circuit” limitation indicates that the copy of the
`
`incoming clock signal that the register circuit is configured to receive need
`
`not have the same frequency as the incoming clock signal. Reply 15–16.
`
`According to Petitioner, “each and every one of the ‘same frequency’ copies
`
`that are generated by the clock signal regeneration circuit are supplied to the
`
`memory chips.” Reply 15; Pet. 43–48. Petitioner further contends that “the
`
`register simply needs to be ‘configured to,’ i.e., able to receive a copy of the
`
`clock signal” and, “[a]s long as the register is so configured, the claim
`
`limitation is met regardless of whether the copy of incoming signal sent to
`
`the register has the same frequency or not.” Reply 16–17.
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`Upon consideration, consistent with Petitioner’s proposal, we are
`
`persuaded that the “the copies of the incoming clock signal” that the clock
`
`signal regeneration circuit is “configured . . . to supply . . . to the memory
`
`chips” must have the same frequency as the incoming clock signal. We are
`
`not persuaded that the “one of the copies” that the register circuit is
`
`configured to receive must have the same frequency as the incoming clock
`
`signal as argued by the Patent Owner. Our determination is consistent with
`
`the express recitations in claim 1 and the intrinsic evidence. For instance,
`
`the recitation of “having a same frequency” in claim 1 immediately follows
`
`the supply of signals to the memory chips.
`
`a clock signal regeneration circuit configured to generate a
`plurality of copies of the incoming clock signal and to supply
`the copies of the incoming clock signal to the memory chips,
`the copies of the incoming clock signal having a same
`frequency as the incoming clock signal; and
`
`a register circuit arrange[d] on the memory module in a common
`chip packing with the clock regeneration circuit and
`
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`IPR2017-00116
`Patent 7,334,150 B2
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`configured to receive one of the copies of the incoming clock
`signal from the clock regeneration circuit, the register circuit
`being further configured to temporarily store the incoming
`command and address signals and to generate a plurality of
`copies of the incoming command and address signals and
`supply the copies of the incoming command and address
`signals to the memory chips, the copies of the incoming
`command and address signals having a same frequency as the
`incoming command and address signals.
`
`Ex. 1001, 7:8–25 (emphases added).
`
`Importantly, if we were to adopt Patent Owner’s proposal, then the
`
`claim would require “one of the copies of the incoming clock signal from the
`
`clock regeneration circuit” received by the register circuit also be supplied to
`
`at least one of the memory chips. Upon consideration of the contentions of
`
`both parties, we are not persuaded that such an interpretation is consistent
`
`with the express language of claim 1 or the intrinsic evidence, including the
`
`’150 Patent Specification.
`
`Furthermore, based on the entire trial record, the intrinsic evidence,
`
`including the ’150 Patent Specification, supports that the “one of the copies
`
`of the incoming clock signal from the clock regeneration circuit” need not
`
`have the same frequency as the incoming clock signal. Petitioner contends
`
`(Pet. 13–15) and Patent Owner does not dispute (Prelim. Resp. 28–31; PO
`
`Resp. 43–47) that the phrase “having the same frequency” did not appear in
`
`the Specification or claims as filed, but was added by amendment. Neither
`
`party points us to disclosure in the ’150 Patent Specification requiring that
`
`“having the same frequency” pertains to “one of the copies of the incoming
`
`clock signal from the clock regeneration circuit.”
`
`Additionally, as we explained in the Institution Decision (Dec. 11–
`
`12), in embodiments set forth in the ’150 Patent Specification, including a
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`preferred embodiment, “[t]he register and clock signal regeneration circuits
`
`are, preferably, designed such that they each multiply the clock signal and
`
`the command and address signal by a factor of 1:2” (Ex. 1001, 3:61–63)
`
`such that “several” copies “can be provided to several DRAM branches or
`
`channels” (id. at 2:57–59 (emphasis added).) Additionally, the Detailed
`
`Description of the ’150 Patent also describes multiplying these signals so as
`
`to supply chip-groups.
`
`[I]ncoming clock signal C1 is conditioned and the incoming
`command and address signals CA are temporarily stored in order
`to multiply these signals by a factor of 1:X and to supply the
`conditioned clock signal C1 and the temporarily stored
`command and address signals CA to X semiconductor memory
`chip groups that are arranged on the semiconductor memory
`module.
`
`Ex. 1001, 5:67–6:6 (emphasis added).
`
`Relying on the testimony of Dr. Bernstein and Dr. Subramanian,
`
`Patent Owner contends “when the ’150 Patent states that signals are
`
`‘multiplied,’ a POSITA would understand that to mean that copies of the
`
`signal are made.” PO Resp. 15 n.3 (citing Ex. 2019 ¶ 65), 45 (citing Ex.
`
`1011 ¶ 23; Ex. 2019 ¶ 66). More specifically, Dr. Bernstein testifies
`
`The ’150 Patent makes numerous references to multiplying a
`signal by a factor of 1:X. See id. at 2:46, 2:47–51, 2:58, 6:19,
`6:31. As one of ordinary skill in the art, I understand this
`terminology to mean that the signal is copied “X” number of
`times. This is clear given the overall focus of the ‘150 Patent on
`avoiding sending multiple copies of the CA signal. “Since the
`CA signals are multiplied by a factor of 1:X, several CA copies
`can be provided to several DRAM branches or channels.” Id. at
`2:57–59. The ’150 Patent also uses this convention and fills in
`the “X” with the number “2” to describe an embodiment where
`two copies of signals are generated. See id. at 5:28–38
`(describing Figure 3 illustrating two copies of by the CA line and
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`the CL line). The fact that this terminology is referring to
`copying the incoming signal is made most evident by the
`statement that the register stores the CA signals “in order to
`multiply these signals by a factor of 1:X and to supply the
`conditioned clock signal Cl and the temporarily stored command
`and address signals CA to X semiconductor memory chip groups
`arranged on the semiconductor memory module.” Id. at 6:2–6.
`This confirms that “X” in this notation means the number of
`copies that need to be made in order to send the signal to “X”
`groups of semiconductor chips. To be clear I find no suggestion
`that 1:X refers to multiplying the frequency of the signal X.
`
`Ex. 2019 ¶ 66.6
`
`As set forth above, Dr. Bernstein testifies that the ’150 Patent
`
`Specification describes multiplying signals, which means that the signals are
`
`copied, so as to supply signals to “several DRAM branches or channels” or
`
`“to supply the conditioned clock signal Cl and the temporarily stored
`
`command and address signals CA to X semiconductor memory chip groups
`
`arranged on the semiconductor memory module.” Id. (citing Ex. 1001,
`
`2:57–59, 6:2–6). These embodiments (id.), however, are consistent with
`
`Petitioner’s contentions regarding the scope of claim 1 (Reply 15; Pet. 43–
`
`48). Patent Owner does not point us to testimony of Dr. Bernstein indicating
`
`that claim 1 does not encompass these embodiments. Dr. Bernstein’s
`
`testimony regarding finding “no suggestion that 1:X refers to multiplying the
`
`
`
`6 Patent Owner includes only cursory statements and a citation to this
`testimony by Dr. Bernstein. See PO Resp. 15 n.3 (citing Ex. 2019 ¶ 65), 45
`(citing Ex. 1011 ¶ 23; Ex. 2019 ¶ 66 (“Dr. Subramanian and Dr. Bernstein
`agree that when the ’150 Patent states that signals are “multiplied,” a
`POSITA would understand that to mean that copies of the signals are
`made.”) The Patent Owner Response must include “a detailed explanation
`of the significance of the evidence.” See 37 C.F.R. §§ 42.22, 42.23, 42.120.
`Such detailed explanation is not provided.
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`frequency of the signal” immediately follows and pertains to his testimony
`
`regarding sending or supplying signals “to ‘X’ groups of semiconductor
`
`chips.” Ex. 2019 ¶ 66. We find Dr. Bernstein’s testimony consistent with
`
`our determination in the Institution Decision that only “the copies of the
`
`incoming clock signal” that the clock signal regeneration circuit is
`
`“configured . . . to supply . . . to the memory chips” must have the same
`
`frequency as the incoming clock signal.
`
`Patent Owner also relies on the declaration testimony and deposition
`
`testimony of Dr. Subramanian. PO Resp. 43–45 (citing Ex. 1011 ¶ 23; Ex.
`
`2018, 126:1–23). We do not find either supports Patent Owner’s position.
`
`Dr. Subramanian’s deposition testimony in this regard refers to “the
`
`limitation above” and does not include further explanation. Ex. 2018,
`
`126:1–23. The limitation above recites the “clock signal regeneration circuit
`
`configured to . . . supply the copies of the incoming clock signal to the
`
`memory chips.” Ex. 1001, 7:8–18. Additionally, Dr. Subramanian’s
`
`declaration testimony is based on his analysis of the intrinsic evidence,
`
`including the ’150 Patent Specification. See, e.g., Ex. 1011 ¶¶ 23, 29, 30,
`
`72–80. As discussed further below, Dr. Subramanian discusses the intrinsic
`
`evidence and claim construction and concludes that Lee discloses the
`
`register circuit “configured to receive one of the copies of the incoming
`
`clock signal from the clock regeneration circuit.” Ex. 2018, 126:1–23.
`
`For this Decision, we discern no reason to modify our analysis or our
`
`claim construction determination set forth in the Institution Decision
`
`regarding “having a same frequency.” Based on the entire trial record, we
`
`determine that only “the copies of the incoming clock signal” that the clock
`
`signal regeneration circuit is “configured . . . to supply . . . to the memory
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`chips” must have the same frequency as the incoming clock signal. We,
`
`however, determine that the broadest reasonable interpretation of the
`
`“register circuit” limitation does not require that the “one of the copies of the
`
`incoming clock signal from the clock regeneration circuit” received by the
`
`register circuit has the same frequency as the incoming clock signal.
`
`2. “RDIMM”
`
`Petitioner contends that “RDIMM” stands for registered dual in line
`
`memory module. Pet. 17. Dr. Subramanian testifies that although “[t]he
`
`term ‘RDIMM’ appears twice” in the ’150 Patent Specification, neither of
`
`these uses “defines or limits the meaning of the term ‘RDIMM.’” Ex.
`
`1011 ¶ 31. Dr. Subramanian also testifies that a RDIMM “is ‘a Dual In-Line
`
`Memory Module that has register circuitry to buffer control signals.’”
`
`Id. ¶ 32.
`
`Patent Owner agrees that “RDIMM” stands for registered dual in line
`
`memory module and, further, agrees that RDIMM’s were known prior art
`
`devices. Prelim. Resp. 48; PO Resp. 10–14, 61. Patent Owner, however,
`
`contends “RDIMMs are a well-known commercial DIMM type, which,
`
`among other things, buffers its C/A [command and address] signals, but not
`
`its data signals.” PO Resp. 61 (citing a printout of a Dell Support webpage
`
`titled “PowerEdge: What are the different types of memory DIMMS for
`
`servers?” (Ex. 2034) (“Registered DIMM: RDIMM, buffers add, control,
`
`clock lines but does not buffer data I/O lines”)). Dr. Bernstein testifies
`
`“RDIMMs feature a design that addresses performance issues . . . by putting
`
`a register between the memory controller and the memory devices on only
`
`the command/address line.” Ex. 2019 ¶ 55 (emphasis added). Additionally,
`
`Patent Owner points to Dr. Subramanian’s testimony that traditionally a
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`fully buffered DIMM provides buffering for control signals and data signals.
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`PO Resp. 12 (citing Ex. 2018, 19:7–11).
`
`As an initial matter, a Web Page from Dell’s Web Site with a print
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`date of July 10, 2017, and a last modified date of May 31, 2017, is less
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`probative than a definition or usage contemporaneous with the filing date of
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`December 3, 2004 of the ’150 Patent. Ex. 2034. Regarding the declaration
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`and deposition testimony identified by the parties (Ex. 1011 ¶¶ 31–32; Ex.
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`2019 ¶ 55; Ex. 2018, 19:7–11), we need not make a determination regarding
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`the broadest reasonable interpretation of RDIMM because based on the
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`entire trial record, for the reasons set forth infra in Section II.D.3, we are
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`persuaded that Petitioner shows sufficiently that Lee teaches an “RDIMM”
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`even if we were to adopt Patent Owner’s proposal that RDIMM stands for
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`registered dual in line memory module, which buffers control signals, but
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`not data signals. See Wellman, Inc. v. Eastman Chem. Co., 642 F.3d 1355,
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`1361 (Fed. Cir. 2011) (“[C]laim terms need only be construed ‘to the extent
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`necessary to resolve the controversy’”) (quoting Vivid Techs., Inc. v. Am.
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`Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999)).
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`D. Obviousness over Lee alone or with Keeth
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`Petitioner contends claims 1, 2, 5, 6, and 8–10 are unpatentable under
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`35 U.S.C. § 103(a) as obvious over Lee. Pet. 41–52. Petitioner also
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`contends that claims 3 and 11 are unpatentable under 35 U.S.C. § 103(a) as
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`obvious over Lee and Keeth. Pet. 52–54.
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`1. Overview of Lee
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`Lee is directed to a method for transmitting a command signal and an
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`address signal, which includes buffering and then transmitting in response to
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`a clock signal and a select signal. Ex. 1007, Abstract. Figure 4 is
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`reproduced below.
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`Figure 4 illustrates Memory Subsystem 27
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`As shown in Figure 4 above, memory subsystem 27 includes write
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`clock (WCLK) regeneration circuit 41, which is a phase lock loop (PLL) and
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`provides WCLK (0) to WCLK (8) signals to each of individual DRAM
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`memory devices 39. Id. at 7:26–30. Memory subsystem 27 also includes
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`register 45, which receives a WCLK/2 signal from WCLK regeneration
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`circuit 41 and command and address data (C/A). Id. at 7:34–41.
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`2. Overview of Keeth
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`Keeth is directed to adaptively adjusting a transition threshold of a
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`data receiver using differential clock signals and a reference voltage. Ex.
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`1016, Abstract. According to Keeth, Double Data Rate Dynamic Random
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`Access Memory (DDR DRAM) devices use differential signaling for clock
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`signals at clock pins of a device package. Id. at 1:22–30. DDR DRAM
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`devices use non-differential signaling for data signals input on the device
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`data pins. Id. at 1:35–37.
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`3. Discussion of Claim 1
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`a. The Petition—Claim 1
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`We begin our analysis with independent claim 1. Claim 1 is directed
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`to a memory module comprising memory chips and bus lines operable to
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`supply incoming clock and command and address signals to the memory
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`chips. Ex. 1001, 7:1–7. Petitioner points to teachings relating to memory
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`module 27. Pet. 41–48 (citing Ex. 1008, Fig. 4; Ex. 1011 ¶¶ 69–71).
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`Consistent with Petitioner’s contentions (id.), Lee teaches that memory
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`module 27 comprises memory chips 39 and bus lines (Ex. 1008, Figs. 1, 3,
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`4). Dr. Subramanian testifies that Lee’s memory module 27 has a plurality
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`of bus signal lines to supply incoming clock signal (WCLK) and incoming
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`command and address signals (C/A) to memory chips 39. Ex. 1011 ¶ 71.
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`We are persuaded by Petitioner’s showing and credit Dr. Subramanian’s
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`testimony (Pet. 41–48; Ex. 1011 ¶¶ 69–71), for example, because in Lee’s
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`memory system, 9 buses send signals, e.g., command and address signals
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`and clock signals, to a plurality of memory modules 27 (Ex. 1008, 4:1–14,
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`Figs. 1, 4). Each memory module 27 may be implemented as a DIMM. Id.
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`at 6:6–21, 7:26–27. These contentions are not contested by Patent Owner.
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`PO Resp. 43–56.
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`Claim 1 also recites “a clock signal regeneration circuit configured to
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`generate a plurality of copies of the incoming clock signal and to supply the
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`copies of the incoming clock signal to the memory chips, the copies of the
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`incoming clock signal having the same frequency as the incoming clock
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`signal.” Ex. 1001, 7:8–13. Relying on the testimony of Dr. Subramanian,
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`Petitioner contends that Lee’s PLL 41 of memory module 27 generates a
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`plurality of copies of incoming clock signal CLK, i.e., WCLK (1–8), and
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`supplies the copies to memory chips 39. Pet. 43 (citing Ex. 1008, 6:51–55;
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`Fig. 4; Ex. 1011 ¶¶ 72–73). We are persuaded by Petitioner’s showing and
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`credit Dr. Subramanian’s testimony (id.) that Lee’s clock signal regeneration
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`circuit (PLL 41) generates a plurality of copies of the incoming clock signal
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`and supplies the copies of the incoming clock signal to the memory chips
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`because Petitioner’s showing and Dr. Subramanian’s testimony are
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`consistent with Lee’s teachings (see, e.g., Ex. 1008, Fig. 4). Patent Owner
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`does not dispute Petitioner’s contentions that Lee’s clock signal regeneration
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`circuit (PLL 41) generates a plurality of copies of the incoming clock signal
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`and supplies the copies of the incoming clock signal to the memory chips.
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`PO Resp. 43–56.
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`Regarding the remainder of the recitation, i.e., “the copies of the
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`incoming clock signal having a same frequency as the incoming clock
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`signal” (Ex. 1001, 7:11–12), we discuss this recitation in connection with the
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`next recitation of “a register circuit” that is
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`configured to temporarily store the incoming command and
`address signals and to generate a plurality of copies of the
`incoming command and address signals and supply the copies of
`the incoming command and address signals to the memory chips,
`the copies of the incoming command and address signals having
`a same frequency as the incoming command and address signals.
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`Id. at 7:18–25.
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`As discussed supra Section II.C.1 with respect to claim construction,
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`in each of these phrases, we determine that the “copies of the incoming
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`command and address signals” that the register circuit is “configured . . . to
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`generate . . . and supply . . . to the memory chips” must have the same
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`frequency as the incoming signal. We, however, are not persuaded that the
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`“one of the copies of the incoming clock signal from the clock regeneration
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`circuit” must have the same frequency as the incoming clock signal.
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`Notwithstanding Patent Owner’s contentions regarding this limitation,
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`discussed further below, we are persuaded by Petitioner’s showing and
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`credit Dr. Subramanian’s testimony that Lee teaches (1) the clock signal
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`regeneration circuit supplying copies of the incoming clock signal having a
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`same frequency as the incoming signals; and (2) the register circuit
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`supplying copies of the command and address signal having the same
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`frequency as the incoming command and address signals. Pet. 43, 46–48
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`(citing Ex. 1008, 6:51–55, 7:35–42, 11:29–37, Fig. 4; Ex. 1003, Fig. 1; Ex.
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`1011 ¶¶ 73, 79–80). We are persuaded by Petitioner’s showing an