Trials@uspto.gov
`571-272-7822
`
`
`Paper 14
`Entered: May 24, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`NETAPP, INC.,
`Petitioner,
`
`v.
`
`INTELLECTUAL VENTURES II, LLC,
`Patent Owner.
`____________
`
`Case IPR2017-00276
`Patent 6,633,945 B1
`____________
`
`
`Before JEFFREY S. SMITH, JENNIFER S. BISK, and BEVERLY M.
`BUNTING, Administrative Patent Judges.
`
`SMITH, Administrative Patent Judge.
`
`
`
`
`
`
`
`DECISION
`Instituting Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`571-272-7822
`
`
`Paper 14
`Entered: May 24, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`NETAPP, INC.,
`Petitioner,
`
`v.
`
`INTELLECTUAL VENTURES II, LLC,
`Patent Owner.
`____________
`
`Case IPR2017-00276
`Patent 6,633,945 B1
`____________
`
`
`Before JEFFREY S. SMITH, JENNIFER S. BISK, and BEVERLY M.
`BUNTING, Administrative Patent Judges.
`
`SMITH, Administrative Patent Judge.
`
`
`
`
`
`
`
`DECISION
`Instituting Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`
`IPR2017-00276
`Patent 6,633,945 B1
`
`
`I. INTRODUCTION
`Petitioner filed a Petition1 for inter partes review of claims 1 and 6 of
`U.S. Patent No. 6,633,945 B1 (Ex. 1001, “the ’945 patent”). Paper 13
`(“Pet.”). Patent Owner filed a Preliminary Response. Paper 8 (“Prelim.
`Resp.”). By statute, institution of an inter partes review may not be
`authorized “unless . . . the information presented in the petition . . . and any
`response . . . shows that there is a reasonable likelihood that the petitioner
`would prevail with respect to at least 1 of the claims challenged in the
`petition.” 35 U.S.C. § 314(a); see also 37 C.F.R. § 42.108.
`Upon consideration of the Petition and the Preliminary Response, we
`are persuaded Petitioner has demonstrated a reasonable likelihood that it
`would prevail in establishing the unpatentability of claims 1 and 6 of the
`’945 patent. Accordingly, we institute an inter partes review of claims 1 and
`6 based on the grounds identified in the Order section of this decision.
`
`
`A. Related Matters
`Both parties identify that the ’945 patent was asserted against NetApp
`Inc. in Intellectual Ventures I, LLC v. NetApp Inc., Case No. 1:16-cv-10868-
`IT (D. Mass.), filed May 11, 2016. Pet. 17; Paper 4.
`
`
`B. The ’945 Patent
`The ’945 patent relates generally to a fully connected multiple flow
`control unit (FCU) based architecture to reduce memory read latencies. Ex.
`
`
`1 Petitioner filed an Original Petition on Nov. 18, 2016 (Paper 1), and a
`Corrected Petition on May 8, 2017 (Paper 13). In this Decision we cite to
`the Corrected Petition.
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`1001, 1:66–2:1. A symmetric multiprocessor system includes a switch
`matrix for data transfers that provides multiple concurrent buses that enable
`increased bandwidth between processors and shared memory. Ex. 1001,
`Abstract. A high-speed point-to-point channel couples command initiators
`and memory with the switch matrix and with input/output (I/O) subsystems.
`Id. Figure 2 of the ’945 patent is reproduced below.
`
`
`
`Figure 2, above, shows a symmetric shared-memory multiprocessor
`system using a switched-fabric data path architecture centered on FCU 220.
`Ex. 1001, 2:59–62. Point-to-point (PP) interconnections 112, 113, and 114
`provide channel interfaces between FCU 220 and dual CPU interface units
`(DCIUs) 210, memory control units (MCUs) 230, and bus bridge units
`(BBUs) 240, respectively. Id. at 2:67–3:8, 3:11–15.
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`Figure 12 of the ’945 patent is reproduced below.
`
`
`
`Figure 12, above, shows fully connected multiple FCU architectures.
`Id. at 6:22–23, 6:62–7:57. The interconnections between FCUs are point-to-
`point. Id. at 7:14–15. Each FCU has direction connection to all other FCUs
`and maintains cache coherency for transactions that belong to its memory
`region via the point-to-point interconnections. Id. at 7:15–21.
`
`
`C. Illustrative Claim
`Challenged claims 1 and 6 of the ’945 patent are independent. Claim
`1 is illustrative of the claimed subject matter:
`1. A multi-processor shared memory system comprising:
`a first set of point-to-point connections;
`a first set of processors each coupled to one of the first set
`of point-to-point connections;
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`a first memory coupled to one of the first set of point-to-
`point connections;
`a first flow control unit including a first data switch
`coupled to the first set of point-to-point connections wherein the
`first data switch is configured to interconnect the first set of
`point-to-point connections to provide first data paths between the
`first memory and the first set of processors;
`a second set of point-to-point connections;
`a second set of processors each coupled to one of the
`second set of point-to-point connections;
`a second memory coupled to one of the second set of
`point-to-point connections;
`a second flow control unit including a second data switch
`coupled to the second set of point-to-point connections wherein
`the second data switch is configured to interconnect the second
`set of point-to-point connections to provide second data paths
`between the second memory and the second set of processors;
`and
`
`a third point-to-point connection coupled to the first data
`switch and to the second data switch wherein the first data switch
`is configured to interconnect the first set of point-to-point
`connections to the third point-to-point connection and the second
`data switch is configured to interconnect the second set of point-
`to-point connections to the third point-to-point connection to
`provide third data paths between the second memory and the first
`set of processors and between the first memory and the second
`set of processors.
`Ex. 1001, 9:2–36.
`
`
`D. References
`Petitioner relies on the following references. Pet. 25.
`Reference Patent No.
`Date
`Sharma
`US 6,055,605
`Apr. 25, 2000
`
`Ex. No.
` 1002
`
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`Reference Patent No.
`Ekanadham US 6,085,295
`Hagersten US 5,754,877
`
`
`Date
`Jul. 4, 2000
`May 19, 1998
`
`Ex. No.
` 1003
` 1004
`
`E. Asserted Grounds of Unpatentability
`Petitioner contends that claims 1 and 6 of the ’945 patent are
`
`unpatentable based on the following specific grounds.2,3 Pet. 25.
`
`References
`Ekanadham and Hagersten
`Ekanadham
`Sharma and Hagersten
`Sharma
`
`
`Basis
`§ 103(a)
`§ 103(a)
`§ 103(a)
`§ 103(a)
`
`Challenged Claims
`1 and 6
`1 and 6
`1 and 6
`1 and 6
`
`II. ANALYSIS
`A. Claim Construction
`On February 14, 2017, we granted Patent Owner’s Motion for district
`court type claim construction under 37 C.F.R. § 42.100(b). Paper 7. The
`Board interprets claims of an expired patent using the principles set forth in
`Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc). See 37
`C.F.R. § 42.5(b); see also In re Rambus Inc., 694 F.3d 42, 46 (Fed. Cir.
`
`
`2 Patent Owner argues that Petitioner “mislabels and mixes the proposed
`grounds.” Prelim. Resp. 5. We disagree, and address each proposed ground
`based on Petitioner’s suggested combination as discussed in Section II.
`3 Patent Owner argues that the Board should institute trial on only one
`ground, because the other grounds are redundant. Prelim. Resp. 30–31.
`However, denying institution because of redundancy is discretionary. Here,
`we are not persuaded that institution of the alleged “redundant” grounds
`would place a significant burden on Patent Owner and the Board, or would
`cause unnecessary delays.
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`2012) (“While claims are generally given their broadest possible scope
`during prosecution, the Board’s review of the claims of an expired patent is
`similar to that of a district court’s review.”) (internal citation omitted)
`(“Phillips” standard). Under this approach, claim terms are given their
`ordinary and customary meaning, as would be understood by a person of
`ordinary skill in the art, at the time of the invention, in light of the language
`of the claims, the specification, and the prosecution history of record.
`Phillips, 415 F.3d at 1313.
`Petitioner proposes construction of the claim term “point-to-point
`connection” as encompassing a statically configured communications link
`between two devices. Pet. 20–25. Patent Owner contends that the plain and
`ordinary meaning of this claim term is clear, and that construction is not
`necessary to resolve the controversy in this proceeding. Prelim. Resp. 5.
`Moreover, Patent Owner does not propose that any other term requires
`construction. See generally Prelim. Resp. 4–5.
`For purposes of this decision, we determine no terms need an explicit
`construction to resolve a controversy at this preliminary stage. See Vivid
`Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999)
`(only those terms which are in controversy need to be construed and only to
`the extent necessary to resolve the controversy).
`
`B. Asserted Obviousness Over Ekanadham and Hagersten:
`Claims 1 and 6
`Petitioner, relying on the Declaration of Mr. Ian Jestice (Ex. 1006),
`challenges claims 1 and 6 as obvious over the combination of Ekanadham
`and Hagersten. Pet. 25–49.
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`1. Ekanadham (Ex. 1003)
`Ekanadham relates to providing cache coherence in a shared memory
`system composed of a network of multiprocessor nodes. Ex. 1003, 1:9–11;
`2:48–50. Figure 3a of Ekanadham is reproduced below.
`
`
`
`
`Figure 3a, above, shows two symmetric multiprocessor (SMP) nodes,
`where each node includes a plurality of processors P1 through Pn, memory
`modules M1 through Mn, and adapter A, interconnected to each other
`through a switch. Id. at 3:37–43. The nodes are connected to each other
`through a network. Id. at 3:43–45. All communications between the
`processors, memories, and adapters are made point-to-point without the need
`for broadcasts within the SMP node. Id. at 2:14–16.
`When a cache line needs to be invalidated, an adapter at the local node
`consults its node list for the line to determine which remote nodes to forward
`the invalidations to, and sends a message to all such nodes. Id. at 2:52–57,
`4:52–60, 8:39–43. The adapter at the remote node consults its local
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`processor list and issues invalidation commands over the switch to each of
`the processors on the list. Id. at 2:57–61, 4:60–63.
`2. Hagersten (Ex. 1004)
`Hagersten is related to the architectural connection of multiple
`processors within a multiprocessor computer system. Ex. 1004, 1:7–9. The
`computer system includes multiple SMP nodes that are connected to each
`other by point-to-point links. Id. at Abstract. Figure 7 of Hagersten is
`reproduced below.
`
`
`
`Figure 7, above, shows an extended symmetric processor (XMP)
`system 130 with three SMP nodes 120A–C. Id. at 13:41–44. XMP interface
`128A of SMP node 120A is point-to-point connected to XMP interface
`128B of SMP node 120B by point-to-point link 142. Id. at 13:62–64. The
`point-to-point linking structure comprising point-to-point connections 140,
`142, and 144 is a transaction synchronous structure. Id. at 14:49–52. Thus,
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`each SMP node 120 may send and receive transactions at approximately the
`same time as each other SMP node 120, without running into latency
`problems or arbitration delay. Id. at 14:2–10, 52–57; 15:4–7.
`3. Analysis of Claims 1 and 6
`Petitioner contends Ekanadham teaches “a first set of point-to-point
`connections,” as recited in claim 1, in teaching that all communications
`between the processors, the memories, and the adapters are made point-to-
`point without the need for broadcasts within the SMP node. Pet. 35 (citing
`Ex. 1003, Fig. 3a, 2:14–16; Ex. 1006 ¶¶ 57–58).
`Petitioner contends that Ekanadham teaches “a first set of processors
`each coupled to one of the first set of point-to-point connections,” and “a
`first memory coupled to one of the first set of point-to-point connections,” as
`recited in claim 1, in teaching that a plurality of processors and a memory
`are connected to a local data switch via a first set of point-to-point
`connections. Id. at 35–38 (citing Ex. 1003, Fig. 3a; 2:14–16; 3:37–45; Ex.
`1006 ¶¶ 59–62).
`Petitioner contends Ekanadham teaches “a first flow control unit
`including a first data switch coupled to the first set of point-to-point
`connections wherein the first data switch is configured to interconnect the
`first set of point-to-point connections to provide first data paths between the
`first memory and the first set of processors,” as recited in claim 1, in
`teaching a switch and adapter coupled to the point-to-point connections to
`the processors and the memory. Pet. 38–40 (citing Ex. 1003, Fig. 3a; 2:14–
`16; 3:37–43; Ex. 1006 ¶¶ 63–66).
`Petitioner contends Ekanadham teaches
`a second set of point-to-point connections;
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`a second set of processors each coupled to one of the
`second set of point-to-point connections;
`a second memory coupled to one of the second set of
`point-to-point connections;
`a second flow control unit including a second data switch
`coupled to the second set of point-to-point connections wherein
`the second data switch is configured to interconnect the second
`set of point-to-point connections to provide second data paths
`between the second memory and the second set of processors
`as recited in claim 1, in teaching a second node that has identical
`components as the first node discussed above. Pet. 40–41 (citing Ex. 1006 ¶
`68).
`
`Petitioner contends Ekanadham teaches that each of the plurality of
`nodes is connected to each other through a network. Pet. 41–43 (citing Ex.
`1003, Fig. 3a; 3:43–44; 4:44–51; Ex. 1006 ¶¶ 53, 70–73).
`Petitioner contends Hagersten teaches
`a third point-to-point connection coupled to the first data
`switch and to the second data switch wherein the first data switch
`is configured to interconnect the first set of point-to-point
`connections to the third point-to-point connection and the second
`data switch is configured to interconnect the second set of point-
`to-point connections to the third point-to-point connection to
`provide third data paths between the second memory and the first
`set of processors and between the first memory and the second
`set of processors
`as recited in claim 1 in teaching SMP nodes connected to each other by
`point-to-point connections, such as SMP node 120A that is point-to-point
`connected to SMP node 120B by point-to-point link 142. Pet. 43 (citing Ex.
`1004, Abstract; Fig. 7; 13:63–64; 14:3–10; Ex. 1006 ¶ 133).
`
`Petitioner further relies on Hagersten to show the benefits of using a
`point-to-point connection to connect SMP nodes, including reduced latency,
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`separate data transmissions during the same clock cycle, and no arbitration
`delay. Pet. 43–44 (citing Ex. 1004, 14:3–10, 49–57; 15:4–7).
`On this record, Petitioner demonstrates sufficiently how the disclosure
`in Ekanadham and Hagersten satisfies the above claim elements. Patent
`Owner disputes that the cited references disclose Petitioner’s reason to
`combine, as well as the claimed third point-to-point connection. Prelim.
`Resp. 6–13.
`Petitioner relies on testimony of Mr. Jestice to contend that it would
`have been obvious to modify Ekanadham to include the point-to-point
`connection between nodes as taught by Hagersten for the benefit of reducing
`latency. Pet. 30–34, 43 (citing Ex. 1006 ¶¶ 136–1574). Mr. Jestice testifies
`that Hagersten teaches the advantages of using point-to-point connections
`between nodes, which include allowing several SMP nodes to be linked
`together without running into many of the physical constraints and latency
`problems associated with other architectures. Ex. 1006 ¶ 133 (citing Ex.
`1004, 14:3–10). Mr. Jestice also testifies that Hagersten teaches the
`advantages include separate broadcasts during the same clock cycle
`originating from each SMP node, which allows for increased utilization of
`the system and enhanced productivity. Ex. 1006 ¶ 134 (citing Ex. 1004,
`15:4–7).
`Patent Owner contends that Petitioner never discusses why a person of
`ordinary skill in the art would substitute the point-to-point connection of
`Hagersten for the network connection of Ekanadham. Prelim. Resp. 7–10.
`However, Mr. Jestice’s testimony provides persuasive evidence that one of
`
`
`4 Although Petitioner cites Ex. 1006 ¶ 39 on page 33 of the Petition, we view
`this as a clerical error and treat this as citing Ex. 1006 ¶ 139.
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`skill in the art would understand that using the point-to-point connection of
`Hagersten to connect the SMP nodes of Ekanadham provides the advantages
`of avoiding latency problems and including separate broadcasts from each
`SMP node during the same clock cycle, which increases utilization and
`productivity of the system. Ex. 1006 ¶¶ 33, 52, 133–134, 143–156.
` Patent Owner also contends that claim 1 requires the two switches
`interconnect “the third point-to-point connection” to enable bidirectional
`data paths. Prelim. Resp. 11–13. According to Patent Owner, Hagersten
`teaches unidirectional point-to-point links. Id. However, Hagersten teaches
`that point-to-point link 142 connects SMP node 120A to SMP node 120B,
`and comprises two unidirectional links. See Pet. 43 (citing Ex. 1004,
`Abstract; Fig. 7; 13:63–64; 14:3–10; Ex. 1006 ¶ 133).
`For purposes of this decision, we credit Mr. Jestice’s testimony and
`supporting evidence and determine at this stage of the proceeding that
`Petitioner has established sufficiently that the combination of Ekanadham
`and Hagersten teaches the “third point-to-point connection coupled to the
`first data switch and to the second data switch,” as recited in claim 1.
`Thus, we determine at this juncture of the proceeding that the
`explanations and supporting evidence presented by Petitioner adequately
`establishes a reasonable likelihood that the combination of Ekanadham and
`Hagersten would have rendered claim 1 obvious.
`Petitioner contends claim 6 recites limitations similar to those of claim
`1 and that the combination of Ekanadham and Hagersten would have
`rendered claim 6 obvious. See Pet. 46–49.
`Specifically, Petitioner contends Ekanadham teaches “interconnecting
`the first set of point-to-point connections in the first data switch to provide
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`first data paths between the first memory and the first set of processors,” as
`recited in claim 6 in teaching interconnecting a first set of point-to-point
`connections in a first data switch to provide first data paths between the
`memory and the first set of processors, as discussed in Petitioner’s analysis
`of claim 1. Pet. 48 (citing Ex. 1003, 2:14–16, 3:37–45, 3:49–55; Ex. 1006
`¶¶ 78–79).
`Petitioner contends Ekanadham teaches “interconnecting the second
`set of point-to-point connections in the second data switch to provide second
`data paths between the second memory and the second set of processors,” as
`recited in claim 6, in teaching interconnecting point-to-point connections in
`a second data switch to provide second data paths between the memory and
`the second set of processors, as discussed in Petitioner’s analysis of claim 1.
`Pet. 48 (citing Ex. 1003, 2:14–16, 3:37–45, 3:49–55; Ex. 1006 ¶¶ 80–81).
`Petitioner contends Hagersten teaches
`interconnecting the first set of point-to-point connections
`to the third point-to-point connection in the first data switch and
`interconnecting the second set of point-to-point connections to
`the third point-to-point connection in the second data switch to
`provide third data paths between the second memory and the first
`set of processors and between the first memory and the second
`set of processors
`as recited in claim 6, in teaching SMP nodes connected to each other by
`point-to-point connections, such as SMP node 120A that is point-to-point
`connected to SMP node 120B by point-to-point link 142, as discussed in
`Petitioner’s analysis of claim 1. Pet. 49 (citing Pet. 41–46; Ex. 1003, 2:14–
`16, 3:37–45, 3:49–55; Ex. 1006 ¶¶ 82–83).
`Patent Owner disputes that the cited references disclose the claimed
`third point-to-point connection. Prelim. Resp. 14–16. According to Patent
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`Owner, Petitioner never discusses how Hagersten relates to the recited
`interconnections formed by the respective switches between the third point-
`to-point connection and the other point-to-point connections. Prelim. Resp.
`15. However, Petitioner articulated sufficient reasoning and supporting
`evidence to adequately establish a reasonable likelihood that the
`combination of Ekanadham and Hagersten teaches the interconnections
`formed by the switches between the third point-to-point connection and the
`other point-to-point connections, as discussed in our analysis of claim 1. See
`Pet. 49 (citing Pet. 41–46; Ex. 1003, 2:14–16, 3:37–45, 3:49–55; Ex. 1006
`¶¶ 82–83).
`For purposes of this decision, we credit Mr. Jestice’s testimony and
`determine at this preliminary stage of the proceeding Petitioner has
`articulated sufficient reasoning to demonstrate a likelihood it will prevail in
`its obviousness challenge. We determine the Petition and supporting
`evidence establish a reasonable likelihood that the combination of
`Ekanadham and Hagersten would have rendered claim 6 obvious.
`
`
` C. Asserted Obviousness Over Ekanadham: Claims 1 and 6
`Petitioner argues that Ekanadham renders claims 1 and 6 obvious.
`Pet. 49–50. Petitioner contends Ekanadham teaches the third point-to-point
`connection for the reasons given in Petitioner’s analysis of claim 1. Pet. 49–
`50 (citing Pet. 41–46). In particular, Petitioner contends that Ekanadham
`teaches the third point-to-point connection in teaching that each of a
`plurality of nodes is connected to each other through a network. Pet. 41
`(citing Ex. 1003, 3:43–44). According to Petitioner, Ekanadham teaches
`that all communications between the processors, the memories, and the
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`adapters are made point-to-point without the need for broadcasts within the
`SMP node. Pet. 42 (citing Ex. 1003, 2:14–16).
`Patent Owner argues that Petitioner misinterprets the cited passage
`from Ekanadham. Prelim. Resp. 19–22. According to Patent Owner, the
`cited passage explicitly refers to point-to-point communications within the
`SMP node, not between nodes. Prelim. Resp. 20 (citing Ex. 1003, 2:14–16).
`Patent Owner contends that a more reasonable explanation is that the point-
`to-point communications of Ekanadham are within the SMP nodes, not over
`the network between nodes. Prelim. Resp. 22.
`Based on the arguments and evidence of record, we agree with Patent
`Owner that the more natural reading of “[a]ll communications between the
`processors, the memories and the adapters are made point to point without
`the need for broadcasts within the SMP node” (Ex. 1003, 2:14–16) is that the
`point-to-point communications are within the node, not between nodes over
`a network.
`We determine the Petition and supporting evidence does not
`adequately establish a reasonable likelihood that Petitioner would prevail in
`showing that Ekanadham renders claims 1 and 6 obvious.
`
`
`D. Asserted Obviousness Over Sharma and Hagersten: Claims 1 and 6
`Petitioner argues the combination of Sharma and Hagersten teaches
`the limitations of claims 1 and 6. Pet. 50–73. Patent Owner disputes that
`Sharma and Hagersten disclose the “third point-to-point connection.”
`Prelim. Resp. 24–26.
`
`
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`1. Sharma (Ex. 1002)
`Sharma relates to the efficient ordering of memory reference
`operations issued by a processor of a multiprocessor system having a shared
`cache. Ex. 1002, 1:19–21. Figure 9 of Sharma is reproduced below.
`
`Figure 9, above, is a schematic block diagram of an SMP node
`comprising plurality of processors (P) 202–208 interconnected with shared
`memory 150 and global port interface 910 via local switch 925. Ex. 1002,
`13:47–50. Figure 7 of Sharma is reproduced below.
`
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`Figure 7, above, shows a schematic block diagram of SMP system
`700 comprising SMP nodes 902–916 interconnected by hierarchical switch
`800. Ex. 1002, 12:25–28. Each node is coupled to the hierarchical switch
`by bidirectional hierarchical switch (HS) link 922–936. Ex. 1002, 12:28–32.
`2. Analysis of Claims 1 and 6
`Petitioner contends Sharma teaches “a first set of point-to-point
`connections; a first set of processors each coupled to one of the first set of
`point-to-point connections; a first memory coupled to one of the first set of
`point-to-point connections,” as recited in claim 1 in teaching a node
`including a plurality of processors interconnected with shared memory and a
`global port interface via a local switch. Pet. 57–61 (citing Ex. 1002, Fig. 3;
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`6:9–12, 8:11–13, 13:47–50; Ex. 1006 ¶¶ 88–89, 93–98).
`Petitioner contends Sharma teaches “a first flow control unit including
`a first data switch coupled to the first set of point-to-point connections
`wherein the first data switch is configured to interconnect the first set of
`point-to-point connections to provide first data paths between the first
`memory and the first set of processors” in teaching a local switch coupled to
`the set of point-to-point connections coupled to each processor and coupled
`to the point-to-point connection that is connected to the shared memory.
`Pet. 61–63 (citing Ex. 1002, Figs. 3, 9; 8:21–23; Ex. 1006 ¶¶ 99–103).
`Petitioner contends Sharma teaches
`a second set of point-to-point connections;
`a second set of processors each coupled to one of the
`second set of point-to-point connections;
`a second memory coupled to one of the second set of
`point-to-point connections;
`a second flow control unit including a second data switch
`coupled to the second set of point-to-point connections wherein the
`second data switch is configured to interconnect the second set of point-
`to-point connections to provide second data paths between the second
`memory and the second set of processors
`as recited in claim 1 in teaching a second node that has identical components
`as the first node discussed above. Pet. 63–65 (citing Ex. 1002, 12:57–65;
`Ex. 1006 ¶¶ 104–106).
`Petitioner contends Hagersten teaches
`a third point-to-point connection coupled to the first data
`switch and to the second data switch wherein the first data switch
`is configured to interconnect the first set of point-to-point
`connections to the third point-to-point connection and the second
`data switch is configured to interconnect the second set of point-
`to-point connections to the third point-to-point connection to
`provide third data paths between the second memory and the first
`
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`
`set of processors and between the first memory and the second
`set of processors
`as recited in claim 1 in teaching SMP nodes connected to each other by
`point-to-point connections, such as SMP node 120A that is point-to-point
`connected to SMP node 120B by point-to-point link 142, as explained in
`Petitioner’s previous analysis of claim 1. Pet. 69–70 (citing Pet. 41–46).
`Petitioner supports its position with the testimony of Mr. Jestice,
`namely that a person of ordinary skill in the art would have found it obvious
`to replace the hierarchical switch of Sharma with the point-to-point
`connections between nodes as taught by Hagersten for the benefit of solving
`the problem of latency in inter-node communication. Pet. 53–56 (citing Ex.
`1006 ¶¶ 158–172); Pet. 69–70 (citing Ex. 1006 ¶ 117).
`Patent Owner asserts that Petitioner never discusses why a person of
`ordinary skill in the art would replace the switch of Sharma with the point-
`to-point connection of Hagersten. Prelim. Resp. 23–24. However, Mr.
`Jestice’s testimony provides persuasive evidence, for this stage of the
`proceeding, that using the point-to-point connection of Hagersten to connect
`the SMP nodes of Sharma provides the advantage of improving speed and
`reducing the problem of latency associated with cache coherency
`maintenance. Ex. 1006 ¶¶ 159–165.
` For purposes of this decision, we credit Mr. Jestice’s testimony and
`determine at this preliminary stage of the proceeding Petitioner has
`articulated sufficient reasoning to demonstrate a likelihood it will prevail in
`its obviousness challenge, specifically, that one of skill in the art would
`modify the switch of Sharma using the point-to-point connection of
`Hagersten to solve the problem of latency in inter-node communication.
`We determine the Petition and supporting evidence establish a reasonable
`
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`likelihood that the combination of Sharma and Hagersten would have
`rendered claim 1 obvious.
`Petitioner contends claim 6 recites limitations similar to those recited
`by claim 1 and that the combination of Sharma and Hagersten would have
`rendered claim 6 obvious. See Pet. 70–73.
`In particular, Petitioner contends Sharma teaches “interconnecting the
`first set of point-to-point connections in the first data switch to provide first
`data paths between the first memory and the first set of processors,” as
`recited in claim 6 in teaching interconnecting a first set of point-to-point
`connections in a first data switch to provide first data paths between the
`memory and the first set of processors, as discussed in Petitioner’s analysis
`of claim 1. Pet. 71 (citing Ex. 1002, 4:9–13; Ex. 1006 ¶¶ 121–122).
`Petitioner contends Sharma teaches “interconnecting the second set of
`point-to-point connections in the second data switch to provide second data
`paths between the second memory and the second set of processors,” as
`recited in claim 6, in teaching interconnecting point-to-point connections in
`a second data switch to provide second data paths between the memory and
`the second set of processors, as discussed in Petitioner’s analysis of claim 1.
`Pet. 72 (citing Ex. 1002, 4:9–13, 12:57–65, Ex. 1006 ¶¶ 123–124).
`Petitioner contends Hagersten teaches
`interconnecting the first set of point-to-point connections
`to the third point-to-point connection in the first data switch and
`interconnecting the second set of point-to-point connections to
`the third point-to-point connection in the second data switch to
`provide third data paths between the second memory and the
`first set of processors and between the first memory and the
`second set of processors
`
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`IPR2017-00276
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`as recited in claim 6, in teaching SMP nodes connected to each other by
`point-to-point connections, such as SMP node 120A that is point-to-point
`connected to SMP node 120B by point-to-point link 142, as explained in
`Petitioner’s analysis of the “third point-to-point connection” of claim 1. Pet.
`72–73 (citing Pet. 41–46; Ex. 1006 ¶¶ 125–126).
`
`Patent Owner contends that Petitioner has not established that the
`combination of Sharma and Hagersten teaches the claimed third point-to-
`point connection recited in claims 1 and 6. Prelim. Resp. 24–26. Petitioner
`relies on Hagersten to teach the third point-to-point connection. Pet. 69–70
`(citing Pet. 41–46).
`For purposes of this decision, we credit Mr. Jestice’s testimony and
`determine at this preliminary stage of the proceeding Petitioner has
`articulated sufficient reasoning to demonstrate a likelihood it will prevail in
`its obviousness challenge. We determine the Petition and supporting
`evidence establish a reasonable likelihood that the combination of
`Ekanadham and Hagersten would have rendered claim 6 obvious.
`
`
`E. Asserted Obviousness Over Sharma: Claims 1 and 6
`Petitioner argues that Sharma renders claims 1 and 6 obvious. Pet.
`73–74. Petitioner contends Sharma teaches the third point-to-point
`connection for the reasons given in Petitioner’s analysis of claim 1. Id.
`(citing Pet. 65–70). In particular, Petitioner contends that Sharma teaches
`the third point-to-point connection in teaching point-to-point connections
`between the global interface of a first node, through the hierarchical switch,
`and to the global port interface of a second node. Pet. 65–70 (citing Ex.
`1002, Figs. 7, 9; 12:56–64; Ex. 1006 ¶¶ 108–117). Petitioner relies on
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`testimony of Mr. Jestice to support Petitioner’s contention that the link
`between two nodes is a third point-to-po
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