`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SK HYNIX INC., SK HYNIX AMERICAN INC.,
`SK HYNIX MEMORY SOLUTIONS INC.,
`Petitioner,
`
`v.
`
`NETLIST, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-00577
`Patent 8,516,185 B2
`____________
`
`Record of Oral Hearing
`Held: April 6, 2018
`____________
`
`
`
`
`Before BRYAN F. MOORE, MATTHEW R. CLEMENTS, and SHEILA F. McSHANE,
`Administrative Patent Judges.
`
`
`

`

`Case IPR2017-00577
`Patent 8,516,185 B2
`
`
`
`APPEARANCES:
`
`ON BEHALF OF THE PETITIONER:
`
`
`JOSEPH MICALLEF, ESQUIRE
`STEVEN S. BAIK, ESQUIRE
`WONJOO SUH, ESQUIRE
`Sidley & Austin, LLP
`1501 K Street NW
`Washington, D.C. 20005
`
`
`
`ON BEHALF OF THE PATENT OWNER:
`
`
`MEHRAN ARJOMAND, ESQUIRE
`DAVID S. KIM, ESQUIRE
`Morrison & Foerster, LLP
`707 Wilshire Boulevard
`Los Angeles, California 90017-3543
`
`
`
`
`The above-entitled matter came on for hearing on Friday, April 6, 2018,
`
`commencing at 3:30 p.m., at the U.S. Patent and Trademark Office, 600 Dulany Street,
`Alexandria, Virginia.
`
`
`
`
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`P R O C E E D I N G S
`- - - - -
`JUDGE MOORE: Okay. We're at the second, I guess you would say, oral
`hearing of the day; this specifically for IPR2017-00577. Just to remind the parties,
`because we have new counsel here, that we have judges that are remote. They're not able
`to see the Elmo and the courtroom in the way that we are here; so be sure that you do
`indicate what page in the demonstratives you're on, and also if you're pointing to a figure,
`just be clear that your description is full in words, and don't rely on people being able to
`see the figure, necessarily, to understand your descriptions.
`
`And for the new counsel, with me here are Judges Clements and McShane; so we
`should have a rollcall starting with the Petitioner.
`
`MR. MICALLEF: Thank you, Your Honor -- Joe Micallef for the Petitioner.
`With me is my partner Steve Baik and my colleagues Wonjoo Suh, and Mr. Pazmandi.
`
`JUDGE MOORE: Thank you; for Patent Owner.
`
`MR. ARJOMAND: Good afternoon, Your Honors --. Mehran Arjomand of
`Morrison & Foerster for, Patent Owner, Netlist. With me is my colleague, David Kim.
`
`JUDGE MOORE: Thank you; whenever you're ready.
`
`MR. MICALLEF[CM1]: Thank you, Your Honor. This is the 577 proceeding, it
`relates to the 185 Patent. We have a number slides; I do not intend to use them all, but I
`will go through some of them. There is one ground at issue here, Your Honor; it is a
`ground of obviousness based on Halbert in view of Amidi. There's also really only one
`claim element in play which the parties have referred to as a selectively allowed
`limitation. What I'd like to do first is very briefly do an overview of the patent and the
`prior art, and that limitation, and then move on to some other things.
`
`JUDGE MOORE: And I understand you weren't prepared -- and this maybe out
`of left field, but only because I was on it -- I know that a reset, remand came back on a
`term limitation selectively, electrically isolating which, of course, as you've mentioned, is
`not in controversy here but does exist in this case; and so, again, if you know, is there
`anything about the Fed Circuit's ruling of that limitation that would have an effect on
`what we're doing here?
`
`MR. MICALLEF: No, I don't think so. I don't think that there's been any issue
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`raised that would affect this hearing. Of course, I believe the Board has actually issued
`an opinion after that remand.
`
`JUDGE MOORE: Right. Yes, a remand opinion went out.
`
`MR. MICALLEF: I don't think that affects us here.
`
`JUDGE MOORE: Okay. And Patent Owner , do you agree, and once again, I
`understand you may not be aware of this issue and it wasn't brought up in any papers or
`anything in this, but just if you know?
`
`MR. ARJOMAND: Your Honor, I don't believe those remand decisions impact
`the hearing today. There's no load isolation in the 185 Patent.
`
`JUDGE MOORE: Right.
`
`MR. MICALLEF: Thank you, Your Honor.
`
`JUDGE MOORE: And I didn't mention, we have, I think, 30 minutes per side;
`so, do you want to reserve some time for rebuttal?
`
`MR. MICALLEF: I'd like to reserve 10 minutes, Your Honor; and perhaps more
`if I finish my presentation.
`
`JUDGE MOORE: 10 minutes, okay. Right; you'll get all the time that you have
`remaining, but I will make you aware when you are approaching your 10 minutes that
`you plan to hold.
`
`MR. MICALLEF: Great; thank you. So, the 185 Patent, Your Honor, issued
`from a patent application filed in 2010 -- it was a CIP of an application filed in 2009.
`They've claimed priority back to 2009. It states that the problem in the prior art -- there
`was a problem because of the increased number of memory devices that were being used
`that increased the resistive and capacitive load on the memory bus leading to some signal
`propagation issues. The 185 Patent proposes to solve this problem by placing a number
`of circuits in the data path between the memory devices; and the system memory
`controller refers to it variously as load reducing circuits or load reducing switching
`circuits.
`
`I'm on slide 8 of our slides, our demonstratives. In Figure 5 of the Patent there's
`sort of a blowout of these -- a diagram of one of these switching circuits; and you can see
`that in the middle of this diagram there is -- and we've highlighted in yellow -- a
`multiplexer 508, that selects between memory ranks. And we've shown on this slide just
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`sort of the selection of the data path towards and away from memory ranks a to c, and not
`memory ranks b to d and, of course, the multiplexer could select in the opposite way.
`
`Here on slide 9, I've placed what we have been referring to as the selectively
`allowed limitation and I think it's important to just stop here for a second because the
`words of the claim actually do matter, obviously; and what this claim element says is that
`each circuit of the plurality of circuits is configured to selectively allow data transmission
`between the system memory controller and at least one memory device, and then it goes
`on. But why I want to stop on it is to point out what's not in this claim language. It does
`not require a multiplexer. In fact, it does not require any specific circuitry whatsoever.
`The Patentee chose to draft this particular element of the claim in terms of generic
`circuitry -- a plurality of circuits -- configured to perform certain functionality. So, that's
`the claim language that's at issue in this proceeding right here.
`
`Now, the Board instituted on Halbert in view of Amidi -- so, let me very briefly
`talk about Halbert and Amidi. Halbert's a prior art patent 102B, issued in 2006. It
`discloses a memory module -- I'm here on slide 12. For example, in Figure 7 of Halbert
`shown on this slide, a number of memory devices 140, a plurality of interfaced circuits
`here -- left interface circuit 125 and R interface circuit 130 in the data path -- controlling
`communication with these memory devices. Halbert also has a blowout of his interface
`circuits -- this is slide 13, and here we've annotated Figure 4 of Halbert -- and you can see
`in this fit circuit, again in the middle, there is a multiplexer which selects between either
`the path to the upper rank, which I think is rank 140 of memory devices, and that's shown
`on the left, or the path on the right which is, I think, rank 142.
`
`Now we argued in the petition that this satisfied the claim element that we're
`talking about today. The Board declined to institute on that; and, instead, found that
`Amidi taught that claim element. And so -- I'm at slide 14; let me just talk about Amidi
`very briefly. Published patent application in 2006 -- again, that's 102b prior art . It also
`discloses a memory module. In this memory module though there is controlled circuitry
`that permits what has been referred to as chip select emulation functionality. In the
`system disclosed in Amidi, the system memory controller would provide two chip select
`signals which would permit the activation of one or two memory ranks. Amidi says you
`could instead take those chip select signals -- and, I think, on the next slide, slide 16, it
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`shows it -- and combine them with the high order address bit and in that way instead of
`using two memory ranks, or memory banks, you could have four memory banks and
`activate just one of the four; and he says that's a good thing to do because you can use
`lower density, less expensive DRAM chips; and that's his reasoning for doing it.
`
`And the ground that we argued in the petition that was instituted was you could
`take that chip select emulation functionality of Amidi and plug it into Halbert and so that
`Halbert's system would be selecting less than all of the ranks and, therefore, selectively
`allowing data communication with some memory and selectively isolating others.
`
`Now, in this case in this proceeding, there has been a number of arguments that
`Petitioner has moved away from the theories in the petition; and that is, I'd like to show
`you that is absolutely inaccurate; and I'd like to do that, if I may, in the best way possible,
`I think, which is by showing you the petition and what's actually in there.
`
`And so I have in my hand -- and I'll put it up on the Elmo -- this is the petition in
`this proceeding, as you can see, Your Honor. Now, as in others, most of the elements of
`the claim are addressed earlier in the petition. This particular ground adds to that and it
`deals with just this selectively allow limitation; and it begins, as you can see here -- I'll
`put this up here. It's page 61 of the petition -- this is Halbert in view of Amidi rendered
`the claims obvious -- and you can see that it deals with the selectively allowed limitation
`-- right at the top of this page -- it says to the extent one might argue that Halbert does not
`disclose, and then there's the selectively allowed limitation; and we say, Halbert would
`render that limitation obvious in light of Amidi.
`
`And then there's some discussion about analogous art, and going over to page 62,
`is a brief discussion of what Amidi discloses. And then here is what I really want to
`point out, Your Honor -- at the bottom of page 62 going over to 63 -- this is the
`obviousness combination that we asserted; and it's right here -- I'm going to highlight it
`on the screen -- it would have been obvious to employ the chip select emulation
`functionality -- the functionality, Your Honor -- i.e., decoding address bits to generate
`module control signals -- going onto the next page -- in order to select memory ranks of
`Amidi and Halbert's memory module. -- from 62 to 63. And why I focus on that is
`because, as I just pointed out, the claim language that we're talking about is generic
`circuitry configured to perform certain functionality. The proposed ground was you take
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`the functionality of Amidi and put it into the circuitry of Halbert.
`
`Now, we justified this in several different ways in the petition. For example, on
`page 65 -- I'm showing you 65 at the bottom -- we pointed out that to employ that chip
`select functionality, the chip select functionality of Amidi in the system of Halbert would
`be only the arrangement of old elements, doing the old things, with no unpredictable
`results. And on the next page, page 66, we had a number of motivations to combine. On
`that page, beginning at the top -- with this one, moreover, a person with ordinary skill in
`the art would have been motivated to use the chip select functionality of Amidi on system
`of Halbert to permit the use of lower density and, therefore, cheaper and more readily
`available DRAM.
`
`Now, this was the proposed ground in the petition and, in fact, that was exactly
`the ground that the Board instituted on. I have the Board's institution decision here. I'll
`put it up here -- it's Paper 8, and at page 13 going over to 14 at the bottom -- the Board
`points out that we are persuaded that Petitioner sets force sufficient articulated reasoning
`with rational underpinning to support the legal conclusion that it would have been
`obvious to modify the teachings of Halbert with Amidi's teachings to include rank
`selection functionality; and then the Board quotes "all of our reasoning -- it's just the
`arrangement of old elements there at the bottom of page 13; if you go over to 14 -- our
`motivation to combine analysis." So this was what was instituted. Note that nowhere in
`there does it say anything about a multiplexer. The claim doesn't say anything about a
`multiplexer, and none of our analysis, and none of what the Board instituted says
`anything about a multiplexer.
`
`I'd like to just point something else out. What I just read to you -- well, to the
`panel -- from the petition and the institution decision, the Patent Owner doesn't dispute.
`The don't dispute that Halbert and Amidi are prior art; they don't dispute that if you took
`the chip select emulation functionality of Amidi and used it in the circuitry of Halbert,
`that the claim would be satisfied; they don't dispute that combination, functionality from
`Amidi and circuitry from Halbert, would be just the arrangement of old elements. They
`don't dispute that there's an explicit motivation to combine to make that particular
`combination in Amidi. None of that is disputed.
`
`So, what are they disputing? Here is what's really going on here, Your Honor;
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`and I'm going to show you another portion of -- this is, again, back to that same part of
`the petition; in the middle of that same analysis; this is page 63 of the petition, at the
`bottom, last paragraph -- where we write in the course of this analysis, the modified
`interface circuity of Halbert in an exemplary implementation of such a combination
`would look like the annotated version of Halbert's Figure 4 reproduced below; okay -- an
`exemplary implementation. That is the only thing they're fighting over. That this
`exemplary implementation that was created by our expert and was in his declaration, and
`we put in our petition here on page 64, they are fighting over that; and their main
`argument relates to these MUXs here. They say that we haven't shown obviousness
`because the MUXs in this exemplary implementation -- MUXs in a data path -- are not
`found in Amidi alone.
`
`Now, I know on reply I'm going to talk a little more about this; but I'd like to
`suggest to you that the law of obviousness does not require me to show the details of an
`implementation of an obvious combination. The claim here does not require
`multiplexers. They could have written it that way; they chose not to; it's generic circuitry
`for performing functionality. I don't have to show Amidi includes multiplexers or
`multiplexers in a data path. I don't even have to show it in Halbert either; although
`Halbert actually has it.
`
`So, all of their arguments go to what is -- and I think this word came up in the last
`argument -- a strawman, something that I don't have to show. They admit by not
`contesting every part of our analysis and every part of the ground that was instituted by
`the Board.
`
`JUDGE MOORE: Okay. So, we'll take it that this did appear in your petition,
`right? It probably appeared in your petition for a reason; and I would suggest that the
`reason may be that as well as showing that the claim limitation was met by the
`combination of references, it has to be shown that it would be within the skill of one of
`ordinary skill in the art at the time of the invention to actually implement it; and although
`there's this tension between cases that say you don't have to show bodily incorporation --
`in other words, you don't have to show exactly how they would fit together -- you do
`have to show that combining the teachings would be within one of ordinary skill in the
`art. So, I just say that to say, from my understanding, that's what the argument is over.
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`MR. MICALLEF: Your Honor, I think you're dead right. That's the only thing
`
`they can be arguing about. So, let me talk about that for a second. I want to go back to
`our slides, if I may. And let me just put a fine point on what they're arguing here.
`They're arguing that multiplexers, using multiplexers in the data path -- that is on signal
`lines that are carrying data information as opposed to control or address -- is the thing
`that takes it outside the level of ordinary skill in the art. Now, they don't explain what the
`data path actually has to do with it; and they never argue that somehow a multiplexer
`operates differently if you put address signals through it rather than data signals, right. In
`fact, I think there's a Federal Circuit case that says that's not so.
`
`But putting that aside -- can we have slide 35? I want to show slide 35 from our
`deck. It's clear that using multiplexers in a data path was well known in the prior art
`because our principal reference in the main figure does so. MUX 124 is a multiplexer;
`it's in the data path. So, there's absolutely no question that -- and this patent is,
`presumably, enabled -- and so, there's no question that a person of skill in the art would
`have known that you could use multiplexers in the data path, and would have known you
`could do it. In fact --
`
`JUDGE MOORE: Their argument then -- and, you know, I understand we have
`motions related to this -- but their argument is that reference to this multiplexer is a new
`theory. I don't know if this is the right time for you to talk about that since we're here?
`
`MR. MICALLEF: I'm happy to do that. I do have more about how people would
`know to use MUXs -- I can do that now; or, let me answer your question first. Could we
`have slide 32, please? So, on this slide we have a number of bullets that were with our
`original filings about this, about using Halbert and using it -- because they're trying to
`argue, no you can only look at Amidi, and even though Amidi has multiplexers, they
`don't have multiplexers in a data path. But, I'd like to direct your attention to the third
`bullet on this slide 32 where it says -- and this is a passage from Dr. Stone, our expert's
`Expert Declaration, Exhibit 1003, at paragraph 176 where he says Halbert also discloses
`how it was known to use a module controller to control interface circuitry such as
`multiplexers, buffers and registers to communicate data with appropriate timing.
`
`We cited this passage at page 65 of our petition -- I'm happy to show it to you, if
`you're interested; and what we cited for, Your Honor, was that using this functionality
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`and these structures was merely in the cited combination the arrangement of old elements
`doing just what they were known to do without unpredictable results. It's the petition,
`page 65, Exhibit 1003, 176. So, we did cite it, specifically. There's no question on this
`record any more that a person of ordinary skill in the art could use multiplexers in the
`data path.
`
`Could I have slide 20? So, on slide 20 here, this annotated, Figure 4, was done at
`the cross examination of Patent Owner's expert, Dr. Baker, who was explaining how you
`would implement a four rank modification embodiment of Halbert; and Halbert says you
`could do that. And he's drawn some additional ranks and some additional buffer
`registers, and he says that you would make that 2:1 multiplexer in the data path a 4:1
`multiplexer in the data path. And he was asked -- and this is slide 21 -- and you think a
`person of ordinary skill in the art would know how to implement the memory module of
`Halbert with four ranks of memory -- I think so, yes. So, all the evidence here is that a
`person of ordinary skill in the art knew how to use MUXs in the data path, in this prior
`art. There's just no question about that.
`
`And I'd like to point out, Your Honor, we're talking about 2009 priority date.
`That's a very late priority date and there is -- in fact, let me go to one more slide, slide 36
`-- so, the figure on this slide comes from Exhibit 1007; and, again, you see there's a MUX
`there, it's in the data path. This document, Your Honor, is the JEDEC DDR standard
`from the year 2000, nine years before the priority date; and it's requiring a MUX in the
`data path, the standard for the technology at issue here at the time. There's just no
`argument that there's no lack of enablement or undue experimentation necessary. The
`standards in the prior art, the prior art references at issue here, they all demonstrate that
`people knew how to use MUXs in the data path.
`
`JUDGE MOORE: I missed it earlier, but you're approaching your 10 minutes that
`you wanted to hold out. If you have a couple more things you want to talk about, I could
`give you a few minutes on top of the 10 minutes if you want to stop now?
`
`MR. MICALLEF: Thank you, Your Honor. I will just maintain the rest of my
`time for rebuttal.
`
`JUDGE MOORE: All right.
`
`MR. MICALLEF: Thank you.
`
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`JUDGE MOORE: Whenever you're ready.
`
`MR. ARJOMAND: Good afternoon, Your Honors, and may it please the Board.
`
`As my colleague for Hynix mentioned, the issue in this proceeding boils down to a single
`combination, the Halbert/Amidi combination; and it's our view that combination is
`deficient. Now, I'm turning to slide 2. Before I discuss the deficiencies of that
`combination, I'd like to make a couple of prefatory statements.
`
`The first statement that I'd like to make is with regard to the question that you had
`asked me right before the hearing began relating to the remand decision. Just to be more
`precise, the 185 claims at issue do not recite load isolation.
`
`Secondly, as another prefatory issue to the extent Hynix's counsel is
`characterizing the 185 Patent in their opening arguments today or in the reply, we do not
`agree with those characterizations. We think the focus of this proceeding should be on
`the Halbert/Amidi combination; and our silence as to those characterizations should not
`be viewed that we concede to them; and, in fact, we do oppose them, Your Honors.
`
`Finally, I'd like to just point to slide 3 of our presentation just to make sure that
`we're all on the same page. What we refer to as the selectively allowed limitation
`actually has two parts. Each circuit of the plurality of circuits configured to selectively
`allow data transmission between the system memory controller and at least one selected
`memory device of the at least two corresponding memory devices in response to the
`module control signal; and to selectively isolate at least one other memory device of the
`at least two corresponding memory devices from the system memory controller in
`response to the module control signals.
`
`That is the claim language that we call the selectively allowed limitation, Your
`Honors; and I believe Hynix's counsel is also referring to that entire passage as the
`selectively allowed limitation. For the rest of the hearing, I'll be referring to this passage
`when I use the term selectively allowed limitation.
`
`Now, turning to the merits at hand, I'd like to make four points today; and, I think,
`those four points will be sufficient to dispose this ground in the IPR. As you may know,
`Your Honors, this patent has been -- this is the third IPR on the 185 Patent. The first two
`IPRs were denied, institution was denied; and this one while institution was made, we
`believe that the claims at issue are patentable.
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`So, point number one is the role of Amidi in the combination; and let me just
`
`direct you to slide no. 4, and in the first three grounds of the petition, Hynix relied on
`Halbert as an anticipatory reference; they relied on Halbert as a single reference --
`obviousness reference -- and they relied on Halbert and Amidi in combination. In the
`institution decision, Your Honors denied the Halbert anticipation ground and the Halbert
`single obviousness ground; and the reason was is that Hynix had relied on the fact that
`data is being driven to data registers 126 and 128 in different cycles as meeting the
`selectively allowed limitation; and because the data registers aren't the memory devices,
`Your Honors decided not to institute on those grounds.
`
`The third ground, specifically, relied on Amidi for the selectively allowed
`limitation; and I believe that Hynix's counsel, today, stated so much so in his opening
`arguments. So, we think it's very clear that they are relying on Amidi to meet the
`limitations of the selectively allowed limitation, and we're a little bit baffled by their
`arguments in their slides and in their paper that in the institution decision at page 13 --
`which is here on slide 4 -- where it says, however, petitioner also relies on Amidi to show
`this limitation that their reference to also somehow indicates that they have been relying
`on Halbert for the Halbert/Amidi combination with respect to the selectively allowed
`limitation.
`
`Of course, that's not the case at all. It also refers to the fact that in those earlier
`grounds, they were relying on Halbert for the selectively allowed limitation, and in this
`ground, the Halbert/Amidi ground, they're relying on Amidi. So, we think it's very clear
`in the record and from the institution decision that Amidi is being relied on for the
`selectively allowed limitation.
`
`JUDGE MOORE: Right; but the -- and we can get into the details of it -- but in
`the petition, what they present is a combination -- and they would say that it's just an
`example -- but even in that example, it's a combination of the functionality of Amidi with
`the existing functionality of Halbert. So, you know, I don't necessarily feel like this
`language, which you could probably find in many DIs, was meant to say that they're not
`relying on a combination. So, they're certainly relying on a combination of Halbert and
`Amidi; so, you know, we can talk about what aspects of Halbert they disclosed or didn't
`disclose, but certainly this isn't meant to deny the fact that this is a combination of -- and
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`as I said before, of the teachings of Amidi with the teachings of Halbert as required by
`the Fed Circuit.
`
`MR. ARJOMAND: Right. I understand that, Your Honor. The point that I was
`making is that when they point to the fact that they raised Halbert in other grounds, those
`anticipation in the single-reference obviousness grounds, they relied on Halbert for,
`specifically, the data registers of Halbert for meeting the selectively allowed limitation;
`and I will now show you that in the Halbert/Amidi ground, they rely squarely on Amidi
`for the selectively allowed limitation. I understand it's a combination, but they're relying
`on Amidi for that limitation; and later on after we deposed their expert, they start to rely
`on other passages of Halbert for the selectively allowed limitation, and Dr. Stone's book,
`not the passages that they relied on in the Halbert anticipation and single reference
`grounds, which were focused on the data registers.
`
`JUDGE MOORE: Okay, and since you weren't there, then the question that I
`have is that then in their reply -- is there a paper, a brief in the case that you're saying,
`relies on that testimony? In other words, I need to know how that testimony is in the case
`besides just being testimony that was given by an expert. Just so we have it for the
`record, if you could tie that to the reply or from the paper that --
`
`MR. ARJOMAND: Of course, Your Honor, I mean it certainly came up in the
`deposition of Dr. Stone. I mean when we asked him questions about well, what is your
`theory, rather than defend a theory that he had in the petition, he came up with a new
`theory relying on Halbert's MUXs and his own book; and that discussion was then also
`provided in Petitioner's reply. I can definitely get you the cites for that, if that's what
`you're looking for, Your Honor.
`
`JUDGE MOORE: Maybe your colleague can provide that later.
`
`MR. ARJOMAND: Okay.
`
`JUDGE MOORE: I don't need a long discussion of it; if he can give me the bates
`number that you're relying on. I think the point is made, but, go ahead.
`
`MR. ARJOMAND: And I will go to the portion of the petition where I think the
`original theory is laid out very clearly. Well, first of all, it's right here on slide 6. This is
`an image from the petition at page 64. This is their combination, Your Honor. For
`counsel here to get up and say that it's exemplary; that this wasn't, you know, our ground;
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`this was just one example. I think it's a little bit surprising to me because, frankly, that's
`the ground that they presented in their petition, and that's the ground that they're stuck
`with. And I think that it's telling that they're trying to get away from this because the fact
`is that when you look at what they've done, it doesn't make sense from an obviousness
`perspective.
`
`That's right from petition, 64; but turning to slide 7, it's also in Dr. Stone's
`Declaration. At paragraph 165, he's very clear. He's saying I am looking at Amidi and I
`would produce a rank selector signal provided to the multiplexers in the interfaced
`circuitry -- and then parenthetical-- similar to Amidi's figure 8 that couples an address bit
`and an inverted form of that address bit to multiplexers which select which rank to
`activate. It's pretty clear that they're relying on, in their petition, Amidi's figure 8, the
`multiplexer in that CPLD, and the signal that basically drives those multiplexers, as the
`rank selector signal.
`
`I'm now moving to slide 8 which shows the portions from the Amidi publication
`that they're relying on; and if you look it's pretty clear. It says the inverted state -- this is
`paragraph 69 of Amidi -- it says the inverted state drives both MUX WCS# and WCS1,
`blocks 8-16 and 8-18, which goes to the respective registers, 820 and 821. So, the
`address bit, or the inverted address bit, selects one of the two sets of MUXs -- in this
`case, this is the top set that's been selected -- and then the CS signals -- the chip select
`signals -- coming in to the MUX basically define what the output chips leg will be. So,
`this is a pretty clear indication. If you go back to Dr. Stone's Declaration, at paragraph
`165, when he talks about rank selector signal and MUXs being used to select ranks, and
`you look at the cites there, and you transfer them over to the cites in Amidi, it's pretty
`clear that this is what he's relying upon for his original theory.
`
`And this is slide 9, righ