Trials@uspto.gov
`571-272-7822
`
`
`
`
`
`
`
`
` Paper 26
`
`
`
` Entered: July 5, 2018
`
`
`
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SK HYNIX INC., SK HYNIX AMERICA INC., and
`SK HYNIX MEMORY SOLUTIONS INC.,
`Petitioner,
`
`v.
`
`NETLIST, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-00577
`Patent 8,516,185 B2
`____________
`
`
`Before BRYAN F. MOORE, MATTHEW R. CLEMENTS, and
`SHEILA F. McSHANE, Administrative Patent Judges.
`
`MOORE, Administrative Patent Judge.
`
`FINAL WRITTEN DECISION
`35 U.S.C. 318(a)
`
`
`
`
`
`571-272-7822
`
`
`
`
`
`
`
`
` Paper 26
`
`
`
` Entered: July 5, 2018
`
`
`
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SK HYNIX INC., SK HYNIX AMERICA INC., and
`SK HYNIX MEMORY SOLUTIONS INC.,
`Petitioner,
`
`v.
`
`NETLIST, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-00577
`Patent 8,516,185 B2
`____________
`
`
`Before BRYAN F. MOORE, MATTHEW R. CLEMENTS, and
`SHEILA F. McSHANE, Administrative Patent Judges.
`
`MOORE, Administrative Patent Judge.
`
`FINAL WRITTEN DECISION
`35 U.S.C. 318(a)
`
`
`
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`
`I.
`INTRODUCTION
`SK hynix Inc., SK hynix America Inc., and SK hynix memory
`solutions Inc., (collectively “Petitioner”) filed a Petition (Paper 1, “Pet.”)
`pursuant to 35 U.S.C. §§ 311–319 to institute an inter partes review of 1–3,
`7, 8, and 10–12 of U.S. Patent No. 8,516,185 B2 (“the ’185 Patent,” Ex.
`1001). The Petition is supported by the Declaration of Harold S. Stone,
`Ph.D. (“Stone Declaration,” “Stone Dec.,” Ex. 1003). Netlist, Inc. (“Patent
`Owner”) filed a Preliminary Response (“Prelim. Resp.,” Paper 6).
`On July 7, 2017, we instituted an inter partes review of claims 1–3, 7,
`8, and 10–12 of the ’185 Patent, but did not institute on all grounds. Paper
`8, 6, 21 (“Inst. Dec.”). Patent Owner filed a Response. Paper 12 (“PO
`Resp.”). The Patent Owner Response is supported by the Declaration of R.
`Jacob Baker, Ph.D. (“Baker Declaration,” “Baker Dec.,” Ex. 2003).
`Petitioner filed a Reply. Paper 16 (“Reply”).
`On February 28, 2018, Patent Owner filed a motion to exclude. Paper
`20 (“Mot. to Excl.”). Petitioner filed a response to the motion to exclude.
`Paper 21 (“Mot. to Excl. Resp.”). Patent Owner filed a reply to the
`response. Paper 22 (“Mot. to Excl. Reply”).
`An oral hearing was held on April 6, 2018. Paper 25 (“Tr.”).
`On May 2, 2018, pursuant to SAS Inst., Inc. v. Iancu, 138 S. Ct. 1348
`(2018), we modified our institution decision to institute on all grounds
`presented in the Petition. Paper 24 (“SAS Order”). We invited the parties to
`request briefing regarding the newly added grounds and did not receive a
`request. Id.
`
`2
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`
`We have jurisdiction under 35 U.S.C. § 6. This Final Written
`Decision is issued pursuant to 35 U.S.C. § 318(a). For the reasons that
`follow, we determine that Petitioner has shown by a preponderance of the
`evidence that claims 1–3, 7, 8, and 10–12 are unpatentable.
`A. Related Proceedings
`Petitioner recites a list of District Court proceedings related to this
`inter partes review. Pet. ii.
`
`B. The ’185 Patent
`The ’185 patent relates generally to a memory module that includes a
`plurality of memory devices, a controller, and a plurality of circuits that are
`configured to selectively isolate the plurality of memory devices from the
`system memory controller. Ex. 1011, Abstract. In a conventional memory
`module, the system memory controller sees its load during a read or write
`operation as all of the memory devices, which causes significant
`performance issues. Id. at 4:47–52, 5:5–10, 11:34–38. To address this need,
`the ’185 Patent discloses a memory module that employs data transmission
`circuits to reduce the load seen by the system memory controller. Id. at
`10:41–47. Figure 3A of the ’185 Patent is reproduced below.
`
`3
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`
`
`
`Figure 3A depicts an exemplary memory subsystem in accordance
`with one embodiment. Id. at 3:37–39. Each memory module 402 comprises
`multiple rows, or “ranks,” of memory devices 412, control circuit 430, and a
`plurality of data transmission circuits 416. Id. at 7:61–8:13. In the
`embodiment depicted, each data transmission circuit 416 is coupled to four
`memory devices 412, and is configured to respond to module control signals
`from the control circuit 430 by selectively allowing or inhibiting data
`transmission between system memory controller 420 and at least one
`selected memory device. Id. at 8:13–31. System memory controller 420 is
`coupled to each memory module 402 by data lines 450 and address and
`control lines 440. Id. at 7:34–48. Because data lines 450 are operatively
`4
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`coupled to single data transmission circuit 416 rather than to four memory
`devices 412, system memory controller 420 sees only a single load instead
`of concurrently seeing the loads of all four memory devices. Id. at 14:30–
`59. Thus, in comparison to prior art memory modules, the load seen by
`system memory controller 420 can be reduced by a factor of four. Id. at
`14:59–62.
`
`C. Illustrative Claim
`Independent claim 1, reproduced below, is illustrative of the claimed
`subject matter:
`1. A memory module comprising:
`a plurality of memory devices;
`a controller configured to receive control information
`from a system memory controller and to produce module
`control signals; and
`a plurality of circuits configured to receive the module
`control signals, each circuit of the plurality of circuits having a
`first bit width and operatively coupled to at least two
`corresponding memory devices of the plurality of memory
`devices, the at least two corresponding memory devices each
`having a second bit width smaller than the first bit width, each
`circuit of the plurality of circuits comprising at least one write
`buffer and at least one read buffer and configured to selectively
`allow data transmission between the system memory controller
`and at least one selected memory device of the at least two
`corresponding memory devices in response to the module
`control signals, and to selectively isolate at least one other
`memory device of the at least two corresponding memory
`devices from the system memory controller in response to the
`module control signals, wherein each circuit of the plurality of
`circuits is operable, in response to the module control signals,
`to actively drive write data from the system memory controller
`to the at least one selected memory device of the at least two
`
`5
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`
`corresponding memory devices through the at least one write
`buffer, and to receive and drive read data from the at least one
`selected memory device of the at least two corresponding
`memory devices to the system memory controller through the at
`least one read buffer, wherein the circuits of the plurality of
`circuits are distributed at corresponding positions separate from
`one another.
`Id. at 18:35–67.
`
`
`D. Instituted Grounds of Unpatentability
`We instituted trial on the following grounds (Inst. Dec. 2, 21;
`
`SAS Order 2):
`
`Reference(s)
`Halbert1
`Halbert and Stone2,3
`Halbert and Amidi4
`Halbert and Connolly5
`Halbert and JEDEC6
`
`
`
`Basis
`§ 102 and § 103
`§ 103
`§ 103
`§ 103
`§ 103
`
`Claims challenged
`1–3, 7, 8, and 10–12
`1–3, 7, 8, and 10–12
`1–3, 7, 8, and 10–12
`3
`10
`
`
`1 US Patent No. 7,024,518 B2, issued April 4, 2006 (“Halbert,” Ex. 1005).
`2 Stone, MICROCOMPUTER INTERFACING, published 1982 (“Stone, Ex. 1013).
`3 Although this ground is not listed on page 2 of the Petition, Petitioner
`includes this analysis at pages 59–60 of the Petition.
`4 US Publication No. 2006/0117152 A1, published June 1, 2006 (“Amidi,”
`Ex. 1019).
`5 US Patent No. 6,070,217, issued May 30, 2000 (“Connolly,” Ex. 1016).
`6 JEDEC STANDARD DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION,
`JESD79, published June 2000 (“JEDEC,” Ex. 1007).
`6
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`
`II. ANALYSIS
`A. Relevant Law
`1. Anticipation Law
`Anticipation is governed by 35 U.S.C. § 102. “To anticipate a claim, a
`prior art reference must disclose every limitation of the claimed invention,
`either expressly or inherently.” Rapoport v. Dement, 254 F.3d 1053, 1057
`(Fed. Cir. 2001). “[A] patent is invalid as anticipated if ‘the invention was
`described in’ a patent or published application ‘before the invention by’ the
`patentee.” Microsoft Corp. v. Biscotti, Inc., 878 F.3d 1052, 1068 (Fed. Cir.
`2017) (quoting 35 U.S.C. § 102(e)). “In order to anticipate the claimed
`invention, a prior art reference must disclose all elements of the claim within
`the four corners of the document, and it must disclose those elements
`arranged as in the claim.” Id. (quotation omitted).
`2. Obviousness Law
`A claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`between the claimed subject matter and the prior art are such that the subject
`matter, as a whole, would have been obvious at the time the invention was
`made to a person having ordinary skill in the art to which said subject matter
`pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The
`question of obviousness is resolved on the basis of underlying factual
`determinations including: (1) the scope and content of the prior art; (2) any
`differences between the claimed subject matter and the prior art; (3) the level
`of skill in the art; and, (4) where in evidence, so-called secondary
`considerations, including commercial success, long-felt but unsolved needs,
`
`7
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`failure of others, and unexpected results.7 Graham v. John Deere Co.,
`383 U.S. 1, 1718 (1966) (“the Graham factors”).
`3. Level of Skill Law
`The level of ordinary skill in the art usually is evidenced by the
`references themselves. See Okajima v. Bourdeau, 261 F.3d 1350, 1355
`(Fed. Cir. 2001); In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995); In
`re Oelrich, 579 F.2d 86, 91 (CCPA 1978). For an obviousness analysis,
`prior art references must be “considered together with the knowledge of one
`of ordinary skill in the pertinent art.” In re Paulsen, 30 F.3d 1475, 1480
`(Fed. Cir. 1994) (quoting In re Samour, 571 F.2d 559, 562 (CCPA 1978)).
`Moreover, “it is proper to take into account not only specific teachings of the
`reference but also the inferences which one skilled in the art would
`reasonably be expected to draw therefrom.” In re Preda, 401 F.2d 825, 826
`(CCPA 1968). That is because an obviousness analysis “need not seek out
`precise teachings directed to the specific subject matter of the challenged
`claim, for a court can take account of the inferences and creative steps that a
`person of ordinary skill in the art would employ.” KSR, 550 U.S. at 418; see
`also In re Translogic Tech., Inc., 504 F.3d at 1259.
`4. Claim Interpretation Law
`In an inter partes review, claim terms in an unexpired patent are given
`their broadest reasonable construction in light of the specification of the
`patent in which they appear. 37 C.F.R. § 42.100(b). Under this standard, we
`
`
`7 Patent Owner does not put forth evidence it alleges tend to show secondary
`considerations of non-obviousness in its Response.
`8
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`interpret claim terms using “the broadest reasonable meaning of the words in
`their ordinary usage as they would be understood by one of ordinary skill in
`the art, taking into account whatever enlightenment by way of definitions or
`otherwise that may be afforded by the written description contained in the
`applicant’s specification.” In re Morris, 127 F.3d 1048, 1054 (Fed. Cir.
`1997).
`We presume that claim terms have their ordinary and customary
`meaning. See Trivascular, Inc. v. Samuels, 812 F.3d 1056, 1062 (Fed. Cir.
`2016) (“Under a broadest reasonable interpretation, words of the claim must
`be given their plain meaning, unless such meaning is inconsistent with the
`specification and prosecution history.”); In re Translogic Tech., Inc., 504
`F.3d 1249, 1257 (Fed. Cir. 2007) (“The ordinary and customary meaning is
`the meaning that the term would have to a person of ordinary skill in the art
`in question.” (internal citation and quotation marks omitted)). A patentee,
`however, may rebut this presumption by acting as his or her own
`lexicographer, providing a definition of the term in the specification with
`“reasonable clarity, deliberateness, and precision.” In re Paulsen, 30 F.3d
`1475, 1480 (Fed. Cir. 1994). Only those terms that are in controversy need
`to be construed, and only to the extent necessary to resolve the controversy.
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir.
`1999); Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co. Ltd., 868
`F.3d 1013, 1017 (Fed. Cir. 2017).
`
`9
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`
`B. Level of Skill Analysis
`
`Petitioner asserts:
`A person of ordinary skill in the art in the field of the ’185
`Patent in 2009 would have been someone with an advanced
`degree in electrical or computer engineering and two years
`working in the field, or a bachelor’s degree in such engineering
`disciplines and at least five years working the field. Such a
`person would have been knowledgeable about the design and
`operation of computer memories, most particular DRAM and
`SDRAM devices that were compliant with various standards of
`the day, and how they interact with other components of a
`computer system, such as memory controllers. He or she would
`also have been familiar with the structure and operation of
`circuitry used to access and control computer memories,
`including sophisticated circuits such as ASICs and CPLDs and
`more low level circuits such as tri-state buffers, flip flops and
`registers. EX1003 ¶45.
`
`Pet. 4. Patent Owner asserts:
`[A] person of ordinary skill in the art would have a Bachelor’s
`degree in electrical engineering, computer engineering, or in a
`related field and at least one year of work experience relating to
`memory systems, and would be familiar with the design of
`memory devices and memory modules. While I believe that at
`least one year of relevant industry experience could be sufficient,
`two years of relevant industry experience would clearly suffice.
`
`Ex. 2003 ¶ 34.
`Neither party has argued that the difference between the parties’
`articulated level of skill should change the analysis as to patentability.
`Therefore, we adopt Petitioner’s articulation of the level of skill and
`acknowledge that the level of ordinary skill in the art is also reflected by the
`prior art of record. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed.
`
`10
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`Cir. 2001); In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995); In re
`Oelrich, 579 F.2d 86, 91 (CCPA 1978).
`C. Claim Construction Analysis
`We determine that it is not necessary to provide an express
`interpretation of any term of the claims.
`
`D. Asserted Anticipation and Obviousness over Halbert
`Petitioner contends claims 1–3, 7, 8, and 10–12 are unpatentable
`under 35 U.S.C. § 102(b) as anticipated by Halbert and/or unpatentable
`under 35 U.S.C. § 103(a) as obvious over Halbert. Pet. 2, 27–58. Petitioner
`explains how Halbert allegedly describes all of the claim limitations. Id.
`(citing Ex. 1003).
`
`1. Halbert (Ex. 1005)
`Halbert describes memory devices, systems, and module architectures.
`Ex. 1005 ¶ 2. Figure 4 of Halbert is reproduced below.
`
`
`
`11
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`
`As illustrated in Figure 4 of Halbert, above, a memory module
`includes module controller 110, data interface circuit 120, and memory
`device array 140/142, which includes device ranks 140 and 142. Ex. 1005
`¶¶ 28, 30. Data interface circuit 120 includes data registers 126 and 128 and
`multiplexer/demultiplexer 124 and provides for data transfers between the
`module and the system memory data bus and between the interface circuit
`and the memory device array. Id. ¶¶ 30, 32, 33.
`
`2. Amidi (Ex. 1019)
`Amidi discloses a memory interface system with a processor, a
`memory controller, and a memory module. Ex.1006 ¶¶ 2, 3. According to
`Amidi, a prior art memory interface system is shown in Figure 1, reproduced
`below.
`
`
`
`
`
`Figure 1 is a schematic of a standard
`prior art memory interface system.
`
`The prior art system in Figure 1 includes memory module 106 with
`controller address bus 114, controller control signal bus 116, and controller
`data bus 118. Id. ¶ 2, Fig. 1. As illustrated in Figure 1, memory module 106
`
`12
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`communicates with memory controller 104 via busses 114, 116, 118. Id. at
`Fig. 1. Amidi teaches that each stack of DDR memory devices has a data
`signal line and a data strobe line DQS. Id. ¶ 32; Fig. 2. Amidi also teaches
`that at least two DDR memory devices are connected to a common data
`memory bus. Id. ¶ 34; Fig. 3.
`Amidi further discloses multiple memory devices mounted on the
`front and back side of memory module 400 as shown in Figure 4A
`reproduced below. Id. ¶¶ 34, 37.
`
`
`
`Figure 4A is a schematic of a DDR memory module.
`
`Figure 4A, above, illustrates one embodiment of Amidi where
`memory module 400 includes memory devices 404, resistor network 406,
`register 408, complex programmable logic device (CPLD) 410, phase-
`locked loop (PLL) 412, and SPD 414. Id. According to Amidi, memory
`module 400 receives input signals, including address (Add(n)) signals, row
`address strobe (RAS) signal, column address strobe (CAS) signal, and bank
`address (BA[1:0]) signals. Ex. 1008 ¶ 50; Fig. 6A.
`
`13
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`
`Another embodiment of Amidi’s memory interface system is shown
`in Figure 6A, reproduced below.
`
`
`Figure 6A is a schematic of a row address decoding system
`for a transparent four rank memory module.
`As illustrated in Figure 6A above, module connector 602 sends
`signals to CPLD 604, PLL 606, and register 608. Id. CPLD 604 also
`ensures that all commands for a two rank memory module conveyed by
`module connector 602 are performed on the four rank memory modules.
`Id. ¶ 52. Amidi explains that the system chip select signals control the ranks
`of individual memory modules. Id. ¶¶ 2, 3.
`
`3. Analysis
`Claim 1 recites “at least one selected memory device of the at least
`two corresponding memory devices in response to the module control
`signals, and . . . at least one other memory device of the at least two
`corresponding memory devices from the system memory controller” and
`“[each circuit of the plurality of circuits] configured to selectively allow data
`transmission between the system memory controller and at least one selected
`
`14
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`memory device of the at least two corresponding memory devices in
`response to the module control signals” (“Selectively Allow Limitation”).
`Petitioner asserts that in Halbert not all of the memory devices are
`written to or read from simultaneously. Pet. 37–41. In particular, Petitioner
`asserts that Halbert’s directing of data, during a write operation, from the
`system memory data bus to registers 126 and 128 in successive clock cycles
`means that data being received by the memory devices corresponding to
`registers 126 and 128, respectively (e.g., ranks 140 and 142, respectively),
`occurs in successive clock cycles. Thus, according to Petitioner, “those
`memory devices associated with register 126 (i.e. Rank 140) receive data
`transmission from the system memory controller in the first clock cycle, but
`not in the second clock cycle . . . [and] those memory devices associated
`with register 128 (i.e., Rank 142) receive data transmissions from the system
`memory controller in the second clock cycle, but not in the first clock
`cycle.” Id. at 38. Therefore, according to Petitioner, Halbert does not, and
`cannot, write to the memory devices in ranks 140 and 142 simultaneously,
`because the memory devices in ranks 140 and 142 do not receive data
`concurrently. Id.
`In its Preliminary Response, Patent Owner asserts8
`while data is sequentially latched onto registers 126 and 128, that
`data is then concurrently, not sequentially, written to memory
`device array 140/142—such operation is illustrated in Fig. 4,
`
`8 Patent Owner chose not to request additional briefing to address this
`ground and arguments in the Preliminary Response are generally waived
`(Paper 8, 2–3), however, we acknowledge these arguments due to the
`unusual circumstance created by the Supreme Court’s decision in SAS.
`15
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`
`above. Thus, all of Halbert’s memory devices are selected or
`enabled concurrently such that Halbert can write to all of its
`memory devices simultaneously. This is not, and is exactly
`counter to, the Petitioner’s assertions that the memory devices in
`ranks 140 and 142 receive—and thus, store—data sequentially.
`
`Prelim. Resp. 27–28. We agree. Petitioner has not explained how latching
`data to registers 126 and 128 is data transmission between a memory
`controller and a memory module when registers 126 and 128 are outside of
`the memory module. Moreover, Petitioner’s arguments and evidence with
`respect to claims 2, 3, 7, 8, and 10–12 do not cure this deficiency.
`
`For the reasons given above, Petitioner has not shown there is a
`preponderance of the evidence in establishing the unpatentability of claim 1
`of the ’185 patent and claims 2, 3, 7, 8, and 10–12 that depend from claim 1
`of the ’185 patent as anticipated by Halbert. Additionally, Petitioner does
`not argue that one of ordinary skill would have modified Halbert to meet the
`Selectively Allow Limitation. Pet. 52–54. Thus, Petitioner also has not
`shown there is preponderance of the evidence establishing the
`unpatentability of claim 1 the ’185 patent, and claims 2, 3, 7, 8, and 10–12
`that depend from claim 1, as obvious over Halbert.
`
`E. Asserted Anticipation and Obviousness over Halbert and Amidi
`Petitioner contends claims 1–3, 7, 8, and 10–12 are unpatentable
`under 35 U.S.C. § 103(a) as obvious over Halbert and Amidi. Pet. 2, 61–67.
`Relying on the testimony of Dr. Stone, Petitioner explains how Halbert and
`Amidi describe all of the claim limitations. Id. (citing Ex. 1003).
`
`16
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`
`1. Claim 1
`Claim 1 recites a memory module comprising a plurality of memory
`devices. Petitioner argues that Halbert discloses this feature. Pet. 27–28.
`For example, as Petitioner explains, Halbert teaches “the general component
`arrangement for a memory module 100 in a DIMM form factor. Two ranks
`of memory devices are arranged along the top of the DIMM card: memory
`devices 140A–140H are arranged on the facing side of the module, with
`memory devices 142A–142H arranged directly behind these (see the side
`view of module 100A in FIG. 8).” Pet. 27 (quoting Ex. 1005, 7:31–37;
`citing Figs. 7, 8).
`Claim 1 also recites a controller configured to receive control
`information from a system memory controller and to produce module
`control signals. Petitioner argues that Halbert discloses this feature. Pet.
`28–30. As Petitioner explains, Halbert discloses that the controller 110 is
`configured to receive control signals (“information”) on the ADD/CMD
`input control signal lines, from a “primary memory controller” (“a system
`memory controller”), (see Ex. 1005, 5:28–30, 6:1–4, 6:66–7:2, 8:33–35,
`Figs. 8 (Memory Controller 20), 11 (Memory Controller 200),) and to
`produce a number of control signals, collectively designated “SYNC” (Ex.
`1005, Fig. 4). Pet. 28–29.
`Claim 1 also recites a plurality of circuits configured to receive the
`module control signals, each circuit of the plurality of circuits having a first
`bit width and operatively coupled to at least two corresponding memory
`devices of the plurality of memory devices, the at least two corresponding
`memory devices each having a second bit width smaller than the first bit
`17
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`width. Petitioner argues that Halbert discloses this feature. Pet. 30–34. As
`Petitioner explains, Halbert discloses, in the embodiment of Figure 7,
`“[i]nterface circuit 120 of FIG. 4 is split into two identical interface circuits
`(left circuit 125 and right circuit 130) in FIG. 7, each handling half of the
`data lines.” Pet. 30 (quoting Ex. 1005, 7:37–40). In particular, the “[d]ata
`interface circuit 120 [of FIG. 4] provides for m-bit-wide data transfers
`between the module and the system memory data bus,” id. at 4:49–51, and
`each of the left and right circuits 125 and 130 provides for m/2 bit transfers
`as shown in Figure 7. Id. And, according to Petitioner, “[a] skilled artisan
`would understand this disclosure to mean that each of the L Interface Circuit
`125 and R Interface Circuit 130 (‘a plurality of circuits’) have the same
`structure and functionality as interface circuit 120 of FIG. 4, but are each
`coupled to only half the relevant data signal lines as depicted in FIG. 7.”
`Pet. 31 (citing Ex. 1003 ¶ 120).
`As Petitioner also explains, Halbert discloses L Interface Circuit 125
`and R Interface Circuit 130 each receive the module control signals included
`in the “SYNC” signal in FIG. 7. Pet. 31 (citing Ex. 1005, 7:51–53).
`Claim 1 also recites that each circuit of the plurality of circuits
`comprising at least one write buffer and at least one read buffer. Petitioner
`argues that Halbert discloses this feature. Pet. 34–37. As Petitioner
`explains, each interface circuit 125 and 130 includes a bidirectional buffer
`122, and bi-directional registers 126 and 128. Pet. 34 (citing Ex. 1005,
`4:60–5:14, 7:37–47, Figs. 4, 7; Ex 1003 ¶¶ 120–121). And, according to
`Petitioner, “[a] skilled artisan Halbert to disclose that each of the bi-
`directional buffer 122 and registers 126 and 128 includes a buffer to drive
`18
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`write data into the memory (‘write buffer’) and another buffer to drive read
`data from the memory (‘read buffer’).” Pet. 34–35 (citing Ex. 1005 Fig. 4;
`Ex. 1003 ¶ 120).
`Claim 1 also recites the Selectively Allow Limitation. Petitioner
`argues that Halbert discloses this feature. Pet. 37–39. As noted above,
`Petitioner has not shown a by a preponderance of the evidence that Halbert
`teaches this limitation. However, Petitioner also relies on Amidi to show the
`teaching of this limitation. As Petitioner explains, Amidi discloses a
`transparent four rank memory module, each rank having a corresponding
`chip select signal, and an emulator permitting the module to communicate
`with a memory socket having only two chip select signals. Pet. 61 (citing
`Ex 1019 ¶ 36, Figs. 3, 6A; Ex. 1003 ¶ 161). As Petitioner further explains,
`Amidi teaches using complex programmable logic device (CPLD) 40, or
`other controller circuitry configured to receive memory commands and
`addresses from a system memory controller, to determine which of four
`memory ranks to select for the memory operation based on first and second
`chip select signals and the highest address bits. Id. at 61–62 (citing Ex 1019
`¶¶ 8–12, 41, 43, 50–57, Figs. 3, 6A, 6B; Ex. 1003 ¶¶ 163–164)
`Based on Petitioner’s citations to specific prior art disclosures and
`supporting evidence, we are persuaded that Petitioner sets forth sufficient
`articulated reasoning with rational underpinning to support the legal
`conclusion that it would have been obvious to modify the teachings of
`Halbert with Amidi’s teachings to include rank select functionality. Pet. 64–
`66. For example, Petitioner asserts:
`
`19
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`
`To employ this chip select functionality of Amidi in the
`system of Halbert would have been only the arrangement old
`elements with each performing the same function it had been
`known to perform and yielding no more than one would expect
`from such an arrangement, i.e., the predictable result of operating
`each rank at desired times, and well within the level of ordinary
`skill to achieve. EX1003 ¶¶175-176.
`Moreover, a person of ordinary skill in the art would have
`been motivated to use the chip select functionality of Amidi in
`the system of Halbert to permit the use of lower density, and
`therefore cheaper and more readily available, memory in the
`system of Halbert, while using the existing address and data
`signal lines of Halbert. EX1019, ¶[0008]; see also id., ¶¶ [0002-
`0012]; EX1003 ¶177.
`A skilled artisan would also have been motivated to
`include such prior art chip selection signals in Halbert in order to
`follow the traditional design of memory ranks including the use
`of traditional memory devices and the traditional address signals,
`as Halbert explains. EX1005, 3:55-57; EX1003 ¶178.
`Furthermore, Halbert suggests such a use by disclosing
`that “[m]any other variations on the illustrated embodiments are
`possible. For instance, . . . [t]he illustrated examples also show
`two ranks of memory, but other numbers of ranks are also
`possible.” EX1005, 9:20-26. Skilled artisans at the time would
`have understood that, in case the number of ranks is increased,
`chip/bank select signals would need to be used to activate some
`but not all of the ranks. See, e.g., EX1019 at FIGS. 5, 6A-6B
`(showing logic circuitry to generate chip select signals for
`additional ranks); EX1003 ¶179.
`
`Id.
`
`20
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`Figure 4 of Halbert, reproduced below, is annotated by Petitioner to
`
`explain the combination of Halbert and Amidi.
`
`
`
`As shown in annotated Figure 4, above, Petitioner added two new ranks of
`memory devices—ranks 141 and 143—to Halbert’s memory module 100 to
`increase the total to four ranks of memory devices. Pet. 64. Petitioner also
`added multiplexers 126A and 128A in the data paths between the memory
`device array (including ranks 140, 141, 142 and 143) and registers 126 and
`128; multiplexer 126A selects between ranks 140 and 141 of memory
`devices based on a “Rank Selector” signal from module controller 110, and
`multiplexer 128A selects between ranks 142 and 143 of memory devices
`based on the same “Rank Selector” signal from module controller 110. Id.
`In order to be able to generate this newly-added “Rank Selector” signal,
`Petitioner added functionality from Amidi to Halbert’s module controller
`110, such that the module controller 110 generates the “Rank Selector”
`
`21
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`signal based on the memory address associated with a given read or write
`command, such “Rank Selector” signal causing multiplexers 126A and
`128A to select between the data paths of ranks 140/141 and 142/143,
`respectively. Id. at 62–65. Specifically, according to the Petitioner, the
`operation of the modified memory module of Halbert is explained as:
`Halbert’s module controller 110 would include functionality
`similar to Amidi’s CPLD 40, and would use a high order address
`bit to create the rank select signal, see EX1019, ¶¶ [0049],
`[0052], FIGS. 5, 8, which signal would then be provided to new
`multiplexors 126A and 128A. Based on the rank seector [sic]
`signal the multiplexors would select from among the outputs of
`the ranks of an expanded memory array that included additional
`ranks, Rank 141 and Rank 143. EX1003 ¶170. For example, as
`Dr. Stone explains, during a read memory operation in which
`module controller 110 decodes the high order address bit such
`that the rank seector [sic] signal is output as logic 0, the outputs
`of Ranks 140 and 142 would be selected (by multiplexors 126A
`and 128A, respectively) and provided to bidirectional buffers
`126 and 128, respectively. The outputs of Ranks 141 and 143,
`however, would not be selected and could not be accessed during
`that memory operation . . . . The operation of this modified
`version of Halbert for a write to memory would be similar . . . .
`
`Id. at 64–65.
`As such, in Petitioner’s proposed combination of Halbert and Amidi,
`Halbert’s memory module would have four ranks of memory devices
`included on it, but only two of those ranks would ever be accessed at any
`moment in time due to the operation of newly-added multiplexers 126A and
`128A, which would be controlled by the Petitioner’s newly-added “Rank
`Selector” signal. Thus, this contention would meet the Selectively Allow
`limitation.
`
`22
`
`
`
`IPR2017-00577
`Patent 8,516,185 B2
`
`
`Accordingly, we agree with and adopt Petitioner’s contentions
`regarding claim 1 on this ground.
`2. Patent Owner Response under “Original Theory”
`Patent Owner argues that Dr. Stone created a “new theory” of
`obviousness, with respect specifically to the Selectively Allow limitation, at
`his deposition. PO Resp. 13–21. We address this allegation below.
`Petitioner maintains its “original” theory
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
