Trials@uspto.gov
`571-272-7822
`
`
`Paper 7
`Entered: July 21, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SK HYNIX INC., SK HYNIX AMERICA INC., and
`SK HYNIX MEMORY SOLUTIONS INC.,
`Petitioner,
`
`v.
`
`NETLIST, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-00692
`Patent 8,874,831 B2
`____________
`
`
`Before STEPHEN C. SIU, MATTHEW R. CLEMENTS, and
`SHEILA F. McSHANE, Administrative Patent Judges.
`
`CLEMENTS, Administrative Patent Judge.
`
`
`
`DECISION
`Instituting Inter Partes Review
`35 U.S.C. § 314 and 37 C.F.R. § 42.108
`
`
`
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`IPR2017-00692
`Patent 8,874,831 B2
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`
`INTRODUCTION
`I.
`SK hynix Inc., SK hynix America Inc. and SK hynix memory
`solutions Inc. (“Petitioner”) filed a Petition requesting inter partes review of
`claims 1–15 (“the challenged claims”) of U.S. Patent No. 8,874,831 B2
`(Ex. 1001, “the ’831 patent”). Paper 1 (“Pet.”). Netlist, Inc. (“Patent
`Owner”) filed a Preliminary Response. Paper 6 (“Prelim. Resp.”). We
`review the Petition pursuant to 35 U.S.C. § 314, which provides that an inter
`partes review may be authorized only if “the information presented in the
`petition . . . and any [preliminary] response . . . shows that there is a
`reasonable likelihood that the petitioner would prevail with respect to at least
`1 of the claims challenged in the petition.” 35 U.S.C. § 314(a); 37 C.F.R.
`§ 42.4(a).
`Upon consideration of the Petition and the Preliminary Response, we
`determine that the information presented by Petitioner establishes that there
`is a reasonable likelihood that Petitioner would prevail in showing the
`unpatentability of at least one of the challenged claims of the ’831 patent.
`Accordingly, pursuant to 35 U.S.C. § 314, we institute an inter partes review
`of claims 1–15 of the ’831 patent.
`
`A. Related Proceedings
`The ’831 patent is involved in Netlist, Inc. v. Smart Modular
`Technologies, Inc. et al, Case No. 2:13-cv-02613 (E.D. Cal.). Paper 4, 3.
`Related patents have been asserted in Netlist, Inc. v. SMART Modular
`Technologies, Inc., Case No. 8-13-cv-00996 (C.D. Cal.), Smart Modular
`Technologies, Inc. v. Netlist, Inc., Case No. 4-13-cv-03916 (N.D. Cal.),
`Diablo Technologies, Inc. v. Netlist, Inc., Case No. 4-13-cv-03901 (N.D.
`Cal.), and Netlist, Inc. v. Smart Modular Technologies, Inc., 4-13-cv-05889
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`(N.D. Cal.). Pet. 2. Related patents are also the subject of SanDisk Corp. v.
`Netlist, Inc., Case No. IPR2014-00982 (PTAB) (institution denied), SanDisk
`Corp. v. Netlist, Inc., Case No. IPR2014-00994 (PTAB) (institution denied),
`Smart Modular Technologies, Inc. v. Netlist, Inc., Case No. IPR2014-01370
`(PTAB) (institution denied); Smart Modular Technologies, Inc. v. Netlist,
`Inc., Case No. IPR2014-01371 (PTAB) (institution denied), SK hynix Inc., et
`al. v. Netlist, Inc., Case No. IPR2017-00587 (PTAB) (instituted June 22,
`2017), and SK hynix Inc., et al. v. Netlist, Inc., Case No. IPR2017-00649
`(PTAB). Pet. 2; Paper 4, 3.
`
`B. The ’831 patent
`The ’831 patent, titled “Flash-Dram Hybrid Memory Module,” issued
`October 28, 2014, from U.S. Patent Application No. 13/559,476. Ex. 1001
`at [54], [45], [21]. The ’831 patent generally relates to a memory module
`with a non-volatile memory, a volatile memory, and a data manager through
`which the volatile memory and non-volatile memory may exchange data,
`and a controller to receive read/write commands from a memory controller
`hub (“MCH”) and transfer data between any two or more of the MCH,
`volatile memory, and non-volatile memory. Id. at Abstract. Figure 4A is
`reproduced below.
`
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`Figure 4A is a block diagram of a Flash-DRAM hybrid dynamic random
`access memory dual in-line memory module (DIMM). In this embodiment,
`volatile memory subsystem 406 (e.g. DRAM) is used as a data buffer such
`that data from Flash memory 402 is transferred to DRAM 406 at the Flash
`access speed, and buffered or collected into DRAM 406, which then
`transfers the buffered data to the MCH based on the access time of DRAM.
`Id. at 9:15–21. Similarly, when the MCH transfers data to DRAM 406,
`controller 404 manages the data transfer from DRAM 406 to Flash 402. Id.
`at 9:21–23.
`Figure 5 is reproduced below.
`
`
`Figure 5A is a block diagram of memory module 500 in accordance with
`certain embodiments. Ex. 1001, 7:7–8. As shown in Figure 5, memory
`module 500 includes two on-module intermediary components: controller
`(CDC) 502 and data manager (DMgr) 504. Id. at 10:35–46. These
`components “manage the interface between a non-volatile memory
`subsystem such as a Flash 506, a volatile memory subsystem such as a
`DRAM 508, and a host system represented by MCH 510.” Id. at 10:49–53.
`“In certain embodiments, CDC 502 controls the read/write access to/from
`Flash memory 506 from/to DRAM memory 508, and to/from DRAM
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`memory from/to MCH 510.” Id. at 10:54–56. “In certain embodiments and
`in response to communication from CDC 502, DMgr 504 provides a variety
`of functions to control data flow rate, data transfer size, data buffer size, data
`error monitoring or data error correction.” Id. at 11:18–21.
`Figure 6 is reproduced below.
`
`
`Figure 6 is a block diagram showing some details of data manager 504. Ex.
`1001, 7:11–12. “In certain embodiments, DMgr 504 also functions as a bi-
`directional data transfer fabric.” Id. at 12:1–3. “For example, DMgr 504
`may have more than 2 sets of data ports facing the Flash 506 and the DRAM
`508.” Id. at 12:3–5. “Multiplexers 611 and 612 provide controllable data
`paths from any one of the DRAMs 508(1) and 508(2) (DRAM-A and
`DRAM-B) to any one of the MCH 510 and the Flash 506.” Id. at 12:5–8.
`“Similarly multiplexers 621 and 622 provide controllable data paths from
`any one of the MCH and the Flash memory to any one of the DRAMs
`508(1) and 508(2) (DRAM-A and DRAM-B).” Id. at 12:8–11.
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`
`C. Illustrative Claim
`Of the challenged claims, claims 1 and 7 are independent, claims 2–6
`depend, directly or indirectly, from claim 1, and claims 8–15 depend,
`directly or indirectly, from claim 7. Independent claim 1 is illustrative of the
`challenged claims and is reproduced below:
`1.
`A memory module couplable to a memory controller of a
`host system, comprising:
`a non-volatile memory subsystem;
`a data manager coupled to the non-volatile memory subsystem;
`a volatile memory subsystem coupled to the data manager and
`operable to exchange data with the non-volatile memory
`subsystem by way of the data manager; and
`a controller operable to receive commands from the memory
`controller and to direct (i) operation of the non-volatile memory
`subsystem, (ii) operation of the volatile memory subsystem, and
`(iii) transfer of data between any two or more of the memory
`controller, the volatile memory subsystem, and the non-volatile
`memory subsystem based on at least one received command
`from the memory controller, wherein:
`at least one of the volatile and non-volatile memory subsystems
`comprises one or more memory segments, each memory segment
`comprising at least one memory circuit, memory device, or
`memory die, and
`the data manager is configured as a bi-directional data transfer
`fabric having two or more sets of data ports, a first set of data
`ports of the two or more sets of data ports is coupled to the
`volatile memory subsystem, a second set of data ports of the two
`or more sets of data ports is coupled to the non-volatile memory
`subsystem, the two or more sets of data ports being operable by
`the data manager to transfer data to or from one or more memory
`segments of the volatile or non-volatile memory subsystems, the
`data manager further including a data buffer for buffering data
`delivered to or from the non-volatile memory subsystem, and a
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`data format module configured to format data to be transferred
`between any two or more of the memory controller, the volatile
`memory subsystem, and the non-volatile memory subsystem
`based on control information received from the controller.
`Ex. 1001, 17:44–18:13.
`
`D. Evidence Relied Upon
`Petitioner relies upon the following prior art references:
`US 2010/0110748 A1 May 6, 2010
`US 6,065,092
`May 16, 2000
`US 2003/0028733 A1 Feb. 6, 2003
`US 2006/0212651 A1 Sept. 21, 2006
`US 2007/0136523 A1 June 14, 2007
`US 2005/0273548 A1 Dec. 8, 2005
`
`Best
`Roy
`Tsunoda
`Ashmore
`Bonella
`Roohparvar
`
`Ex. 1006
`Ex. 1008
`Ex. 1009
`Ex. 1011
`Ex. 1013
`Ex. 1019
`
`Pet. 3. Petitioner also relies upon the Declaration of Ron Maltiel (“Maltiel
`Decl.”) (Ex. 1003).
`
`E. Asserted Grounds of Unpatentability
`Petitioner asserts that the challenged claims are unpatentable based on
`the following grounds (Pet. 3):
`Reference(s)
`Best
`Best and Roy
`Best and Tsunoda, with or
`without Roy
`Best and Roohparvar, with or
`without Roy
`Best and Bonella, with or
`without Roy
`Best, Bonella, and Ashmore,
`with or without Roy
`
`Basis Claim(s) challenged
`§ 102 1–14
`§ 103 1–14
`§ 103 2 and 8
`
`§ 103 5 and 12–14
`
`§ 103 15
`
`§ 103 15
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`Petitioner also relies upon the Declaration of Ron Maltiel. Ex. 1003
`(“Maltiel Decl.”).
`
`II. ANALYSIS
`A. Claim Construction
`In an inter partes review, a claim in an unexpired patent shall be given
`its broadest reasonable construction in light of the specification of the patent
`in which it appears. 37 C.F.R. § 42.100(b). Under the broadest reasonable
`construction standard, claim terms are given their ordinary and customary
`meaning, as would be understood by one of ordinary skill in the art in the
`context of the entire disclosure. In re Translogic Tech., Inc., 504 F.3d 1249,
`1257 (Fed. Cir. 2007). Any special definition for a claim term must be set
`forth in the specification with reasonable clarity, deliberateness, and
`precision. In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994). We must be
`careful not to read a particular embodiment appearing in the written
`description into the claim if the claim language is broader than the
`embodiment. See In re Van Geuns, 988 F.2d 1181, 1184 (Fed. Cir. 1993).
`Only terms that are in controversy need to be construed, and then only to the
`extent necessary to resolve the controversy. Vivid Techs., Inc. v. Am. Sci. &
`Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
`Petitioner proposes constructions for “bi-directional data transfer
`fabric,” “set of data ports,” “format data,” and “operable at a . . . clock
`frequency.” Pet. 10–14. Patent Owner argues that no construction is
`necessary for “bi-directional data transfer fabric,” “set of data ports,” and
`“operable at a . . . clock frequency.” Prelim. Resp. 21–24. Patent Owner
`proposes a different construction of “format data,” and offers constructions
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`for the terms “memory module,” “memory address mapping,” “address
`domain conversion,” and “data width modulation.” Id. at 21, 23–28. On
`this record, and for purposes of this Decision, we determine that only the
`term “memory module” requires express construction.
`1. “memory module” (claim 1)
`Petitioner does not propose a construction for “memory module.”
`Patent Owner contends that “memory module” should be construed to mean
`“a carrier that contains one or more memory chips.” Prelim. Resp. 21.
`Specifically, Patent Owner contends that a “memory module” is a removable
`circuit board and does not refer to an integrated circuit by itself. Id. (citing
`Ex. 2001 (Microsoft Computer Dictionary, 5th ed.), 334 (“memory module
`n. A removable circuit board, cartridge, or other carrier that contains one or
`more RAM memory chips.”); see also Prelim. Resp. 32–33 (arguing that
`Best’s integrated circuit package is not a “memory module” because it is not
`a circuit board). Patent Owner also relies upon our construction of “memory
`module” in a prior proceeding involving a different patent to mean “a carrier
`that contains one or more memory chips.” Id. (citing Diablo Technologies,
`Inc. v. Netlist, Inc., Case IPR2014-00882 (PTAB Dec. 14, 2015) (Paper 33
`(“882 FWD”), 8–11 (construing “memory module” as used in U.S. Patent
`No. 7,881,150 B2) (“the ’150 patent”)).
`The ’831 patent does not define a “memory module.” The ’831 patent
`depicts a memory module 500 in Figures 5A and 5B, and describes how
`“[i]n certain embodiments, memory module 500 is a Flash-DRAM hybrid
`memory module that has the DIMM (dual-inline memory module) form
`factor” (Ex. 1001, 10:28–31), but the ’831 patent also expressly
`contemplates other form factors (see, e.g., id. at 10:32–34 (“it is to be
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`understood that in both structure and operation [memory module 500] may
`be different from the FDHDIMM discussed above and described with
`reference to FIGS. 4A and 4B”), 10:46–49 (“While the DIMM form factor
`will predominate the discussion herein, it should be understood that this is
`for illustrative purposes only and memory systems using other form factors
`are contemplated as well.”).
`Moreover, our construction of “memory module” in IPR2014-00882
`is informative, but not dispositive, because the ’150 patent has a different
`Specification than the ’831 patent, and our construction in that case was
`based, in part, on disclosures in the ’150 patent that are not found in the ’831
`patent. See, e.g., 882 FWD, 10 (citing teachings of a printed circuit board on
`which memory devices are mounted). The ’831 patent, in contrast, does not
`use the terms “printed circuit board” or “circuit board” even once, much less
`limit explicitly a “memory module” to a removable printed circuit board, as
`Patent Owner suggests. Because the ’831 patent is open-ended regarding the
`form factor that a “memory module” may take, and because it makes no
`mention of a printed circuit board, much less a removable printed circuit
`board, we also are not persuaded by Patent Owner’s extrinsic evidence (Ex.
`2001) such that we should import such a limitation into our construction of
`this term.
`On this record, and for purposes of this decision, we construe
`“memory module” to mean “a carrier that contains one or more memory
`chips,” where “carrier” encompasses an integrated circuit package.
`
`B. Claims 1–14: Anticipation by Best
`Petitioner argues that the claims 1–14 are unpatentable under
`35 U.S.C. § 102(e) as anticipated by Best. Pet. 11–35. In light of the
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`arguments and evidence of record, we are persuaded that Petitioner has
`established a reasonable likelihood that the claims 1–14 are unpatentable as
`anticipated by Best.
`1. Best (Ex. 1006)
`Best is directed to a hybrid volatile and non-volatile memory device.
`Ex. 1006, Abstract. Specifically, Best discloses “[a]composite, hybrid
`memory device including a first storage die having an array of volatile
`storage cells and a second storage die having an array of non-volatile storage
`cells disposed within an integrated circuit package.” Id. “The hybrid
`memory device includes a shared interface circuit to receive memory access
`commands directed to the first storage die and the second storage die and to
`convey read and write data between an external data path and the first and
`second storage dice.” Id.
`Figure 2 of Best is reproduced below.
`
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`Figure 2 illustrates an embodiment of a hybrid, composite memory device
`with shared interface circuitry, volatile memory, and non-volatile memory.
`Id. ¶ 17. “[T]he shared interface circuitry includes an external request
`interface 125, external data interface 133, command decoder 122, address
`queue 135, DRAM control circuit 129, Flash control circuit 137, and data
`control/steering circuit 131.” Id. “[I]ncoming control signals and addresses
`. . . are received in the external request interface 125 via control/address
`(CA) path 126, reformatted as necessary (e.g., deserialized to form a parallel
`command word and one or more address values) and then forwarded to the
`command decoder 122.” Id. “The command decoder 122 in turn forwards
`address to the address queue 135 and stores memory access commands.” Id.
`“[M]emory access operations may be automatically directed to either the
`volatile storage die or non-volatile storage die according to the memory
`address to be accessed.” Id. “[C]ommand decoder 122 outputs, from the
`head of the command queue, an enable signal and corresponding memory
`access control signals to the DRAM control circuit 129 and NV control
`circuit 137.” Id. ¶ 18. “[D]ata control/steering circuit 131 is used to control
`the transfer of data between a shared internal data bus and dedicated internal
`data buses associated with the volatile and non-volatile storage dice,
`respectively.” Id. ¶ 20.
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`Figure 3 of Best is reproduced below.
`
`
`Figure 3 illustrates an embodiment of a data control/steering circuit 150 that
`may be used to implement the data control/steering circuit 131 of Figure 2.
`Id. ¶ 21. “[D]ata control circuit 151 receives control signals from the
`command decoder that indicate the direction of data flow during a memory
`access operation (read or write) and whether the volatile or non-volatile
`storage die is the target of the memory access.” Id.
`2. Independent claims 1 and 7
`Claim 1 recites “[a] memory module couplable to a memory controller
`of a host system.” Petitioner relies upon Best’s disclosure of “a ‘hybrid
`composite memory device having non-volatile and volatile memories
`implemented in distinct integrated circuit (IC) dice that are packaged
`together and accessed through a shared interface.’” Pet. 20 (quoting Ex.
`1006 ¶ 12). Claim 1 further recites “a non-volatile memory subsystem.”
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`Petitioner relies upon Best’s disclosure of a Flash memory. Pet. 21. Claim 1
`further recites “a data manager coupled to the non-volatile memory
`subsystem.” Petitioner relies upon Best’s data control/steering circuit in
`combination with the external interface. Pet. 21–22 (citing Ex. 1006, Figure
`3). Claim 1 further recites “a volatile memory subsystem.” Petitioner relies
`upon Best’s disclosure of a DRAM. Pet. 22–23. Claim 1 further recites “a
`controller.” Petitioner relies upon Best’s command decoder 122, which
`receives “incoming control signals and addresses” and directs operation of
`the volatile and non-volatile memories by “output[ting] . . . an enable signal
`and corresponding memory access control signals to the DRAM control
`circuit . . . and NV control circuit,” and transfers data between the memories
`and memory controller. Pet. 23–24 (citing Ex. 1006 ¶¶ 17–19, 21, 29).
`Claim 1 further recites “at least one of the volatile and non-volatile memory
`subsystems comprises one or more memory segments.” Petitioner relies
`upon Best’s disclosure that “the volatile and non-volatile memories [are]
`implemented by a DRAM die 103 and Flash memory die 101, respectively,”
`each of which, according to Petitioner, is a memory segment. Pet. 24–25.
`Claim 1 further recites
`the data manager is configured as a bi-directional data transfer
`fabric having two or more sets of data ports, a first set of data ports
`of the two or more sets of data ports is coupled to the volatile
`memory subsystem, a second set of data ports of the two or more
`sets of data ports is coupled to the non-volatile memory subsystem,
`the two or more sets of data ports being operable by the data
`manager to transfer data to or from one or more memory segments
`of the volatile or non-volatile memory subsystems.
`Petitioner relies upon Best’s disclosure of an interface to the primary volatile
`data path 142 between data control/steering circuit 150 and DRAM 101 (“a first
`set of data ports . . . coupled to the volatile memory subsystem”), and of an
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`interface to primary non-volatile data path 144 between data control steering
`circuit 150 and NV memory 103 (“a second set of data ports . . . coupled to the
`non-volatile memory subsystem”). Pet. 25–26. Petitioner contends that each
`set of interconnections is “bi-directional” because data can flow in either
`direction, and illustrates the point with an annotated version of Figure 3,
`reproduced below:
`
`
`
`Finally, claim 1 recites
`the data manager further including a data buffer for buffering data
`delivered to or from the non-volatile memory subsystem, and a data
`format module configured to format data to be transferred between
`any two or more of the memory controller, the volatile memory
`subsystem, and the non-volatile memory subsystem based on
`control information received from the controller.
`Petitioner relies upon Best’s disclosure of “non-volatile-storage-die
`interface buffer 161” as the recited “data buffer” (Pet. 27–28), and relies
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`upon Best’s disclosure of logic for serializing/deserializing within data
`steering/control circuit and the external data interface as the recited “data
`format module” (id. at 28–30). We are persuaded that Petitioner’s
`citations support its contentions.
`We also are persuaded that Petitioner’s citations support its
`contentions with respect to claim 7, for which Petitioner relies upon largely
`the same disclosures in Best (Pet. 38–43).
`Patent Owner argues that Best does not disclose a “memory module”
`because it is implemented on a single integrated circuit package—i.e., a
`single chip. Prelim. Resp. 32–33. This argument is not persuasive,
`however, because it is based upon Patent Owner’s proposed construction of
`“memory module,” which we do not adopt. Because our broadest
`reasonable construction of “memory module,” as discussed above,
`encompasses an integrated circuit package, we are persuaded that Best
`discloses this limitation.
`Patent Owner also argues that “neither [Best’s interface to the single
`volatile data path 142 nor its interface to the single nonvolatile data path 144
`is] a ‘set of data ports’ because each interface is to a single data bus.”
`Prelim. Resp. 33–34. This argument also is not persuasive. Patent Owner
`argues that no construction is necessary for the phrase “set of data ports.”
`Prelim. Resp. 23. The claims require that the “first set of data ports” is
`“coupled to the volatile memory subsystem,” and that the “second set of data
`ports” is “coupled to the non-volatile memory subsystem.” The ’831 patent
`explicitly describes non-volatile memory subsystem 506 as coupled to a
`single data bus, i.e., data bus 606. Ex. 1001, Fig. 6, 12:58 (“wide data bus
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`606 coupled to the Flash memory 506”). As a result, we are not persuaded
`that “set of data ports” excludes a single data bus, as disclosed by Best.
`3. Dependent claims 2–6 and 8–14
`We have reviewed Petitioner’s explanations and supporting evidence
`regarding dependent claims 2–6 and 8–14, and find them persuasive. See
`Pet. 30–49. Patent Owner does not argue separately these claims. Based on
`the record before us, Petitioner has demonstrated a reasonable likelihood that
`it would prevail on its assertion that claims 2–6 and 8–14 are anticipated by
`Best.
`4. Conclusion
`On this record, we are persuaded that Petitioner has established a
`reasonable likelihood that it would prevail in showing that claims 1–14 are
`unpatentable as anticipated by Best.
`
`C. Claim 1–14: Obviousness over Best1
`As discussed above, we are persuaded that Petitioner has established a
`reasonable likelihood that it would prevail in showing that claims 1–14 are
`unpatentable as anticipated by Best. Inasmuch as “anticipation is the
`epitome of obviousness” (In re McDaniel, 293 F.3d 1379, 1385 (Fed. Cir.
`2002)) and because there is no evidence of objective indicia of non-
`obviousness on the record, we determine that Petitioner has also established
`a reasonable likelihood of prevailing in showing that claims 1–14 would
`have been obvious over Best.
`
`1 Although Petitioner challenges claims 1–14 as obvious over “Best in view
`of Roy” (Pet. 3), its other obviousness challenges are “with or without Roy”
`(id.). We, therefore, interpret the Petition to allege that claims 1–14 also are
`obvious over Best alone.
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`D. Claims 1–14: Obviousness over
`Best and Roy
`Petitioner argues that claims 1–14 are unpatentable under
`35 U.S.C. § 103(a) as obvious over the combination of Best and Roy. Pet.
`49–53. In light of the arguments and evidence of record, we are persuaded
`that Petitioner has established a reasonable likelihood that the claims 1–14
`are unpatentable as obvious over the combination of Best and Roy.
`1. Roy (Ex. 1008)
`Roy is directed generally to an “independent and cooperative
`multichannel memory architecture” that includes a plurality of independent
`channels between a master device and one or more memory clusters. Ex.
`1008, Abstract. Figure 1 of Roy is reproduced below.
`
`Figure 1 of Roy is a system level block diagram of a multichannel memory
`architecture disclosed in Roy. Id. at 7:59–60. As shown, “memory device
`20 further includes multiplexer units 241–4 which couple individual ones of a
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`plurality of the channels to one or more of the memory clusters 30.” Id. at
`11:52–54.
`2. Claims 1 and 7
`Independent claims 1 and 7 recite “a bi-directional data transfer fabric
`[having/with] two or more sets of data ports.” Petitioner argues that, if this
`phrase is construed to require two or more independent read/write paths to
`each of the volatile and non-volatile memory subsystems, such a feature was
`taught by Roy. Pet. 49–51. In particular, Petitioner relies upon Roy’s
`teaching of multiplexers 241–4 (“a bi-directional data transfer fabric”), their
`interfaces to buses 231–4 (“two or more sets of data ports”), some of which
`are coupled to memory cluster 303 (“a first set . . . coupled to”) and others of
`which are coupled to memory cluster 30K (“a second set . . . coupled to”).
`Pet. 50–51. Petitioner also annotates Figure 1 of Roy to indicate
`multiplexers (red), interfaces (green), and memory clusters to which they are
`coupled (yellow):
`
`Id. at 50.
`
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`With respect to why a person of ordinary skill in the art would have
`modified Best in view of Roy, Petitioner argues:
`One of ordinary skill in the art would have been motivated
`to implement this architecture for all the reasons Roy describes,
`including allowing independent and simultaneous transactions,
`Ex. 1008, 7:37-40, and increased performance by providing a
`wide effective channel, id., 7:45-49; Ex. 1003, ¶173. Roy also
`teaches that a multichannel architecture provides substantial
`flexibility. Ex. 1008, 9:30-42; Ex. 1003, ¶173.
`Roy discloses that “nearly identical address and control
`information” can be applied to each channel such that
`“[s]ubsequent transfer[s] of data on each of these channels can
`be synchronized to provide an effectively wider channel.” Ex.
`1008, 10:28-32. This provides particular motivation to combine
`with Best in light of Best’s disclosure that “multiple non-volatile
`storage dice and/or multiple volatile storage dice may be …
`selected … based on incoming address and/or control signals.”
`Ex. 1006, ¶15; Ex. 1003, ¶174.
`Best suggests such a modification through his disclosure
`of overlapping and pipelined memory operations. Ex. 1006, ¶18.
`One of ordinary skill would understand that multiple channels
`allow for further overlapping or pipelining of operations, such as
`allowing Best to write data from volatile to non-volatile memory
`as part of the “Shadow Mode” operation while allowing the host
`to simultaneously write data to volatile memory, thus improving
`the operation and responsiveness of the system. Ex. 1003, ¶175.
`Modifying Best to use a multichannel architecture such as
`Roy’s would have been an arrangement of old elements (Best’s
`hybrid memory, Roy’s multichannel architecture) with each
`performing the same function it had been known to perform and
`yielding no more than what one would expect from such an
`i.e., Best’s
`arrangement,
`system with a multichannel
`architecture. Ex. 1003, ¶176. Multichannel architectures were
`known in the art, and using one in Best would have involved only
`routine skill to implement the functionality described by Roy. Id.
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`Such a modification would have therefore been obvious. Id.,
`¶¶176, 240.
`Pet. 56–53. On this record, we are persuaded that Petitioner has provided an
`articulated reasoning with some rational underpinning that would support the
`legal conclusion of obviousness. See KSR Int’l Co. v. Teleflex Inc., 550 U.S.
`398, 418 (2017) (citing In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006)).
`Additionally, Patent Owner relies upon the same argument as for
`Ground 1—i.e., that Best does not teach a “memory module”—and argues
`that the Petition fails to show that Roy teaches a “memory module.” Prelim.
`Resp. 35. We are not persuaded by that argument for the reasons discussed
`above.
`3. Dependent claims 2–6 and 8–14
`For dependent claims 2–6 and 8–14, Petitioner relies upon its
`explanations and supporting evidence from Ground 1. See Pet. 49–53.
`Patent Owner does not argue separately dependent claims 2–6 and 8–14.
`Based on the record before us, Petitioner has demonstrated a reasonable
`likelihood that it would prevail on its assertion that claims 2–6 and 8–14
`would have been obvious over Best and Roy.
`4. Conclusion
`On this record, we are persuaded that Petitioner has established a
`reasonable likelihood that it would prevail in showing that claims 1–14 are
`unpatentable as obvious over the combination of Best and Roy.
`
`Claim 15: Obviousness over
`E.
`Best, Mills, and Bonella, with or without Roy
`Petitioner argues that claim 15 is unpatentable under
`35 U.S.C. § 103(a) as obvious over Best, Mills, and Bonella, with or without
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`Roy.2 Pet. 57–68. In light of the arguments and evidence of record, we are
`persuaded that Petitioner has established a reasonable likelihood that the
`claim 15 is unpatentable as obvious over the combination of Best and
`Bonella, and over the combination of Best, Roy, and Bonella.
`1. Bonella (Ex. 1013)
`Bonella describes “A memory module including a volatile memory, a
`non-volatile memory, and a controller that provides address, data, and
`control interfaces to the memories and to a host system.” Ex. 1013,
`Abstract. Bonella teaches that, “[t]he memory module controller . . . is
`‘Power State Aware.’” Id. ¶ 45. At “Power Level 4,” Bonella’s controller
`“reduces power by limiting the DRAM performance and the PCIe
`transaction performance.” Id. ¶ 48. Bonella teaches that “[r]education of
`power in the DRAM can be accomplished” by “reduc[ing] the frequency in
`which the DRAM is operating,” which “reduces power and, in general,
`produces no noticeable decrease in system performance.” Id. ¶ 49.
`2. Claim 15
`Claim 15 recites
`operating the volatile memory subsystem at a first clock
`frequency when the memory module is in a first mode of
`operation in which data is communicated between the volatile
`memory subsystem and the memory controller;
`Ex. 1001, 20:12–15. Petitioner relies upon Best’s teaching of a conventional
`DRAM, which one of ordinary skill in the art would have understood
`operates at a first clock frequency. Pet. 58–60.
`
`
`2 Although Petitioner does not include Mills (Ex. 1010) explicitly in its
`ground (Pet. 3), we include it here because Petitioner’s analysis relies upon
`it (id. at 61–64) for teaching part of a limitation.
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`Claim 15 further recites
`operating the non-volatile memory subsystem at a second clock
`frequency when the memory module is in a second mode of
`operation in which data is communicated between the volatile
`memory subsystem and the non-volatile memory subsystem; and
`Ex. 1001, 20:16–20. Petitioner concedes that Best does not explicitly
`disclose this limitation, but relies upon Mills’ teaching