Paper 10
`Trials@uspto.gov
`571-272-7822 Entered: August 18, 2017
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`
`AMAZON.COM, INC. and AMAZON WEB SERVICES, INC.,
`Petitioner,
`
`v.
`
`BROADCOM CORPORATION,
`Patent Owner.
`____________
`
`Case IPR2017-00814
`Patent 6,766,389 B2
`____________
`
`
`
`
`
`
`Before JAMES B. ARPIN, BARBARA A. PARVIS, and
`DANIEL J. GALLIGAN, Administrative Patent Judges.
`
`GALLIGAN, Administrative Patent Judge.
`
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314(a) and 37 C.F.R. § 42.108
`
`
`
`Trials@uspto.gov
`571-272-7822 Entered: August 18, 2017
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`
`AMAZON.COM, INC. and AMAZON WEB SERVICES, INC.,
`Petitioner,
`
`v.
`
`BROADCOM CORPORATION,
`Patent Owner.
`____________
`
`Case IPR2017-00814
`Patent 6,766,389 B2
`____________
`
`
`
`
`
`
`Before JAMES B. ARPIN, BARBARA A. PARVIS, and
`DANIEL J. GALLIGAN, Administrative Patent Judges.
`
`GALLIGAN, Administrative Patent Judge.
`
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314(a) and 37 C.F.R. § 42.108
`
`
`
`
`IPR2017-00814
`Patent 6,766,389 B2
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`I. INTRODUCTION
`
`Amazon.com, Inc. and Amazon Web Services, Inc. (collectively,
`“Petitioner”) filed a Petition (“Pet.”) requesting inter partes review of claims
`1–19 of U.S. Patent No. 6,766,389 B2 (“the ’389 patent,” Ex. 1001).
`Paper 2. Broadcom Corporation (“Patent Owner”) filed a Preliminary
`Response. Paper 7 (“Prelim. Resp.”). Pursuant to 37 C.F.R. § 42.4(a), we
`have authority to determine whether to institute review.
`The standard for instituting an inter partes review is set forth in
`35 U.S.C. § 314(a), which provides that an inter partes review may not be
`instituted unless the information presented in the Petition shows “there is a
`reasonable likelihood that the petitioner would prevail with respect to at
`least 1 of the claims challenged in the petition.”
`After considering the Petition, the Preliminary Response, and
`associated evidence, we determine that Petitioner has demonstrated a
`reasonable likelihood of prevailing in showing the unpatentability of claims
`1–3, 7, and 8. Thus, we institute an inter partes review as to these claims.
`
`The ’389 Patent and Illustrative Claims
`A.
`The ’389 patent is directed to a system on a chip for networking.
`Ex. 1001, 1:31. The ’389 patent discloses:
`[A]n integrated circuit for a network device is contemplated. The
`integrated circuit includes at least one processor coupled to an
`interconnect; a cache coupled to the interconnect; a memory
`controller coupled to the interconnect; and one or more
`input/output (I/O) devices for networking applications. The at
`least one processor, the cache, the memory controller, the
`interconnect, and the one or more I/O devices are integrated onto
`the integrated circuit.
`
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`Moreover, an integrated circuit for a network device is
`contemplated,
`including at
`least one processor and an
`input/output (I/O) device capable of caching data. The processor
`and the I/O device are integrated onto the integrated circuit.
`Coherency is enforced between the processor and the I/O device.
`Ex. 1001, 1:46–59.
`Claims 1 and 7 are independent claims. Claims 2–6 depend directly
`or indirectly from claim 1, and claims 8–19 depend directly or indirectly
`from claim 7. Claims 1, 4, and 7 are illustrative and are reproduced below:
`1.
`An integrated circuit comprising:
`at least one processor coupled to a bus;
`a cache memory coupled to the bus to cache data for the
`integrated circuit;
`a memory controller coupled to the bus;
`a bridge circuit coupled to the bus: and
`at least one interface circuit to couple to a network external
`to the integrated circuit, the at least one interface circuit also
`coupled to the bridge circuit to allow the bridge circuit to initiate
`transactions onto the bus for data transfer between the bus and
`the at least one interface circuit.
`
`
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`The integrated circuit as recited in claim 2 wherein the
`4.
`bridge circuit to operate to maintain cache coherency for the
`integrated circuit.
`
`In a network device, an integrated circuit containing a
`7.
`system thereon, comprising:
`at least one processor coupled to a bus;
`a cache memory coupled to the bus to cache data for the
`integrated circuit;
`a memory controller coupled to the bus;
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`a plurality of interface circuits to couple to different
`networks to allow the network device to operate in more than one
`type of network; and
`at least one bridge circuit coupled to the bus to operate as
`a bridge between the bus and the plurality of interface circuits to
`initiate transactions between the plurality of interface circuits and
`the bus.
`
`References
`B.
`Petitioner relies upon the following references:
`Young
`US 5,768,548
`June 16, 1998 Ex. 1007
`Shigeeda
`US 5,778,425
`July 7, 1998
`Ex. 1004
`“Fast Cache and Bus Power Estimation for Parameterized
`Ex. 1006
`System-on-a-Chip Design,” T. D. Givargis, F. Vahid, J.
`Henkel (“Givargis”), Proceedings of Design, Automation and
`Test Conference and Exhibition 2000, March 27–30, 2000,
`ISBN 0-7695-0537-6, at pp. 333–339
`“Broadcom, Cisco, Nvidia, Sun Among First Adopters of
`AMD’s New HyperTransport Technology,” Advanced Micro
`Devices, February 14, 2001 (“HT Press Release”)
`
`Ex. 1008
`
`
`
`Asserted Grounds of Unpatentability
`C.
`Petitioner challenges claims 1–19 of the ’389 patent based on the
`asserted grounds of unpatentability set forth in the table below. Pet. 3.
`Reference(s)
`Basis
`Claim(s) Challenged
`Shigeeda
`§ 102(b)
`1–5, 7, 9, and 13
`Shigeeda alone or in combination
`§ 103(a)
`5–7, 9–11, and 13
`with Givargis
`Shigeeda and HT Press Release
`Shigeeda, alone or in combination
`with Givargis, and also in
`combination with HT Press Release
`
`8
`8 and 12
`
`§ 103(a)
`§ 103(a)
`
`
`
`4
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`Reference(s)
`Shigeeda, alone or in combination
`with Givargis, and also in
`combination with Young
`Shigeeda, alone or in combination
`with Givargis, and also in
`combination with Young and HT
`Press Release
`
`Basis
`§ 103(a)
`
`Claim(s) Challenged
`14–18
`
`§ 103(a)
`
`19
`
`II. ANALYSIS
`Claim Construction
`A.
`In an inter partes review, “[a] claim in an unexpired patent that will
`not expire before a final written decision is issued shall be given its broadest
`reasonable construction in light of the specification of the patent in which it
`appears.” 37 C.F.R. § 42.100(b). In determining the broadest reasonable
`construction, we presume that claim terms carry their ordinary and
`customary meaning. See In re Translogic Tech., Inc., 504 F.3d 1249, 1257
`(Fed. Cir. 2007). This presumption may be rebutted when a patentee, acting
`as a lexicographer, sets forth an alternate definition of a term in the
`specification with reasonable clarity, deliberateness, and precision. In re
`Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994).
`The parties disagree as to the meaning of the term “Level 2 cache,”
`which is recited in dependent claim 3. Pet. 4; Prelim. Resp. 21–24. Based
`on the record and for purposes of this Decision, we determine that neither
`this term nor any other term in the claims of the ’389 patent requires express
`construction at this time.
`
`Principles of Law
`B.
`To establish anticipation, each and every element in a claim, arranged
`as recited in the claim, must be found in a single prior art reference. Net
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`MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1371 (Fed. Cir. 2008).
`While the elements must be arranged or combined in the same way as in the
`claim, “the reference need not satisfy an ipsissimis verbis test,” i.e., identity
`of terminology is not required. In re Gleave, 560 F.3d 1331, 1334 (Fed. Cir.
`2009).
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
`differences between the claimed subject matter and the prior art are such that
`the subject matter, as a whole, would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
`subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007). The question of obviousness is resolved on the basis of underlying
`factual determinations including: (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art;
`(3) the level of ordinary skill in the art;1 and (4) objective evidence of
`nonobviousness.2 Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`
`Anticipation by Shigeeda
`C.
`(Claims 1–5, 7, 9, and 13)
`Petitioner contends Shigeeda anticipated claims 1–5, 7, 9, and 13 and
`relies upon the Declaration of Jon B. Weissman, Ph.D. (Ex. 1003) to support
`its positions. Pet. 3, 17–53.
`
`
`1 Petitioner proposes an assessment of the level of ordinary skill in the art.
`Pet. 16–17; see Ex. 1003 ¶ 46. Petitioner’s declarant, Dr. Weissman,
`exceeds this assessed level. Ex. 1003 ¶¶ 3–9, 46–49. At this time, Patent
`Owner does not propose an alternative assessment. For purposes of this
`Decision, and to the extent necessary, we adopt Petitioner’s assessment.
`2 Patent Owner does not present arguments or evidence of such secondary
`considerations in the Preliminary Response.
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`1. Independent Claim 1
`a. Petitioner’s Contentions
`Independent claim 1 is directed to “[a]n integrated circuit comprising”
`various recited components. Petitioner contends Shigeeda discloses that its
`microprocessor unit (MPU) and peripheral processing unit (PPU) together
`incorporate all of the components recited in claim 1. Pet. 17–18. Petitioner
`further contends Shigeeda discloses integrating these components into a
`single chip, i.e., one “integrated circuit.” Pet. 18; see Ex. 1005, 11:57–59
`(“In still other embodiments the MPU 102, PPU 110 and PCU [(peripheral
`control unit)] 112 are integrated into only one single-chip device.”).
`Figure 9 of Shigeeda is a block diagram of MPU 102. Ex. 1005,
`3:34–35. The Petition includes an annotated version of Figure 9, reproduced
`below, illustrating what components of Shigeeda Petitioner alleges disclose
`various recited elements of the claims.
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`Pet. 27. According to Petitioner, the figure reproduced above is an
`annotated version of Figure 9 of Shigeeda. Id. at 26–27.
`Petitioner contends that Shigeeda’s CPU 701 having CPU core 702,
`DRAM memory controller 718, and bus bridge 716 disclose, respectively,
`the claimed “at least one processor,” “memory controller,” and “bridge
`circuit.” Id. at 18–19, 23–26. Petitioner contends instruction and data
`cache 704 discloses a “cache memory.” Id. at 19–21. Petitioner also
`contends data circuit 720 of Shigeeda discloses a “cache memory,” citing
`Shigeeda’s disclosure that block 720 is implemented as write-back cache.
`Id. at 22–23 (citing Ex. 1005, 31:65–32:20, 41:34–40, 43:31–32, 47:37–43,
`50:35–53, Figs. 9 and 17). For example, Shigeeda discloses that “data
`router/buffer 720 . . . includes a Read/Write buffer implemented as a
`writeback cache in addition to and distinct from the cache in CPU 701.”
`
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`Ex. 1005, 41:38–40; see also id. at 42:38–40 (“[R]ead/write block 720 is
`implemented as a small write-back cache having 16 or 32 bytes, among
`other exemplary sizes, instead of a prefetch buffer.”).
`Claim 1 recites that each of the “at least one processor,” “a cache
`memory,” “a memory controller,” and “a bridge circuit” is “coupled to” the
`recited “bus.” Petitioner contends Shigeeda discloses that each of CPU 701
`(include CPU core 702 and cache 704), memory controller 718, bus bridge
`716, and block 720 is coupled to bus 714, as depicted in Figure 9. Pet. 18–
`26; see also Ex. 1005, 12:62–64 (“Bus 714 is connected to CPU 701, to a
`bus bridge circuit 716, and to a DRAM memory controller (MCU) 718”).
`Claim 1 further recites “at least one interface circuit to couple to a
`network external to the integrated circuit, the at least one interface circuit
`also coupled to the bridge circuit to allow the bridge circuit to initiate
`transactions onto the bus for data transfer between the bus and the at least
`one interface circuit.” Petitioner contends Shigeeda discloses that its
`peripheral processing unit (PPU) includes interface circuits, and the Petition
`includes the following annotated version of Figure 11, which is a block
`diagram of PPU 110 (Ex. 1005, 3:39–41). Pet. 30–32.
`
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`Pet. 33. According to Petitioner, the figure reproduced above is an
`annotated version of Figure 11 of Shigeeda. Id. at 32–33.
`Petitioner argues that XD/IDE interface 934 and infrared (IR) serial
`port 935 in Shigeeda’s PPU disclose two “interface circuit[s] to couple to a
`network external to the integrated circuit,” as recited in claim 1. Id. at 30–
`35. As to interface 934, Petitioner cites Shigeeda’s disclosure that “included
`in interface 934 is a bus interface for XD bus 116 of FIG. 6.” Ex. 1005,
`16:26–28 (cited at Pet. 31 n.63). Petitioner further presents the following
`annotated version of Figure 6 from Shigeeda.
`
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`Pet. 31. According to Petitioner, the figure reproduced above is an
`annotated version of Figure 6 of Shigeeda. Id. at 31. Petitioner contends
`“XD bus 116—which interfaces with XD/IDE interface 934—leads from
`PPU 110 to a modem, which connects to telephone lines using an RJ11
`jack.” Id. at 31. Petitioner asserts a person of ordinary skill in the art
`“would have understood that [a] modem is a device a computer uses to
`communicate with an external network over telephone lines or other cables.”
`Id. at 31 (citing Ex. 1003 ¶ 76). Petitioner contends, therefore, that XD/IDE
`interface 934 in peripheral processing unit (PPU) 110 “enables Shigeeda’s
`electronic system to communicate with an external network, and is thus an
`interface circuit to couple to an external network.” Id. at 31–32.
`As to IR serial port 935, Petitioner cites Shigeeda’s disclosure that an
`infrared assembly on a notebook computer “provides two-way
`communication with a corresponding infrared emitter/detector assembly on
`the back of” another notebook computer. Ex. 1005, 5:53–6:6 (cited at
`
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`Pet. 33 n.68). Petitioner contends that “Shigeeda’s two-way communication
`between IR emitter/detectors is wireless network communication that is
`external to the integrated circuit” and, therefore, that IR serial port 935
`discloses an “interface circuit to couple to a network external to the
`integrated circuit.” Pet. 34–35 (citing Ex. 1003 ¶¶ 79–81).
`Petitioner also contends that each of XD/IDE interface 934 and
`infrared (IR) serial port 935 is “coupled to the bridge circuit,” as recited in
`claim 1. Pet. 35–36. To illustrate this coupling, Petitioner presents the
`following annotated figures from Shigeeda.
`
`Id. at 36. According to Petitioner, the figures reproduced above are
`annotated versions of Figures 9 and 11 of Shigeeda illustrating an alleged
`coupling between bus bridge 716 (the alleged “bridge circuit”) and each of
`XD/IDE interface 934 and infrared (IR) serial port 935. Id. at 36. Petitioner
`asserts:
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`[B]us bridge 716 connects via line 738 to bus 104. Bus 104 in
`turn leads to the external-bus-to-internal-bus interface 902 in
`PPU 110. In PPU 110, interface 902 connects to both XD/IDE
`interface 934 and IR serial port 935 through internal bus 904. As
`such, bus bridge 716 couples to both XD/IDE interface 934 and
`IR serial port 935.
`Id. at 35–36 (citing Ex. 1005, Figs. 9, 11; Ex. 1003 ¶¶ 85–97).
`Claim 1 further recites “to allow the bridge circuit to initiate
`transactions onto the bus for data transfer between the bus and the at least
`one interface circuit.” Petitioner contends Shigeeda discloses that XD/IDE
`interface 934 and infrared (IR) serial port 935 are coupled to bus bridge 716
`to allow the bus bridge to initiate transactions onto bus 714 for data transfer
`between bus 714 and XD/IDE interface 934 or IR serial port 935. Id. at 36–
`41. In support of its contention, Petitioner cites, among other things, the
`following disclosure of Shigeeda:
`The bus bridge 716 acts as an integrated interface which is
`made compliant with whatever suitable specification is desired
`of bus 104. Bus bridge 716 advantageously acts, for example, as
`a bus master when there is a MPU 102 initiated transfer between
`the CPU and bus 104, and as a target for transfers initiated from
`bus 104.
`Ex. 1005, 13:38–43 (quoted at Pet. 37). Shigeeda further discloses that bus
`bridge 716 may be “[a]n on-chip PCI interface 716 (bus bridge) . . .
`compliant with the PCI 2.0 specification.” Ex. 1005, 24:20–21 (quoted at
`Pet. 38). Shigeeda discloses:
`In FIG. 9 the PCI bus bridge 716 provides the interface
`between the rest of MPU 102 and the PCI bus 104. The
`integrated 486 core processor 701 and memory controller 718,
`720 subsystems are connected to the PCI bus 104 through the
`PCI bridge 716. The PCI bridge 716 maps the address space of
`local bus 714, of the integrated 486 core processor 701, into the
`address space of the PCI bus 104; and provides the mechanism
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`that allows the 486 core processor to access PCI configuration
`space. The PCI bridge 716 provides a low-latency path through
`which the 486 core processor directly accesses other PCI bus
`agents mapped anywhere
`in memory and I/O spaces.
`Additionally, the PCI bridge 716 provides a high-bandwidth path
`that allows PCI bus masters outside MPU 102 direct access to
`main memory. MPU 102 is capable of behaving as a bus master
`(initiator) or PCI Slave (target) running at 0 MHz up to 25 or 33
`MHz and much higher frequencies into hundreds of MegaHertz
`according to the concepts disclosed herein.
`Ex. 1005, 24:59–25:9 (cited at Pet. 40). Shigeeda further discloses that
`types of transfers or transactions include “PCI bus 104 to main memory
`access” and “host to peripheral component access.” Id. at 25–14–16.
`Petitioner contends that these passages from Shigeeda disclose that
`“bus bridge 716 initiates transactions onto bus 714 for data transfer between
`bus 714 and peripheral components connected to the integrated circuit
`through bus 104,” including interface circuits XD/IDE interface 934 and IR
`serial port 935. Pet. 41; see Ex. 1003 ¶¶ 85–97.
`
`b. Patent Owner’s Arguments
`Patent Owner argues Petitioner has not shown Shigeeda discloses that
`the bridge circuit “initiate[s] transactions onto the bus for data transfer
`between the bus and the at least one interface circuit.” Prelim. Resp. 7–12.
`Patent Owner argues that “there is no reason to conclude that transactions
`from either ‘interface circuit’ to which Petitioners point (IR Serial Port 935
`or XD/IDE interface 934) would necessarily be transfers initiated by bus
`bridge 716 onto bus 714.” Id. at 8. According to Patent Owner, “[a] person
`having ordinary skill in the art would understand that data can be transferred
`between an I/O device and memory under control of either the CPU (known
`as programmed I/O (PIO)) or a DMA (Direct Memory Access) controller.”
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`Id. at 9 (citing Ex. 2001). Patent Owner further argues that “[a] person
`having ordinary skill in the art also would understand that the embodiments
`disclosed by Shigeeda could conceivably employ either PIO or DMA to
`control data transfers between an I/O device and memory.” Id. at 10. Patent
`Owner then explains how an input/output operation under PIO control
`allegedly would operate in Shigeeda. Id. at 10–11 (citing Ex. 1003, 24:20–
`24, 24:58–25:3, 41:53–54, 43:27–29, Fig. 17). Patent Owner argues that a
`person of ordinary skill in the art “would know that PIO could be used for
`I/O transfers, especially for slower, serial I/O devices such as a telephone
`modem or IR transceiver” and that “Shigeeda therefore suggests that the I/O
`transfers from these interfaces are not ones that would involve or require that
`bus bridge 716 ‘initiate[s] transactions onto the bus for data transfer between
`the bus and’ XD/IDE 934 or IR Serial Port 935.” Id. at 11–12.
`Although Patent Owner posits that programmed I/O (PIO) could be
`used for certain transactions in Shigeeda, such as those involving a modem
`or an IR transceiver, Patent Owner has not directed us to, nor do we find,
`disclosure in Shigeeda that PIO is used for such transactions. Furthermore,
`the pertinent language of claim 1 recites “to allow the bridge circuit to
`initiate transactions onto the bus for data transfer between the bus and the at
`least one interface circuit.” Even if a transaction under PIO control is
`“initiated by the CPU 701,” this does not mean that the bus bridge may not
`initiate a transaction onto the bus as part of the transaction initiated by the
`CPU. For example, one passage of Shigeeda cited by Patent Owner states:
`“The PCI interface 716 acts as a bus master when there is a CPU initiated
`transfer between the CPU and the high speed PCI bus 104 and as a target for
`PCI initiated transfers.” Ex. 1003, 24:21–24 (emphasis added) (cited at
`
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`Prelim. Resp. 10). Referring to this passage of Shigeeda, Petitioner argues:
`“In this context, Shigeeda again teaches that a ‘bus master’ (such as bus
`bridge 716) acts an ‘initiator’ of ‘transfers’ (i.e., transactions).” Pet. 38.
`Petitioner’s characterization of a “master” as an “initiator” appears
`consistent with Shigeeda. For example, in describing PCI control signals,
`Shigeeda discloses that “FRAME is asserted by the initiator (master).”
`Ex. 1003, 25:24 (cited at Pet. 38 n.80). Shigeeda, therefore, appears to
`equate the terms “master” and “initiator.” As such, on the current record, we
`are persuaded by Petitioner’s contention that a “bus master” in Shigeeda,
`such as bus bridge 716, is a component that is an “initiator” with respect to
`the bus, i.e., initiates transactions onto the bus. See Pet. 40.
`On the current record, we also are persuaded by Petitioner’s
`contention that “bus bridge 716 initiates transactions onto bus 714 for data
`transfer between bus 714 and peripheral components connected to the
`integrated circuit through bus 104,” such as components connected through
`XD/IDE interface 934 and IR serial port 935. See Pet. 41. As noted above,
`Shigeeda discloses that “[b]us bridge 716 advantageously acts, for example,
`as a bus master when there is a MPU 102 initiated transfer between the CPU
`and bus 104, and as a target for transfers initiated from bus 104.” Ex. 1005,
`13:40–43 (quoted at Pet. 37). As Petitioner explains, XD/IDE interface 934
`and IR serial port 935 are coupled to bus bridge 716 through bus 104. See
`Pet. 35–36, 41. Furthermore, as explained above, Shigeeda discloses that
`types of transfers or transactions include “PCI bus 104 to main memory
`access” and “host to peripheral component access.” Ex. 1005, 25:14–16.
`Thus, on the current record, we are persuaded that Shigeeda discloses “at
`least one interface circuit to couple to a network external to the integrated
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`circuit, the at least one interface circuit also coupled to the bridge circuit to
`allow the bridge circuit to initiate transactions onto the bus for data transfer
`between the bus and the at least one interface circuit,” as recited in
`independent claim 1.
`
`c. Threshold Determination as to Independent Claim 1
`On this record, Petitioner has demonstrated a reasonable likelihood of
`prevailing on its assertion that independent claim 1 is unpatentable under 35
`U.S.C. § 102(b) as anticipated by Shigeeda.
`
`2. Independent Claim 7
`Petitioner also contends Shigeeda anticipated independent claim 7.
`Pet. 50–52. Independent claim 7 is directed to, “[i]n a network device, an
`integrated circuit containing a system thereon,” and it recites limitations
`substantially similar to those of claim 1 except that claim 7 recites “a
`plurality of interface circuits to couple to different networks to allow the
`network device to operate in more than one type of network.” For its
`contentions with respect to claim 7, Petitioner refers us to its contentions as
`to claim 1 for substantially similar limitations. See Pet. 50–52. As to the
`“plurality of interface circuits” recited in claim 7, Petitioner refers to its
`discussion of “at least one interface circuit” in claim 1, as well as its
`discussion of “multiple interface circuits” in dependent claim 5. See Pet. 51.
`As discussed above in the section addressing claim 1, Petitioner contends
`XD/IDE interface 934 and infrared (IR) serial port 935 in Shigeeda’s PPU
`disclose two such interface circuits that couple to different networks.
`Pet. 30–35; see also id. at 48–49 (discussing multiple interface circuits in the
`context of dependent claim 5).
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`IPR2017-00814
`Patent 6,766,389 B2
`
`
`Patent Owner argues claim 7 is not unpatentable as anticipated for the
`same reasons it presents with respect to claim 1, which we address above.
`Prelim. Resp. 12–14. On this record, we are persuaded that Petitioner’s
`analysis is sufficient for institution. Therefore, we determine Petitioner has
`established a reasonable likelihood it would prevail in showing that
`independent claim 7 is unpatentable under 35 U.S.C. § 102(b) as anticipated
`by Shigeeda.3
`
`3. Dependent Claims 2–5, 9, and 13
`Petitioner also contends Shigeeda anticipated dependent claims 2–5,
`9, and 13. Pet. 42–50, 52–53. Each challenged claim is discussed in turn
`below.
`
`a. Dependent Claims 2 and 3
`Dependent claim 2 recites: “The integrated circuit as recited in
`claim 1 wherein the memory controller to control transfer of data between
`the bus and an external memory when the external memory is coupled to the
`integrated circuit, in order to store data received from the at least one
`interface circuit.” Petitioner contends “Shigeeda discloses that memory
`controller 718 controls transfer of data between bus 714 and DRAM 106
`when DRAM 106 is coupled to Shigeeda’s integrated circuit, in order to
`store data received from XD/IDE interface 934 or IR serial port 935.”
`Pet. 42; see also Pet. 42–44 (further explaining contention). On this record,
`
`
`3 We make this determination based on the information presented in
`Petitioner’s anticipation challenge to claim 7 notwithstanding Petitioner’s
`potentially inconsistent statement with respect to another unpatentability
`challenge that “Shigeeda does not expressly state that such an integrated
`circuit may have multiple interface circuits to couple to separate networks.”
`See Pet. 53.
`
`
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`IPR2017-00814
`Patent 6,766,389 B2
`
`we are persuaded that Petitioner’s analysis is sufficient for institution as to
`claim 2.
`Dependent claim 3 recites: “The integrated circuit as recited in
`claim 2 wherein the cache memory is a Level 2 cache.” Petitioner contends
`“Shigeeda teaches that cache memory may be a ‘second level cache,’ i.e., ‘a
`Level 2 cache.’” Pet. 45 (citing Ex. 1003, Abstract, claims 10–14). Patent
`Owner argues that Petitioner’s proposed interpretation of “Level 2 cache” is
`incorrect and, therefore, that Petitioner’s challenge to claim 3 should be
`rejected. Prelim. Resp. 16–26. On the current record, we are persuaded
`Shigeeda discloses “Level 2 cache.” For example, Shigeeda discloses:
`An electronic system, such as a computer system, having
`a first level write through cache and a smaller second-level write-
`back cache, is disclosed. The disclosed computer system
`includes a single integrated circuit microprocessor unit that
`includes a microprocessor core, a memory controller circuit, and
`first and second level caches.
`Ex. 1005, Abstract (emphases added). Thus, Shigeeda expressly discloses
`“second level,” i.e., “Level 2,” cache. Shigeeda’s terminology appears
`consistent with Patent Owner’s characterization of how caches in a system
`are labeled. See Prelim. Resp. 18 (citing Ex. 1009, 4–5 (describing “first-
`level or primary cache” and “secondary or second level cache”)).
`On this record, we are persuaded that Petitioner’s analysis is sufficient
`for institution as to claim 3.
`
`b. Dependent Claims 4, 5, 9, and 13
`Dependent claim 4 recites: “The integrated circuit as recited in
`claim 2 wherein the bridge circuit to operate to maintain cache coherency for
`the integrated circuit.” The Petition’s entire contention with respect to
`claim 4 is as follows:
`
`
`
`19
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`IPR2017-00814
`Patent 6,766,389 B2
`
`
`Shigeeda discloses all elements of claim 2 as described above.
`Shigeeda further discloses “the bridge circuit to operate to
`maintain cache coherency for the integrated circuit,” as recited
`in claim 4. Shigeeda uses an “automatic write,” or a “cache
`flush,” of the write-back cache block to “reestablish coherency”
`in its system. Bus bridge 716 maintains cache coherency by
`participating in the cache flush process. Because it is involved
`in the cache flush process, bus bridge 716 thus operates to
`maintain cache coherency for the integrated circuit.
`Shigeeda thus discloses all elements of, and anticipates,
`claim 4.
`Pet. 48 (citing Ex. 1003 ¶¶ 112–129; Ex. 1005, Abstract, 42:38–47:43,
`Figs. 9 and 17). For the reasons that follow, we deny institution as to claims
`4, 5, 9, and 13.
`First, Petitioner has not explained sufficiently how Shigeeda discloses
`operation “to maintain cache coherency,” as recited in claim 4. In support of
`its assertion that “Shigeeda uses an ‘automatic write,’ or a ‘cache flush,’ of
`the write-back cache block to ‘reestablish coherency’ in its system” (Pet. 48
`n.105), Petitioner cites the following passage from Shigeeda:
`Remarkably, the read/write block 720 is implemented as a
`small write-back cache having 16 or 32 bytes, among other
`exemplary sizes, instead of a prefetch buffer. The write-back
`cache 720 has Least Recently Used (LRU) type operation in one
`embodiment. Write-back cache 720 provides data back to CPU
`without a DRAM 106 access, and maintains dirty data until it is
`full of dirty data (data not necessarily the same as DRAM 106
`contents at the memory address written), whereupon an
`automatic write (cache flush) occurs to reestablish coherency.
`Ex. 1005, 42:38–47 (emphases added). Petitioner provides no further
`explanation of this citation—specifically why a cache flush that occurs only
`upon the write-back cache’s becoming full of dirty data to “reestablish
`coherency” discloses “maintain[ing] cache coherency.” Petitioner also cites
`
`
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`20
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`IPR2017-00814
`Patent 6,766,389 B2
`
`Shigeeda’s Abstract (Pet. 48 n.105) but provides no further explanation of its
`relevance. Although Shigeeda’s Abstract mentions a cache flush operation,
`it does not explain how a cache flush discloses an operation “to maintain
`cache coherency,” as recited in claim 4.
`Second, Petitioner does not explain sufficiently how bus bridge 716
`“operate[s] to maintain cache coherency for the integrated circuit,” as recited
`in claim 4. Petitioner states: “Bus bridge 716 maintains cache coherency by
`participating in the cache flush process. Because it is involved in the cache
`flush process, bus bridge 716 thus operates to maintain cache coherency for
`the integrated circuit.” Pet. 48 (citing Ex. 1005, 42:38–47:43, Figs. 9 and
`17). In support of this assertion, Petitioner cites five columns and two
`figures from Shigeeda without any further explanation in the Petition
`specifying the relevance or significance of this cited evidence. Our Rules
`provide that a petition for inter partes review must “[p]rovide a statement of
`the precise relief requested for each claim challenged” and that “[t]he
`statement must identify . . . the relevance of the evidence to the challenge
`raised, including identifying specific portions of the evidence that support
`the challenge.” 37 C.F.R. § 42.104(b)(5). Petitioner’s citation to five
`columns of Shigeeda (Ex. 1005, 42:38–47:43) is not an adequate
`identification of a “specific portion[] of the evidence,” and, further, the
`Petition lacks sufficient explanation of these cited columns. See 37 C.F.R.
`§ 42.104(b)(5) (“The Board may exclude or give no weight to the evidence
`where a party has failed to state its relevance or to identify specific portions
`of the evidence that support the challenge.”).
`Petitioner’s more focused citation of Shigeeda (Ex. 1005, 42:38–47)
`does not mention bus bridge 716, much less explain how it “operate[s] to
`
`
`
`21
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`
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