Trials@uspto.gov
`571-272-7822
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` Paper No. 8
` August 24, 2017
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`XILINX, INC.,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`IPR2017-00844
`Patent 6,653,731 B2
`____________
`
`
`Before MICHAEL J. FITZPATRICK, JENNIFER MEYER CHAGNON,
`and SHEILA F. McSHANE, Administrative Patent Judges.
`
`McSHANE, Administrative Patent Judge.
`
`
`
`DECISION
`Instituting Inter Partes Review
`35 U.S.C. § 314(a) and 37 C.F.R. § 42.108
`
`
`
`
`
`
`
`571-272-7822
`
`
` Paper No. 8
` August 24, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`XILINX, INC.,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`IPR2017-00844
`Patent 6,653,731 B2
`____________
`
`
`Before MICHAEL J. FITZPATRICK, JENNIFER MEYER CHAGNON,
`and SHEILA F. McSHANE, Administrative Patent Judges.
`
`McSHANE, Administrative Patent Judge.
`
`
`
`DECISION
`Instituting Inter Partes Review
`35 U.S.C. § 314(a) and 37 C.F.R. § 42.108
`
`
`
`
`
`
`
`
`IPR2017-00844
`Patent 6,653,731 B2
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`I. INTRODUCTION
`A. Background
`Xilinx, Inc. (“Petitioner”) filed a Petition requesting inter partes
`review of claim 5 (“the challenged claim”) of U.S. Patent No. 6,653,731 B2
`(Ex. 1001, “the ’731 patent”) pursuant to 35 U.S.C. §§ 311–319. Paper 1
`(“Pet.”). Godo Kaisha IP Bridge 1 (“Patent Owner”) filed a Preliminary
`Response to the Petition. Paper 7 (“Prelim. Resp.”).
`We have authority under 35 U.S.C. § 314(a), which provides that an
`inter partes review may not be instituted “unless . . . the information
`presented in the petition . . . shows that there is a reasonable likelihood that
`the Petitioner would prevail with respect to at least 1 of the claims
`challenged in the petition.” See 37 C.F.R. § 42.4(a) (“The Board institutes
`the trial on behalf of the Director.”).
`We determine that Petitioner has demonstrated that there is a
`reasonable likelihood that it would prevail with respect to the one challenged
`claim. For the reasons described below, we institute an inter partes review
`of claim 5 of the ’731 patent.
`B. Related Proceedings
`The parties indicate that a related matter is: Xilinx, Inc. v. Godo
`Kaisha IP Bridge 1, Civ. No. 5:17-cv-00509 (N.D. Cal.). Pet. 1, Paper 4, 1.
`Patent Owner also indicates that three petitions for inter partes review have
`been filed for related patents: Cases IPR2017-00841, IPR2017-00842, and
`IPR2017-00843. Paper 4, 1.
`C. The ’731 Patent
`The ’731 patent is entitled “Semiconductor Device And Method For
`
`Fabricating Same,” and issued on November 25, 2003, from an application
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`filed on February 15, 2001. Ex. 1001, [22], [45], [54]. The ’731 patent
`claims foreign priority to application JP 2000-051873, dated February 28,
`2000. Id. at [30].
`
`The ’731 patent is directed to a semiconductor device in which a chip
`with bumps, and having a protective resin, is provided. Ex. 1001, Abstract.
`The bare chip is coated with protective resin in order to prevent it from
`being cracked. Id. at 1:7–11. A semiconductor device, such as a large-scale
`integration (LSI) chip 101, is reproduced in Figure 1 below.
`
`Figure 1, above, show a conventional bare chip. Ex. 1001, 1:20–21.
`Insulating layer 102 is provided on the surface of LSI chip 101, with wiring
`layer 104 with LSI electrodes 103. Id. at 1:22–24. Plural bumps 105 are
`mounted on the leading ends of LSI electrodes 103, and serve as external
`electrodes. Id. at 1:24–27. Figure 4A, reproduced below, shows a cross-
`sectional view of a chip with resin.
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`Figure 4A, above, depicts protective resin 4 coating the sides of LSI chip 1.
`Ex. 1001, 4:48–51. Testing of chip reliability of a chip such as that shown
`in Figure 4A was performed “supposing a condition that the semiconductor
`devices are packed up and transported,” where “[t]he permissible width of
`the semiconductor device shown in FIG. 4A is defined as the sum of 25 µm
`and the thickness of protective resin 4.” Id. at 10:29–40. Figure 12,
`reproduced below, shows the relationship “between the permissible widths
`of the semiconductor devices and percent de[f]ectives of the semiconductor
`devices” (id. at 10:49–51):
`
`
`Figure 12, above, depicts, in black circles, data of semiconductor devices
`such as that shown in Figure 4A, and the white circles show test data of the
`conventional semiconductor device such as that shown in Figure 1.
`Ex. 1001, 10:51–55. The data indicates that the defective percentages of the
`semiconductor device shown in Figure 4A decreases as the permissible
`width increases, and when the permissible width is more than 100 µm, the
`effect is a noticeable improvement in mechanical reliability as compared to a
`conventional semiconductor device with the same dimensions. Id. at 10:55–
`65.
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`Claim 5, reproduced below, is the only challenged claim of the ’731
`patent.
`
`5. A semiconductor device, comprising:
`a bare chip;
`plural bumps provided on an active surface of said bare chip;
`
`and
`
`protective members formed on side surfaces of said bare chip to
`surround a periphery of said bare chip,
`wherein a sum of a thickness of each of said protective
`members and a width of said bare chip is more than 100 µm.
`Ex. 1001, 12:55–64.
`
`D. Asserted Grounds of Unpatentability
`Petitioner asserts the following grounds of unpatentability against
`
`claim 5 of the ’731 patent:
`Ground
`§ 102
`§ 103
`§ 102
`§ 102
`
`Prior Art
`Yoshikazu1
`Yoshikazu and Ohta2
`Ohta
`Lau3
`
`Pet. 29–30.
`
`
`1 U.S. Patent No. 5,989,982 (issued November 23, 1999) (Ex. 1005).
`Petitioner asserts that Yoshikazu is prior art to the ’731 patent under
`35 U.S.C. § 102(e). Pet. 29.
`2 U.S. Patent No. 6,228,688 B1 (issued May 8, 2001) (Ex. 1006). Petitioner
`asserts that Ohta is prior art to the ’731 patent under 35 U.S.C. § 102(e).
`Pet. 29.
`3 FLIP CHIP TECHNOLOGIES (John H. Lau ed., McGraw-Hill 1996) (Ex.
`1007). Petitioner asserts that Lau is prior art to the ’731 patent under
`35 U.S.C. §§ 102(a) and 102(b). Pet. 30.
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`II. ANALYSIS
`A. Claim Construction
`In an inter partes review, the Board interprets claim terms in an
`unexpired patent according to the broadest reasonable construction in light
`of the specification of the patent in which they appear. 37 C.F.R.
`§ 42.100(b); Cuozzo Speed Techs., LLC v. Lee, 136 S. Ct. 2131, 2144–46
`(2016) (upholding the use of the broadest reasonable interpretation
`approach). Under that standard, and absent any special definitions, we give
`claim terms their ordinary and customary meaning, as they would be
`understood by one of ordinary skill in the art at the time of the invention.
`In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).
`“a sum of a thickness of each of said protective members and a
`width of said bare chip is more than 100 μm”
`Hereinafter, we will refer to the claim 5 term “wherein a sum of a
`
`thickness of each of said protective members and a width of said bare chip is
`more than 100 μm” as the “Sum Limitation.” Petitioner proposes that the
`plain and ordinary meaning of the term is a “sum of a width of the bare chip
`(along a plane parallel to an active surface of the bare chip) and a thickness
`of the protective member on each side of the bare chip (along a plane
`parallel to an active surface of the bare chip) is greater than 100 μm” under
`the broadest reasonable interpretation of the term. Pet. 25. In support,
`Petitioner alleges that a person of ordinary skill in the art would understand
`that the width of a chip is measured in a direction parallel to the active
`surface of the chip, and the thickness of the member along the side of the
`chip would be measured in the same direction. Id. at 25–26 (citing Ex. 1003
`¶ 65).
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`In the alternative, Petitioner proposes an allegedly narrower
`
`construction of the Sum Limitation. Pet. 26–28 (citing Ex. 1003 ¶¶ 66, 68,
`69). Petitioner explains that Figure 12 is described as the “the percent
`defective of the semiconductor device according to the invention shown in
`FIG. 4A,” and this chart shows that “[w]hen the permissible width is more
`than 100 μm, the effect of the invention becomes further noticeable.” Id. at
`26–27 (citing Ex. 1001, 10:56–57, 10:59–61). Petitioner asserts that
`the ’731 patent describes that the crack permissive area is as “a frame-
`shaped region ranging from edges of the LSI chip 101 to exterior electrodes
`on the same, and a width thereof is about 50 µm” Id. at 27 (citing Ex. 1001,
`1:46–48). Petitioner argues that, referring to annotated Figure 4A,
`reproduced below, that a person of ordinary skill “might interpret the ‘width
`of said bare chip’ as referring to the permissible width” as shown in the
`annotated figure. Id. at 28 (citing Ex. 1003 ¶ 69).
`
`As such, Petitioner asserts that, in the alternative, and as depicted in
`annotated Figure 4A above, the Sum Limitation should be interpreted to
`mean “that a sum of a crack permissible area within the bare chip (area
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`between the edges of the chip to exterior electrodes) and a thickness of the
`protective member adjacent the die is greater than 100 μm.” Id. at 28 (citing
`Ex. 1003 ¶ 69).
`Patent Owner disputes Petitioner’s first proposed claim construction,
`contending that it reads out the claim limitation of “each of said protective
`members.” Prelim. Resp. 33. Patent Owner argues that the “‘each’
`limitation requires that the claimed sum of more than 100 μm apply to each
`of the protective members surrounding the bare chip.” Id. Patent Owner
`also alleges that a person of ordinary skill in the art would understand the
`broadest reasonable interpretation of the Sum Limitation as requiring the
`following:
`the sum of the thickness of each protective member (i.e., the
`protective member on each side of the chip) and a width of the
`bare chip adjacent the side surface on which that protective
`member is formed (i.e., the “width” of the crack permissible
`area 107 in Fig. 1) be more than 100 μm.
`Id. at 34. Patent Owner argues that this interpretation is consistent with the
`Specification and its disclosures relating to the protective boundary
`surrounding the electronics in the circuit area. Id. at 36–39. Patent Owner
`asserts that Petitioner’s first alternative interpretation, therefore, is
`unreasonably broad in light of the Specification and also impermissibly
`reads out limitations from the claim. Id. at 42–43.
`As to Petitioner’s second alternative proposed construction, Patent
`Owner alleges that Petitioner reads out the limitation of “each of said
`protective members,” as it only includes the protective member thickness for
`a single side of the chip. Prelim. Resp. 44–45.
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`At this juncture, we are persuaded by Patent Owner’s argument that
`Petitioner’s first proposed construction of the Sum Limitation does not fully
`consider the claim language itself in light of the disclosures of the
`Specification. See Prelim. Resp. 39–43. The Specification refers to “a
`frame-shaped region ranging from edges of the LSI chip 101 to exterior
`electrodes on the same, and a width thereof is about 50 µm.” Ex. 1001,
`1:46–49 (emphasis added). Also, as discussed above in the description of
`the ’731 patent, the Specification discusses testing that was done on bare
`chips, and those with protective resin applied, as follows
`Finally, reliability of the semiconductor device according to the
`invention shown in FIG. 4A is compared with that of the
`conventional semiconductor device (the bare chip) shown in
`FIG. 1, supposing a condition that the semiconductor devices
`are packed up and transported. In case that protective resin 4 is
`removed from the semiconductor device shown in FIG. 4A, a
`permissible width (corresponding to a permissible area 107
`shown in FIG. 1) of the LSI chip is 25 µm. The permissible
`width of the semiconductor device shown in FIG. 4A is defined
`as the sum of 25 µm and the thickness of protective resin 4.
`Ex. 1001, 10:30–40 (emphasis added).
`
`Here, the term “a width” of a bare chip is disclosed to be that
`between the edges of the chip to the exterior electrodes, and then the
`“permissive width” is defined as that width and the thickness of
`protective resin. However, at this juncture, it is unclear as to whether
`Patent Owner is proposing that the widths of “each protective
`member” to be summed are those of the protective members on two
`sides of the cross-section of the chip or include the sum of protective
`members on all four sides of the chip. Petitioner assumes, under its
`second alternative construction of the Sum Limitation, that the
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`protective member width be considered for “the protective member
`the protective member adjacent the die,” which appears to include
`only the width on one side of the chip—and Petitioner appears to use
`the width of the protective member only on one side of the chip in its
`mapping of prior art to the Sum Limitation. We would further
`consider any additional clarifications of positions and rationale
`regarding the respective claim constructions from the parties in future
`filings. However, as discussed further below, because Petitioner’s
`challenges appear to consider the protective member width on one
`side only of the applied prior art, if the prior art meets the sum of
`“more than 100 μm” under Petitioner’s proposed construction, it
`would also meet that limitation under Patent Owner’s proposed
`construction, which appears to include and sum widths on other sides
`of the chip as well. Therefore, for the purposes of this Decision, we
`determine that the Sum Limitation requires that the sum of the
`thickness of at least one protective member and a width of the bare
`chip adjacent the side surface on which that protective member is
`formed (i.e., the “width” of the crack permissible area 107 in Fig. 1)
`be more than 100 μm.
`“to surround a periphery”
`Patent Owner argues that a person of ordinary skill in the art would
`understand that the broadest reasonable interpretation of the term “to
`surround a periphery” to mean that “protective members are formed on all
`the side surfaces of the chip and fully cover each of those side surfaces.”
`Prelim. Resp. 27. Patent Owner refers to dictionary definitions for the terms
`of “surround” and “periphery” in support. Id. at 28. Patent Owner also cites
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`to the Specification, where it discloses that the side surfaces are “coated
`with” and “protect[ed]” by the resin. Id. at 28–29 (citing Ex. 1001, 1:6–10,
`4:33–35, 4:48–51, 5:2–4, 5:33–38, 5:55–63). Patent Owner further asserts
`that an objective of the invention is to prevent the chip from being chipped
`or cracked and the protective members cannot provide that protection
`“unless they fully cover those side surfaces.” Id. at 29. It is also contended
`that in all of the embodiments provided in the ’731 patent, the resin fully
`coats the side surfaces. Id. at 29–32. Petitioner did not provide a proposed
`construction for the claim term.
`At this juncture, we do not find persuasive Patent Owner’s arguments
`that the claim requires “full coverage,” because this impermissibly adds a
`claim limitation not recited in the claim. We agree that “to surround” means
`to be on all sides of an object, but to require also that it fully cover the sides
`is an additional requirement. For the purposes of this Decision, we adopt the
`plain and ordinary meaning of the claim term of “to surround a periphery” to
`be “on all sides of the periphery.”
`Other Terms
`The proposed claim constructions provided for other terms are
`undisputed. See Pet. 23–25; Prelim. Resp. 26–27. At this juncture of the
`proceeding, we determine that it is not necessary to provide an express
`interpretation of any other term of the claims. Cf. Vivid Techs., Inc. v. Am.
`Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999) (“[O]nly those terms
`need be construed that are in controversy, and only to the extent necessary to
`resolve the controversy.”) (emphasis added).
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`B. Alleged Anticipation of Claim 5 by Yoshikazu
` Petitioner contends that claim 5 is anticipated by Yoshikazu. Pet. 34–
`43. To support its contentions, Petitioner provides explanations as to how
`Yoshikazu discloses each claim limitation. Id. Petitioner also relies upon
`the Declaration of Peter Elenius (“Elenius Declaration” (Ex. 1003)) to
`support its positions.
` We are not persuaded by Petitioner’s explanations and evidence in
`support of this anticipation ground against claim 5. We begin our discussion
`with a brief summary of Yoshikazu, and then address the evidence, analysis,
`and arguments presented.
`1. Yoshikazu (Ex. 1005)
`Yoshikazu is directed to a method of manufacture of a semiconductor
`device, where a wafer is divided into smaller fractions. Ex. 1005, Abstract.
`A chip size package can be manufactured with the chip sides sealed in resin.
`Id. Figure 1 of Yoshikazu, reproduced below, is a cross-section of a chip.
`
`
`Figure 1, above, depicts LSI chip 1, with bump electrodes 2, epoxy resin 3,
`and solder balls 4. Ex. 1005, 2:23–36. Epoxy resin may be used for
`protection of the surface of the chip, and may cover the surface and sides of
`it. Id. at 2:28–32. Solder balls 4 are used for providing electrical
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`connections to an external substrate, are shaped in the form of a sphere, and
`may have a diameter range from about 300 to 500 µm. Id. at 2:33–36.
`2. Analysis
`A claim is unpatentable under 35 U.S.C. § 102 if a prior art reference
`discloses each and every element of the claimed invention, either explicitly
`or inherently. Glaxo Inc. v. Novopharm Ltd., 52 F.3d 1043, 1047 (Fed. Cir.
`1995); see MEHL/Biophile Int’l Corp. v. Milgraum, 192 F.3d 1362, 1365
`(Fed. Cir. 1999) (“To anticipate a claim, a prior art reference must disclose
`every limitation of the claimed invention . . .;” any limitation not explicitly
`taught must be inherently taught and would be so understood by a person
`experienced in the field.); In re Baxter Travenol Labs., 952 F.2d 388, 390
`(Fed. Cir. 1991) (The dispositive question is “whether one skilled in the art
`would reasonably understand or infer” that a reference discloses all of the
`elements of the claimed invention.).
` Petitioner asserts that Yoshikazu discloses a bare chip having a width
`greater than 100 μm, and that the disclosure of “[t]his dimension, standing
`alone, is sufficient to meet [the Sum Limitation] element.” Pet. 41.
`Petitioner provides an annotated version of Yoshikazu’s Figure 1,
`reproduced below, in support of its contention.
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`Petitioner asserts, as per annotated Figure 1 above, that Yoshikazu discloses
`that there are at least two bumps 4 on bare chip 1, and, as such, chip 1 has a
`width of at least two of those bumps, or 600 µm. Pet. 42 (citing Ex. 1003
`¶ 88 (at pages 44–46); Ex. 1005, 2:32–36). In further support, the Elenius
`Declaration states
`It is my understanding that patent drawings are not necessarily
`drawn to scale and that in some instances relative dimensions in
`a patent drawing cannot be relied upon. In my analysis, I have
`not relied upon the size of the illustrated various structures, nor
`have I assumed the drawings are to scale. Rather, I have relied
`upon the explicit disclosure of the solder ball size and the
`explicit disclosure of multiple balls on the chip to conclude that
`Yoshikazu expressly discloses a minimum width of greater than
`100 μm.
`Ex. 1003 ¶ 88 (at pages 45–46 (claim chart, element [1.3c])).
`Patent Owner counters that Petitioner does not establish that
`Yoshikazu discloses the Sum Limitation of claim 5 because it relies on an
`erroneous and overly broad claim construction. Prelim Resp. 46–52. Patent
`Owner argues that Petitioner fails to identify the thickness of any protective
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`member or the width of area at the edge of the bare chip, and does not
`establish the claimed sum of thicknesses as required by the claim. Id. at 48.
`Patent Owner also asserts that “[a]lthough Yoshikazu discloses that the
`solder balls are spherical and can range from 300 μm to about 500 μm, the
`Petition points to no disclosure in Yoshikazu that the chip is larger than
`those solder balls in the direction perpendicular to the dimension shown in
`Fig. 1.” Id. at 51.
` Petitioner acknowledges that its anticipation challenge over
`Yoshikazu is predicated on the adoption of its first proposed construction of
`the sum limitation as the sum of the width of a bare chip and the thicknesses
`of the protective members. Pet. 30–31. Here, we do not adopt Petitioner’s
`first proposed claim construction, and Petitioner does not provide any
`rationale or evidence for anticipation under Yoshikazu under its second
`alternative construction of the Sum Limitation. Therefore, based on the
`record before us, and because we do not adopt the claim construction the
`challenge depends upon, Petitioner has not demonstrated a reasonable
`likelihood of prevailing on its assertion that claim 5 is anticipated by
`Yoshikazu.
`C. Alleged Obviousness of Claim 5 over Yoshikazu and Ohta
`Petitioner contends that claim 5 would have been obvious over
`Yoshikazu and Ohta. Pet. 44–56. To support its contentions, Petitioner
`provides explanations as to how the prior art discloses each claim limitation.
`Id. Petitioner also relies upon the Elenius Declaration to support its
`positions. Patent Owner counters that the prior art does not render claim 5
`obvious, because the prior art fails to sufficiently teach the Sum Limitation
`of claim 5. Prelim. Resp. 52–60.
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`On this record, we are persuaded by Petitioner’s explanations and
`evidence in support of the obviousness grounds asserted under Yoshikazu
`and Ohta for claim 5. We begin our discussion with a brief summary of
`Ohta, and then address the evidence, analysis, and arguments presented by
`the parties.
`
`1. Ohta (Ex. 1006)
`Ohta is directed to semiconductor devices with solder bumps.
`Ex. 1006, 5:38–41. The semiconductor devices are resin-encapsulated, to
`include application of the sealing resin to the sides and bottom of the
`semiconductor element. Id. at Abstract. Figure 3, reproduced below,
`depicts the semiconductor element.
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`
`
`Figure 3, above, is a cross-sectional view showing an example of a
`resin-encapsulated semiconductor device. Ex. 1006, 4:61–63.
`Semiconductor element 5 is mounted facedown on on double-sided wiring
`sebsrate 8 via bumps 9. Id. at 5:38–41. Semiconductor element 5 is
`encapsulated by resin layer 7. Id. at 6:43–46. Ohta depicts a series of steps,
`uilizing frame-like mold 1 and press mold 2 to encapulate semiconductor
`element 5 with sealing resin 6. Figures 2A–2D are reproduced below.
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`Figures 2A to 2D, above, are cross-sectional views showing a manufacturing
`process of a resin-encapsulated semiconductor device. Ex. 1006, 4:58–60.
`Ohta discloses “the sealing resin 6 and the semiconductor element 5 are
`completely enclosed by a region defined by the printed wiring substrate 8,
`the frame-like mold 1 and the press mold 2,” where then “the press mold 2 is
`moved downward to directly apply a pressure onto the sealing resin 6.” Id.
`at 6:10–15. Ohta further states that
`The molten resin thus pressurized by the press mold 2 is forced
`to flow through the space between four sides of the
`semiconductor element 5 and the side walls of the frame-like
`mold into the space between the semiconductor element 5 and
`the printed wiring substrate 8 until it reaches the center of the
`space.
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`Id. at 6:17–22. Using the process, “[a]s a result, a package shown in
`[Figure] 3 . . . can be obtained.” Id. at 6:43–46.
`2. Analysis
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
`differences between the claimed subject matter and the prior art are such that
`the subject matter, as a whole, would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
`subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007). The question of obviousness is resolved on the basis of underlying
`factual determinations including: (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art;
`(3) the level of ordinary skill in the art;4 and (4) objective evidence of
`nonobviousness.5 Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`We have reviewed the Petitioner’s evidence and explanations for the
`alleged teaching by Yoshikazu and Ohta of a semiconductor device,
`comprising a bare chip, plural bumps, and protective member elements of
`claim 5. Pet. 46–50. Patent Owner provide no arguments disputing the
`teaching of these elements at this stage, and we are persuaded that the
`evidence provided is sufficient.
`However, Patent Owner disputes whether the relied-upon prior art
`teaches the Sum Limitation of claim 5. See Prelim. Resp. 52–60. Petitioner
`relies on Ohta for the teaching of the Sum Limitation. Pet. 52–54.
`
`
`4 Petitioner proposes an assessment of the level of ordinary skill in the art.
`Pet. 33; see Ex. 1003 ¶ 29. Patent Owner does not propose an alternative
`assessment. For purposes of this Decision and to the extent necessary, we
`adopt Petitioner’s assessment.
`5 There is no objective indicia of nonobviousness yet in the record.
`
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`Petitioner cites to Ohta’s disclosures of a 20 mm by 20 mm chip, placed in a
`25 mm by 25 mm mold cavity to form protective members, i.e. resin layer 7.
`Id. at 52–53 (citing Ex. 1006, 33:25–26, 33:16; Ex. 1003 ¶ 91 (at pages 52–
`55 (claim chart, element [1.3c]))). The respective dimensions are shown in
`annotated Figure 2D reproduced below.
`
`
`Annotated Figure 2D, above, presents a cross-section of Ohta’s chip.
`Pet. 53.
`The Elenius Declaration provides testimony on annotated Figure 2D,
`above, as follows:
`Ohta’s Figure 2D shows that a 20 mm x 20 mm chip is placed
`in the 25 mm x 25 mm mold cavity to form Ohta’s protective
`members (resin layer 7). The gap between the inside dimension
`of the mold cavity and the size of the semiconductor element is
`5 mm total (25mm – 20 mm) or half of this, 2.5 mm, at each
`side of the semiconductor element. . . . This 2.5 mm gap is
`filled with resin layer 7 to form the protective members, which
`are hence each 2.5 mm in thickness. My understanding of
`Ohta’s teaching is not based upon an assumption that the
`drawings are to scale. Rather, my understanding is based upon
`the express disclosure of the dimensions of the semiconductor
`element and the mold cavity, as discussed above. . . . As such,
`Ohta’s protective members (resin layer 7) have a thickness of
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`2500 μm on each side of Ohta’s bare chip (semiconductor
`element 5). This is “more than 100 μm” as recited by claim 1.
`Ex. 1003 ¶ 91 (at pages 53–54 (claim chart, element [1.3c])).
`
`Petitioner asserts that Ohta teaches the Sum Limitation of claim 5
`under its second proposed claim construction. Pet. 52–54. Petitioner
`contends that one of ordinary skill in the art would have been motivated to
`modify Yoshikazu with Ohta in order “to provide a resin-encapsulated
`semiconductor device which is capable of withstanding an external shock
`and of avoiding a warpage thereof, and is excellent in reliability.” Id. at 54
`(quoting Ex. 1006, 33:48–51; also citing Ex. 1003 ¶ 91 (at pages 52–55
`(claim chart, element [1.3c]))).
`
`Patent Owner asserts that Petitioner’s assumption that Ohta’s resin is
`applied uniformly around that entire periphery of the chip is unsupported.
`Prelim. Resp. 52–53, 55–57. More specifically, Patent Owner argues that
`the Petition does not allege or establish that the chip is centered in Ohta’s
`mold. Id. at 59. Patent Owner contends that, not only does Ohta fail to
`disclose uniform application, but also that it affirmatively discloses that the
`resin can have different thicknesses on different sides. Id. at 53, 57–58.
`Patent Owner refers to Figures 6A to 6C for views of chips that are
`positioned in molds such that there would be no protective resin formed on
`one side of the chip. Id. at 58 (citing Ex. 1006, 8:21–32, Figs. 6A–6C).
`Patent Owner contends that patent drawings are not drawn to scale and
`dimensions should not be inferred from them. Id. at 59.
`
`At this juncture, the overall weight of the evidence supports the
`Petition’s arguments regarding Ohta’s disclosures. “[I]t is well established
`that patent drawings do not define the precise proportions of the elements
`and may not be relied on to show particular sizes if the specification is
`
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`completely silent on the issue” and the drawings are not drawn to scale.
`Hockerson-Halberstadt, Inc. v. Avia Group Int’l, Inc., 222 F. 3d 951, 956
`(Fed. Cir. 2000); see Nystrom v. TREX Co., Inc., 424 F.3d 1136, 1148–49
`(Fed. Cir. 2005). However, drawings are “evaluat[ed] and appl[ied] . . . on
`the basis of what they reasonably disclose and suggest to one skilled in the
`art,” (In re Aslanian, 590 F.2d 911, 914 (CCPA 1979) (quoting In re Baum,
`374 F.2d 1004, 1009 (CCPA 1967)), and drawings may teach relative
`quantitative relationships between or among the depicted elements. See
`Vas-Cath, Inc. v. Mahurkar, 935 F.2d 1555, 1566 (Fed. Cir. 1991); In re
`Mraz, 455 F.2d 1069, 1072 (CCPA 1972). Here, the dimensions of the mold
`and chip relied upon by Petitioners are provided in the Specification. See
`Pet. 52–53 (citing Ex. 1006, 33:25–26 and 33:16). Although Ohta discloses
`an embodiment with no resin on one side in Figures 6A to 6C, it also
`discloses embodiments where the resin is described as “flow[ing] into the
`space” “all at once from fours sides thereof” and “entire[] encapsulation by
`the resin layer 7 can be obtained.” See Ex. 1006, 6: 22–25, 6:43–46.
`Moreover, even if there were different thicknesses on different sides, as
`Patent Owner argues, there is nonetheless sufficient evidence that there
`would still be large enough widths of resin on some sides of the Ohta chip to
`meet the Sum Limitation (i.e., “more than 100 μm”), particularly under
`Patent Owner’s proposed construction, which includes in the sum the widths
`of more than one protective member on different sides of the chip.
`Therefore, based on the record before us, Petitioner has demonstrated
`a reasonable likelihood of prevailing on its assertion that claim 5 would have
`been obvious over Yoshikazu and Ohta.
`
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`D. Alleged Anticipation of Claim 5 by Ohta
`Petitioner contends that claim 5 is anticipated by Ohta. Pet. 56–66.
`
`Petitioner relies on the similar evidence and argument as that discussed
`above for Ohta’s disclosure of the Sum Limitation of claim 5, and provides
`additional evidence in support of the assertion that Ohta discloses the other
`elements of claim 5. Id. Patent Owner relies upon the same arguments for
`its assertions on this ground as it did for the obviousness ground above, that
`is, that Ohta does not disclose the Sum Limitation. Prelim. Resp. 61. For
`the reasons discussed supra Section II.C, we do not find Patent Owner’s
`arguments persuasive.
`
`On this record, we are persuaded that Petitioner has provided
`sufficient evidence and explanations as to how the Ohta discloses each claim
`limitation and, thus, has demonstrated a reasonable likelihood of prevailing
`on the assertion that claim 5 of the ’731 patent is anticipated by Ohta.
`E. Alleged Anticipation of Claim 5 by Lau
`Petitioner contends that claim 5 is anticipated by Lau. Pet. 66–77. To
`support its contentions, Petitioner provides explanations as to how the prior
`art discloses each claim limitation. Id. Petitioner also relies upon the
`Elenius Declaration to support its positions. Patent Owner counters that Lau
`does not anticipate claim 5 because it fails to disclose the Sum Limitation.
`Prelim. Resp. 63–69.
`On this record, we are persuaded by Petitioner’s explanation and
`evidence in support of the Lau anticipation ground for claim 5. We begin
`our discus
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