demonstrated to consist of write patterns that contain three or more
`unspaced consecutive transitions. A class of block codes that limits
`the number of consecutive symbol transitions~ typically representing
`binary "1 's'\ are known as maximum transition run (MTR) codes. To
`avoid three or more consecutive transitions, codes with MTR values
`(no more than two successive binary "l's" in the coding result) equal
`to two are desirable.
`
`(Id. at 2:14-27.) Both embodiments of Tsang involve a MTR value of 2, and
`
`thereby "limits the number of consecutive symbol trans.itions" pnd eliminates the
`
`''most likely error sequence" in recorded data. (See id) Tsang therefore discloses
`
`facilitation of '~e reduction of a probability of a detection error' in the receiver
`
`means, as recited in claim l [D].
`
`141. Tsang also claims "an encoder coupled to said encoding receiver for
`
`providing a corresponding said code block for each said data block," such that
`
`"each said code block and any concatenations of said code blocks are without more
`
`than a preselected first symbol number of successive repetitions ofa first symbol
`
`throughout, and without more than a preselected second symbol number of
`
`successive repetitions of a second symbol throughout." (Ex. 1009 at 19:41-57)
`
`( claim 1 ). Claim 2 recites the apparatus of claim 1 wherein "said first symbol is a
`
`'0' and said second is a '1."' (Id., 19:58-60.) Claim 3 recites the apparatus of
`
`claim 1 wherein "said first symbol number equals nine/' i.e., k = 9. (Id .• 19:61-
`
`Page 230 of 358
`
`- 57-
`
`LSI Corp. Exhibit 1010
`Page61
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`unspaced consecutive transitions. A class of block codes that limits
`the number of consecutive symbol transitions~ typically representing
`binary "1 's'\ are known as maximum transition run (MTR) codes. To
`avoid three or more consecutive transitions, codes with MTR values
`(no more than two successive binary "l's" in the coding result) equal
`to two are desirable.
`
`(Id. at 2:14-27.) Both embodiments of Tsang involve a MTR value of 2, and
`
`thereby "limits the number of consecutive symbol trans.itions" pnd eliminates the
`
`''most likely error sequence" in recorded data. (See id) Tsang therefore discloses
`
`facilitation of '~e reduction of a probability of a detection error' in the receiver
`
`means, as recited in claim l [D].
`
`141. Tsang also claims "an encoder coupled to said encoding receiver for
`
`providing a corresponding said code block for each said data block," such that
`
`"each said code block and any concatenations of said code blocks are without more
`
`than a preselected first symbol number of successive repetitions ofa first symbol
`
`throughout, and without more than a preselected second symbol number of
`
`successive repetitions of a second symbol throughout." (Ex. 1009 at 19:41-57)
`
`( claim 1 ). Claim 2 recites the apparatus of claim 1 wherein "said first symbol is a
`
`'0' and said second is a '1."' (Id., 19:58-60.) Claim 3 recites the apparatus of
`
`claim 1 wherein "said first symbol number equals nine/' i.e., k = 9. (Id .• 19:61-
`
`Page 230 of 358
`
`- 57-
`
`LSI Corp. Exhibit 1010
`Page61
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`62.) Claim 4 recites the apparatus of claim 1 wherein "said second symbol number
`
`equals two," i.e.,j = 2. (Id., 19:63-64.)
`
`142. Thus, Tsang discloses claim limitation 1 [DJ
`
`S.
`
`Claim l[E]: "said sequences generating no more than j
`consecutive transitions in the recorded waveform such that
`j is an integer equal to or greater than 2; and"
`
`143. As discussed above with respect to claim I [DJ, Tsang discloses
`
`apparatuses having an MTR ("j") value of 2. As also discussed above with respect
`
`to claim 1 [DJ, Claim 4 of Tsang specifically claimsj = 2. A value ofj=2 ensures
`
`that the recorded wavefonn "avoid[s] three or more consecutive transitions." (Ex.
`
`1009 at 2:25-28. Tsang thus discloses claim element I [E].
`
`6.
`
`Claim l[F]: "said sequences generating no more than k
`consecutive sample periods without a transition in the
`recorded waveform."
`
`144. As discussed above with respect to claim element 1 [D], Tsang
`
`discloses apparatuses having a constraint k of 9, which ensures generation ofno
`
`more than 9 consecutive sample periods without a transition in the recorded
`
`waveform. (See Ex. 1009 at 2:3-S; 5:25-39) And as also discussed above with
`
`.respect to claim element I [D], claim 3 of Tsang specifically claims k = 9. Tsang
`
`thus discloses claim element I [F].
`
`Page 231 of 358
`
`- S8-
`
`LSI Corp. Exhibit 1010
`Page62
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`B.
`
`Claim 2 is anticipated by Tsang
`
`145. Claim 2 recites "Apparatus as in claim l wherein thej consecutive
`
`transition limit is defined by the relationship 2 S j < 10."
`
`146. As shown above, Tsang anticipates claim 1 from which claim 2
`
`depends. As to the additional limitation of claim 2. Tsang discloses and claims
`
`apparatuses and methods whereinj = 2. (Seethe discussion of claims 1 [D] and 1
`
`[E], supra.) Tsang thus anticipates claim 2.
`
`C. Claim 8 is anticipated by Tsang
`
`147. Claim 8 recites "Apparatus as in claim 2 wherein th.e consecutive
`
`transition limit is defined by the relationship j=2. ''
`
`148. As shown above, Tsang anticipates claims land 2 from which claim
`
`8 depends. As to. the additional limitation of claim 8, Tsang discloses and claims
`
`apparatuses and methods wherein j 2. (See the discussion of claims l [D] and l
`
`[E], supra.) Tsang thus anticipates claim 8.
`
`D. Claim 9 is anticipated by Tsang
`
`149. Claim 9 recites "Apparatus as in claim 2 wherein the binary sequences
`
`produced by combining codewords have no more than j consecutive I's and no
`
`more thank consecutive O's when used with a NRZI recording format."
`
`ISO. As shown above, Tsang anticipates claim I from which claims 2 and
`
`9 depend. As to the additional limitation of claim 9, Tsang discloses and claims
`
`Page 232 of 358
`
`-59-
`
`LSI Corp. Exhibit 1010
`Page63
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`that, afterNRZI modulation, (see Ex. 1009 at 1:5-41; 2:22-25), wherej=2, "invalid
`
`patterns (three or more consecutive l's) do not occur when these code words are
`
`concatentated.'t (E.g., Bx. 1009 at 4:3-13.) Further "the "O's' run length 'k'
`
`constraint"= 9, and therefore no more than 9 consecutive zeros are found. (Bx.
`
`1009 at 5:25-39.) (See the discussion of claims 1 (D], 1 [E], and 1 [F], supra.)
`
`1 S 1. Tsang thus anticipates claim 9.
`
`E. Claim 10 is anticipated by Tsang
`
`152. Claim 10 recites "Apparatus as in claim 2 wherein binary sequences
`
`produced by combining codewords have no more than one of j consecutive
`
`transitions from 0 to l and from l to 0 and no more than k+ 1 consecutive O's and
`
`k+l consecutive l's when used in coajunction with a NRZ recording format."
`
`153. As shown above, Tsang anticipates claims land 2 from which claim
`
`l 0 depends. In particular, Tsang discloses and claims that the binary sequences
`
`produced by combining codewords, after NRZI modulation, have no more than 2
`consecutive l's and no more than 9 consecutive O's, i.e., j = 2 and k = 9. (See the
`
`discussion of claims l [DJ, l [E], and l [F], supra.)
`
`154. As to the additional limitations of claim lO, Okada dis.closes no more
`
`than one of 2 consecutive transitions from 0 to l and from 1 to 0 in NRZ format
`
`In particular, Figure 3 shows the code word assignment and next state table for a
`5/6 rate MTR code havingj 2 and k = 9 constraints. (Ex. 1009 at 3:4446). The
`
`Page 233 of 358
`
`-60-
`
`LSI Corp. Exhibit 1010
`Page64
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`32 rows of codewords in Figure 3 are shown in NRZI format. (Ex. 1009 at 1 :5-26,
`
`4:3-18.) As can be observed, each such codeword has at most two consecutive 1 's
`
`in a row. A sequence "11" in NRZI results from NRZ strings of"0101" or''l010,"
`
`i.e., one of2 consecutive transitions from Oto 1 and from 1 to O in NRZ format, as
`
`claimed. Figure 3 shows two columns of codewords for each data word,
`
`corresponding to "State O" and "State l." Tsang uses a "two-state trellis diagram"
`which ensures that the MTR j = 2 constraint is satisfied across codeword
`
`boundaries. (Ex. 1009 at 4:3-18; Ex.) (Figure 8 is similar to Figure 3, but
`
`corresponds to a second embodiment having a 6/7 rate MTR code havingj = 2 and
`
`k = 9 constraints.) As stated in the '601 Patent, k consecutive O's in NRZlformat
`
`is equivalent to no more thank+ 1 consecutive O's and k + 1 consecutive 1 's, in
`
`NRZformat. (Ex. 1001 at 1:15-36.)
`
`lSS. Tsang thus anticipates claim 10.
`
`F. Claim 13 is anticipated by Tsang
`
`1.
`
`Claim 13(A]: "A method for encoding m-bit binary
`datawords into n-bit binary codewords in a recorded
`waveform, where m and n are preselected positive integers
`such that n is greater than m, comprising tbe steps of:"
`
`156. Claim 13 is highly similar to claim 1, but claim 13 recites a "method"
`
`while claim l recites an ''apparatus.''
`
`157. As informed by counsel, the preamble of the claim may not be
`
`limiting. Alternatively, if the preamble is found to be limiting, as shown above,
`
`-61 -
`
`Page 234 of 358
`
`LSI Corp. Exhibit 1010
`Page65
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`Tsang discloses and claims apparatuses and methods for encoding m-bit binary
`
`datawords into n-bit binary codewords, in a recorded waveform, wherein m is
`
`greater than n. (Seethe discussion of claim 1 [A], supra.)
`
`158. Tsang thus discloses and claim element 13 [A].
`
`2.
`
`Claim 13[B]: "receiving binary datawords; and"
`
`159. As explained above with respect to claim element 1 [BJ, Tsang
`
`discloses a first embodiment, depicted in Figure 4A, wherein datawords ( 11) are
`
`received by a "data word receiver" consisting of a 5-bit register ( l 0), and a second
`
`embodiment, depicted in Figure 9A, wherein datawords (61) are received by a 6-
`
`bit register (60). Tsang thus discloses and claims claim 13 [B].
`
`3.
`
`Claim 13[C): "producing sequences or n-bit codewords;"
`
`160. As explained above with respect to claim element 1 [CJ, Tsang
`
`discloses a first embodiment wherein an encoder (15) is coupled to a receiver
`
`means (10) for producing sequences of6-bit codewords. (Ex. 1009, Figure 4A;
`
`6:5-28.) In a second embodiment, Tsang discloses an encoder (65) coupled to a
`
`receiver means (60) for producing sequences of 7-bit codewords. (Id., Figure 9A;
`
`11:43-56.) Thus, Tsang discloses claim element 13 [C].
`
`Page 235 of 358
`
`-62-
`
`LSI Corp. Exhibit 1010
`Page66
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`4.
`
`Claim 13(D): "imposing a pair of constraints (j;k) on the
`encoded waveform;,,
`
`161. As explained above with respect to claim elements 1 [DJ. [E], and [F],
`
`Tsang discloses and claims MTR constraints j = 2 and k 9. Thus, Tsang
`
`discloses claim element 13 [D].
`
`5.
`
`Claim 13(E]: "generating no more than j consecutive
`transitions of said sequence in the recorded waveform .such
`that j ~ 2; and,,
`
`162. As explained above with respect to claim elements 1 [E], Tsang
`
`discloses and claims MtR constraints j = 2, resulting in generation of not more
`
`than 2 consecutive transitions. Thus, Tsang discloses claim element 13 [E].
`
`6.
`
`Claim 13(F): "generating no more thank consecutive
`sample periods of said sequences without a transition in the
`recorded waveform."
`
`163. As discussed above with respect to claim element 1 [F], Tsang
`
`discloses and claims MTR constraint k = 9, ensuring no more than 9 consecutive
`
`sample periods without a transition in the recorded waveform. ThU$, Tsang
`
`discloses and claims claim 13 [F].
`
`G. Claim 14 is anticipated by Tsang
`
`164. Claim 14 recites "The method as in claim 13 wherein the consecutive
`
`transition limit is defined by the relationship 2 S j < 10."
`
`165. As explained previously, Tsang anticipates claim 13 from which claim
`
`14 depends. As to the additional limitations ofclaim 14, as explained above with
`
`-63-
`
`Page 236 of 358
`
`LSI Corp. Exhibit 1010
`Page67
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`respect to claim 2, Tsang discloses and claims apparatuses and methods wherein j
`
`= 2. Tsang thus anticipates claim 14.
`
`H. Claim 15 is anticipated by Tsang
`
`166. Claim 15 recites "The method as in claim 14 wherein the consecutive
`
`transition limit is j=2.''
`
`167. As discussed previously, Tsang anticipates claims 13 and 14 from
`
`which claim 15 depends. As to the additional limitation of claim 15, as shown
`
`above with respect to apparatus claim 2, Tsang discloses and claims apparatuses
`
`and methods whereinj = 2. Tsang thus anticipates claim 15.
`
`I.
`
`Claim 16 is anticipated by Tsang
`
`168. Claim 16 recites the "method as in claim 14 wherein the binary
`
`sequences produced by combining codewords have no more than j consecutive I's
`
`and no more thank consecutive O's when used with the NRZI recording format''
`
`169. As explained previously, Tsang anticipates claim 14 from which claim
`
`16 depends. As to the additional limitations of claim 16, Tsang discloses and
`
`claims that the binary sequences produced by combining the disclosed 6- and %bit
`
`codewords, after NRZI modulation, have no more than 2 consecutive 1 's and no
`
`more than 9 consecutive O's, i.e., j 2, k 9 . (See the discussion of claims 1 [D],
`
`1 [E], and 1 [F], supra.) Tsang thus anticipates claim 16.
`
`Page 237 of 358
`
`-64-
`
`LSI Corp. Exhibit 1010
`Page68
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`J.
`
`Claim 17 is anticipated by Tsang
`
`170. Claim 17 recites "The method as in claim 14 wherein the binary
`
`sequences produced by combining codewords have no more than one of j
`
`consecutive transitions from Oto 1 and from 1 to O and no more than one of k+ 1
`
`consecutive O's and k+ 1 c.onsecutive 1 's when used in conjunction with the NRZ
`
`recording format."
`
`171. As discussed previously, Tsang anticipates claims 14 from which
`
`claim 17 depends. In addition, for the reasons discussed previously with respect to
`
`claim 10, Tsang discloses that the binary sequences produced by combining
`
`codewords have no more than one of j consecutive transitions from O to 1 and from
`
`1 to O and no more than one ofk+l consecutive O's and k+ 1 consecutive l's when
`
`used in conjunction with the NRZ recording format.
`
`172. Tsang thus anticipates. claim 17.
`
`IX. CLAIMS 12 AND 21 ARE OBVIOUS OVER OKADA IN VIEW OF
`SHIMODA
`
`A. Claim 12 is obvious over Okada in view of Shimoda
`
`173. Claim 12 recites "Apparatus as in claim 2 wherein the receiver means
`
`incorporates means for removing certain code-violating patterns from the detection
`
`process wherein the detection process comprises at least one of the steps of:
`
`removing states and state transitions corresponding to more than j consecutive
`
`transitions from a Viterbi trellis ... " [Emphasis added.]
`
`-65 -
`
`Page 238 of 358
`
`LSI Corp. Exhibit 1010
`Page69
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`174. As shown above, Okada teaches all of the limitations recited in claims
`
`l and~ from which claim 12 depends. (See the discussion of Okada with respect
`
`to anticipation of claims l and 2, supra.) Okada teaches a 8-to-13 block encoder,
`
`but does not dis.close "means for removing certain code-violating patterns from the
`
`detection process'' wherein the detection process comprises "removing states and
`
`state transitions corresponding to more than j consecutive transitions from a Viterbi
`
`trellis."
`
`175. Shimoda discloses an apparatus and method for encoding binary data
`
`into codewords using an RLL code (as opposed to MTR code). The apparatus and
`
`method comprises an encoder (101), a recording/reproducing system (102), a
`
`Viterbi equalizer (103), and a decoder (104), as depicted in Figures 7 and 8:
`
`11
`'<
`0
`ii
`
`H
`
`I!
`
`I
`
`IOI
`
`102
`
`103
`
`[04
`
`RIOORD :uro/
`RIPRODUO'l'IRO
`S'lCftR
`
`Vl':'J!BRBI
`BQUALIZIR
`
`DIICODIR
`
`UOODBR
`
`I
`
`m.L 00011
`
`H
`
`n
`Ji
`
`i. -~
`
`0
`
`C
`
`Page 239 of 358
`
`-66-
`
`LSI Corp. Exhibit 1010
`Page 70
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`Rl!ICOROIJIO
`t>A'l'A
`
`IOI
`
`UCODIR
`
`=
`iE
`gglll
`@ii=
`21=
`••m
`
`103
`
`114
`
`113
`
`104
`
`'flftRSI
`IQUALIZBR
`
`DBCODD
`
`RIIPROOUC'l'I01'
`DA'tA
`
`OLOllK llftRAOflR
`
`116
`
`(Ex. 1008t Figs. 7 and 8, respectively.)
`
`176. ·The encoder ( l 0 1) e.ncodes recording data into run length limited
`
`("RLL'') code data. (Ex. 1008, 4:13-27.) The recording/reproducing system (102)
`
`records the RLL code data on a recording medium, such as a magnetic disk, and
`
`reproduces the RLL code data from the recording medium. The Viterbi equalizer
`
`(I 03) equalizes the RLL code data read out from the recording medium. The
`
`decoder (I 04) decodes equalized RLL code data output by the Viterbi equalizer
`
`103, and generates reproduction data. (See id.)
`
`177. The Viterbi equalizer eliminates the intersymbol interference which
`
`takes place in the recording/reproducing system (102). (Ex. 1008, 4:28-40). "A
`
`viterbi decoding algorithm designed for use with an RLL code does not particular
`
`have state transitions inherent in the RLL code." (Id.) "In other words, there are
`
`state transitions which do not take place due to the rule of the RLL code." Thus, "a
`
`maximum likelihood path determination circuit provided in the viterbi equalizer ...
`
`-67-
`
`Page 240 of 358
`
`LSI Corp. Exhibit 1010
`Page 71
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`does not have any structural elements related to the state transitions which do not
`
`take place due to the rule of the RLL code." (/d.)
`
`178. In one embodiment, Shimoda discloses an RLL (1, 7) code generated
`
`in accordance with the following rules:
`
`BASIC TRANSFORM
`CODEWORD
`101
`100
`001
`010
`
`DATA
`00
`01
`10
`11
`
`EXCBPI'ION
`CODB WOW BASED ON
`BASIC 'I'RANSPORM
`101101
`101100
`001101
`001100
`
`OORR.BCTBD
`CODEWORD
`101000
`100000
`001000
`010000
`
`DATA
`0000
`0001
`1000
`1001
`
`(Ex. 1008, 4:65-5:31). Shimoda discloses "the trellis state transition diagram of
`
`the Viterbi equalizer (114)" in Figure 9, (id.), which is reproduced below:
`
`Page 241 of 358
`
`-68-
`
`LSI Corp. Exhibit 1010
`Page72
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`RLL{/1 7), 3 TAPS
`
`(Ex. 1008, Fig. 9.) u1n FIG. 9, it is assumed that the directions of the write current
`
`(recording data) are defined as +1 and -1. In this case, a time series of the write
`
`current encoded into the ( 1, 7) code does not have two transitions ( + 1, -1, +I) and (-
`
`1, +I, -1)." (Id., S:23-30). "Thus, state transitions indicated by broken lines
`
`shown ill FIG. 9 do not take place in the viterbl equalizer 114 which uses the
`
`RLL (1,7) code." (Id.) (emphasis added). As discussed above in Section Ill(E),
`
`the term t'means for removing certain code-vioJating patterns'' reads on a Viterbi
`
`trellis corresponding to a detection system, or its equivalents. Shimoda, in Figure
`
`9, discloses this structure.
`
`l 79~ In another embodiment,, Shimoda discloses an RLL (2, 7) code
`
`generated in accordance with the following rules:
`
`-69-
`
`Page 242 of 358
`
`LSI Corp. Exhibit 1010
`Page 73
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`DATA
`10
`11
`000
`010
`011
`0010
`0011
`
`CODBWOBD
`0100
`1000
`000100
`100100
`001000
`00100100
`00001000
`
`(Ex. I 008 at 6:52-7:8.) In this embodiment, a time series of the write data "does
`
`not have state transitions of (+I, -1, +l), (-1, +l, -1), (+1, -1, -1, +1) and (-1, +l,
`
`+1, -1)." (Id., 7:1-8). "Thus, there tlre not state transitions indicated by broken
`
`Unes shown in FIG. 12, and it is not necessary for the viterbi equali1.er 114 to
`
`have circuits related to such state transitions which do not take place at all." (Id.)
`
`(emphasis added). Figure 12 is reproduced below:
`
`Page 243 of 358
`
`-70-
`
`LSI Corp. Exhibit 1010
`Page 74
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`----...
`,
`\
`. ... _____ ,, \\
`{-J+J-1 ...
`\\ ,,
`
`RLL(2,7J, 4 TAPS
`
`(Ex. 1008, Fig. 12.) Shimoda, in Figure 12, therefore discloses an additional
`
`Viterbi trellis corresponding to a detection system, which corresponds to the claim
`
`term ~'means for removing certain code-violating patterns."
`
`Page 244 of 358
`
`-71-
`
`LSI Corp. Exhibit 1010
`Page 75
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`180. Shimoda therefore discloses apparatuses and methods "wherein the
`
`receiver means incorporates means for removing certain code-violating patterns
`
`from the detection process wherein the detection process comprises» a step of
`
`"removing states and state transitions corresponding to" transitions that violate
`
`RLL (d,k) codes "from a Viterbi trellis."
`
`181. It would have been obvious for a person having ordinary skill in the
`
`art at the time of the alleged invention to combine the teachings of Okada and
`
`Shimoda to arrive at the alleged invention recited in claim 12. Both references
`
`address issues with data storage and associated apparatus and methods to reduce
`
`errors. (Ex. 1007 at abstract; Ex. 1008 at abstract.) A person ofordinary skill
`
`naturally would have been motivated to include with the 8-to-13 bit block encoder
`
`of Okada a Viterbi trellis corresponding to a "maximum likelihood path» detection
`
`system, as taught by Shimoda, because Okada is sub-optimal and it was well(cid:173)
`
`known that the purpose of "maximum likelihood path detection" systems is to
`
`lower the bit error rate in an optimal manner. A maximum likelihood path
`
`detection system computes the most probable input resulting in an observed output.
`
`One of ordinary skill would have thus been motivated to further minimize the bit
`
`error rate by optimizing the apparatus described in Okada using the Viterbi trellis
`
`of Shimoda. Further, adapting the recording apparatus of Okada in this way in
`
`view of Shimoda was well within the ability of one of ordinary skill in the art at the
`
`Page 245 of 358
`
`LSI Corp. Exhibit 1010
`Page 76
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`time. Indeed, removing states and state transitions corresponding to code violating
`
`patterns from a Viterbi trellis is a routine function, well-known and easily
`
`employed by graduate students in the field. Moreover, doing so would have
`
`produced the predictable (and desirable) result of a lower bit error rate.
`
`182. Further, a person of ordinary skill would have been motivated to
`
`include in the detection process a step of removing states and state transitions
`
`corresponding to more than j consecutive transitions from the Viterbi trellis, as
`
`taught by Shimoda, because then the device does not need to "have any structural
`
`elements related to the state transitions which do not take place due to the rule" of
`
`the MTR code, (Ex. 1008 at 4:28-40), making the device more "compact" and
`
`"less expensive." (Id. at 2:64-65.)
`
`183. Claim 12 is therefore obvious over Okada in view ofShimoda.
`
`B. Claim 21 is obvious over Okada in view of Shimoda.
`
`184. Claim 21 recites ''The method as in claim 13 wherein the method of
`
`receiving data incorporates the removal of certain code-violating patterns from the
`
`detection process wherein the detection process comprises at least one of the steps
`
`of; removing states and state transitions corresponding to more than j consecutive
`
`transitions from a Viterbi treilis ... '~ [Emphasis added.]
`
`185. As shown above in the Section discussing Okada's anticipation of
`
`certain claims, Okada teaches all of the limitations recited in claim 13 from which
`
`- 73 -
`
`Page 246 of 358
`
`LSI Corp. Exhibit 1010
`Page 77
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`claim 21 depends. Further, ''methodH claim 21 is similar to "apparatus" claim 12.
`
`As shown above, claim 12 is obvious over Okada in view ofShimoda. Claim 21 is
`
`obvious for the same reasons.
`
`186. Again, Okada teaches a 8-to-13 block encoder, but does not disclose
`
`"the removal of certain code-violating patterns from the detection process"
`
`wherein the detection process comprises "removing states and state transitions
`
`corresponding to more than j consecutive transitions from a Viterbi trellis." As
`
`shown above with respect to claim 12, Shimoda teaches a Viterbi trellis
`
`corresponding to a maximum likelihood path detection system, wherein RLL code
`
`violating states and states transitions are removed from the detection process. For
`
`the same reasons discussed with respect to claim 12, it would have been obvious
`
`for a person having ordinary skill in the art at .the time of the alleged invention to
`
`combine the teachings of Okada and Shimada to arrive at the alleged invention
`
`recited in claim 21.
`
`187. Claim 21 is therefore obvious over Okada in view of Shimoda, for the
`
`same reasons that claim 12 is obvious over Okada in view of Shimoda
`
`X. CLAIMS 12 AND 21 ARE OBVIOUS OVER TSANG IN VIEW OF
`SHIMODA
`
`A. Claim 12 is obvious over Tsang in view ofShimoda
`
`188. Claim 12 recites "Apparatus as in claim 2 wherein the receiver means
`
`incorporates means for removing certain code-violating patterns from the detection
`
`-74-
`
`Page 24 7 of 358
`
`LSI Corp. Exhibit 1010
`Page 78
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`process wherein the detection process comprises at least one o/the steps of:
`
`removing states and state transitions corresponding to more than j consecutive
`
`transitions from a Viterbi trellis ... " [Emphasis added.]
`
`189. As shown above, Tsang teaches all of the limitations recited in claims
`
`1 and 2, from which claim 12 depends. (See the discussion ofTsang's anticipation
`
`of claims 1 and 2, supra.) In particular, Tsang discloses and claims rate 5/6 and
`
`rate 6/7 encoders, each having MTR constraints of j = 2 and k = 9. Tsang teaches
`
`the use of a "trellis diagram in such a manner that invalid patterns (three or more
`
`consecutive 1 's) do not occur when •.. code words are concatenated." (Ex. 1009 at
`
`4:3-19; see id. at 10:17-11:57.)
`
`190. To the extent it is found, however, that Tsang does not disclose
`
`nmeans for removing certain code-violating patterns from the detection process
`
`wherein the detection process c.omprises at least one of the steps of: removing
`
`states and state transitions corresponding to more than j consecutive transitions
`
`from a Viterbi tre~lis," Shimoda supplies such teachings. As discussed previously,
`
`Shimoda teaches a Viterbi trellis corresponding to a maximum likelihood path
`
`detection system, wherein RLL code violating states and states transitions are
`
`removed from the detection process. (See supra.).
`
`191. It would have been obvious for a person having ordinary skill in the
`
`art at the time of the alleged invention to combine the teachings of Tsang and
`
`-75-
`
`Page 248 of 358
`
`LSI Corp. Exhibit 1010
`Page79
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`Sbimoda to arrive at the alleged invention recited in claim 12. Tsang expressly
`
`discloses the use of a "trellis diagram'' to eliminate "invalid patterns." In
`
`particular, a person of ordinary skill would have naturally looked to different trellis
`
`options in the art, including the Viterbi trellis corresponding to a "maximum
`
`likelihood pat.bu detection system taught by Shimoda to accomplish this
`
`elimination of "invalid patterns," especially because it was well-known that the
`
`purpose of optimal "maximum likelihood path detection" systems such as
`
`disclosed in Shimada is to lower the bit error rate. A maximum likelihood path
`
`detection system computes the most probable input resulting in an observed output.
`
`One of ordinary skill would have thus been motivated the Viterbi trellis of
`
`Shimoda as the ''trellis diagram"' that eliminates ''invalid patterns" in Tsang.
`
`Further, using the Viterbi trellis from Shimoda for the "trellis diagram" from Tsang
`
`was well within the ability ofone of ordinary skill in the art at the time of the
`
`invention oft.he '601 patent. Indeed, removing code violating states and state
`
`transitions from a Viterbi trellis was a routine function at that time, well-known
`
`and easily employed by even graduate students. Moreover, doing so would have
`
`produced the predictable (and desirable) result of a lower bit error rate.
`
`192. Further, a person of ordinary skill would have been motivated to
`
`include in the detection process a step of removing states and state transitions
`
`corresponding to more thanj consecutive transitions from the Viterbi trellis, as
`
`-76-
`
`Page 249 of 358
`
`LSI Corp. Exhibit 1010
`Page SO
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`taught by Shimoda, because then the device does not need to •'have any structural
`
`elements related to the state transitions which do not take place due to the rule" of
`
`the MTR code, (Ex. 1008 at 4:28-40), making the device more "compact'' and
`
`"less expensive." (Id. at 2:64-65.)
`
`193. Claim 12 is therefore obvious over Tsang in view ofShimoda.
`
`B. Claim 21 is obvious over Tsang in view of Shimoda.
`
`194. Claim 21 recites "The method as in claim 13 wherein the method of
`
`receiving data incorporates the removal of certain code-violating patterns from the
`
`detection process wherein the detection process comprises at least one of the steps
`
`of: removing states and state transitions corresponding to more than j consecutive
`
`transitions from a Viterbi trellis •.. " [Emphasis added.]
`
`195. As shown above, Tsang teaches all of the limitations recited in claim
`
`13 from which claim 21 depends. Further, "method" claim 21 is similar to
`
`"apparatus" claim 12. As shown above, apparatus claim 12 is obvious over Tsang
`
`in view ofShimoda. Method claim 21 is obvious over Tsang in view ofShimoda,
`
`for the same reasons that claim 12 is obvious.
`
`196. Again, if Tsang does not disclose "means for removing certain code(cid:173)
`
`violating patterns from the detection process wherein the detection process
`
`comprises at least one of the steps of: removing states and state transitions
`
`corresp.onding to more thanj consecutive transitions from a Viterbi trellis,"
`
`-77-
`
`Page 250 of 358
`
`LSI Corp. Exhibit 1010
`Page 81
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`Shimoda supplies such teachings. As discussed previously, Shimoda teaches a
`
`Viterbi trellis corresponding to a maximum likelihood path detection system,
`
`wherein RLL code violating states and states transitions are removed from the
`
`detection process.
`
`197. It would have been obvious for a person having ordinary skill in the
`
`art at the time of the alleged invention to combine the teachings of Tsang and
`
`Shimoda to arrive at the alleged invention recited in claim 21.
`
`198. Claim 21 is therefore obvious over Tsang in view of Shimoda, for the
`
`same reasons that claim 12 is obvious over Tsang in view of Shimoda
`
`Xl. SECONDARY CONSIDERATIONS OF NON-OBVIOUSNESS
`
`199. As discussed above, I understand the objective factors indicating
`
`obviousness or non-obviousness may include: commercial success of products
`
`covered by the patent claims; a long-felt need for the invention; failed attempts by
`
`others to make the invention; copying of the invention by others in the field;
`
`unexpected results achieved by the invention; praise of the invention by the
`
`infringer or others in the field; the taking of licenses under the patent by others;
`
`expressions of surprise by experts and those skilled in the art at the making of the
`
`invention; and the inventors proceeded contrary to the accepted wisdom of the
`
`prior art.
`
`Page 251 of 358
`
`-78-
`
`LSI Corp. Exhibit 1010
`Page 82
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`200. I have considered these factors in my above obviousness analyses and
`
`am not aware of any evidence at this stage indicating that at any of these factors
`
`would weigh against a fmding of obviousness.
`
`XII. CONCLUSION
`
`20 l. For the reasons given above, it is my opinion that the Challenged
`
`Claims of the '601 patent are not patentable, and should be cancelled.
`
`69182908\1.1
`
`- 79-
`
`Page 252 of 358
`
`LSI Corp. Exhibit 1010
`Page 83
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`APPENDIX A
`
`Page 253 of 358
`
`LSI Corp. Exhibit 1010
`Page84
`
`UMN EXHIBIT 2008
`LSI Corp. et al. v. Regents of Univ. of Minn.
`IPR2017-01068
`
`
`
`CASE 0:16-cv-02891-WMW;.SER Document 40-3 Filed 11/11/16 Page 1 of 3
`
`Maximum Transition Run Codes for Data Storage Systems
`JailkyJl11 M<>on and Bam=n: Bm:knm-
`Ccmer for Micromagnctics and lnformalion Technologies
`Depan;mel1t o f~ Bilglnecrmg, Umvemty of Minnesota
`:Minneapolis, Minnesota S$4S5
`
`1U1tract - A uw code Is presented which
`Im•
`proves the mlDimWD dlttance
`properties •f lie•
`quenee detectors
`oper•tb11 •t hlch linear densities.
`This code, whith is citlled the maximum transition
`run code, eliminates data patterns producing three
`or more consecutive trar.tsitions whne
`Imposing
`the uSltlli k-eaustralut necessary for tlmin1 reco••
`vy. The colle p0$$eNes the similar distance-gain•
`Ing property of the .(l.,k) code, but cau be impJe(cid:173)
`mented with considerably hither rates. Bh error
`rate simulations on fifld delay tne search with de(cid:173)
`dsion feedback and high order partial ruponst
`ma:dmvm likelihood detectors confirm tarae coding
`gala over the conventional (D,t) code.
`
`l INmODt.TCllON
`IN this pspm-, we p -1 a new coa dfli.gnod to Improve the
`distance propcmes of sequence detecton opot'IIUllJli al rdllllvely
`h!gb Unur densities. The basic: idea is to eliminate c:crtllll'I !op.It
`bit patterns that wcutd CIIIISC. most errors in s~ e dolc!Ctors,
`More specl&:ally, the code el.lmil11ite$ illpt
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
