`
`
`
`1111111111111111111111111I1111114111fili1111111111111111111111111
`
`(12) United States Patent
`Fu et al.
`
`(to) Patent No.:
`(45) Date of Patent:
`
`US 6,278,748 B1
`Aug. 21, 2001
`
`(54)
`
`RATE 5/6 MAXIMUM TRANSITION RUN
`CODE FOR READ CHANNELS
`
`(75)
`
`Inventors: Leo Fu, Sunnyvale; An-Loong Kok,
`Irvine, both of CA (US)
`
`(73) Assignee: Texas Instruments Incorporated,
`Dallas, TX (US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/070,438
`
`(22) Filed:
`
`Apr. 30, 1998
`
`(51) Int. C1.7
`
`(52) U.S. Cl.
`
`HO3D 1/00; HO4L 27/06;
`HO4L 5/12; HO4L 23/02; HO3M 7/00
`375/341; 375/263; 375/262;
`341/59; 341/61
` 375/263, 341,
`(58) Field of Search
`375/340, 290, 262, 265; 360/39, 40, 48;
`714/759, 746, 794, 795, 792; 341/59, 50,
`61, 58, 68, 94, 106
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,731,768 * 3/1998 Tsang
`5,754,593 * 5/1998 Koren
`5,949,357 * 9/1999 Fitzpatrick et al.
`
` 341/59
` 375/263
` 341/68
`
`* cited by examiner
`
`Primary Examiner—Stephen Chin
`Assistant Examiner—Betsy L. Deppe
`(74) Attorney, Agent, or Firm—W. Daniel Swayze, Jr.;
`Wade James Brady, III; Frederick J. Telecky, Jr.
`
`(57)
`
`ABSTRACT
`
`A method and apparatus encoding and decoding data for
`storage on a mass storage device is described. The code used
`is a 5/6 rate code in which a maximum transition run
`constraint is imposed. This code is designed for use with an
`EEPR4 read channel and provides a Euclidian squared free
`distance, d2free, of 10 when used with an EEPR4 partial
`response filter and a Viterbi decoder.
`
`3 Claims, 5 Drawing Sheets
`
`r
`
`READ CHANNEL DECODER
`
`41
`
`42
`
`V32
`
`v -30
`
`AGC
`
`31
`
`FIR
`LOW PASS
`FILTER
`FILTER
`EEPR4 FILTER
`
`
`J
`
`33
`
`34
`
`35
`
`A/D
`CONVERTER
`
`EEPR4
`DETECTOR
`
`#Vi
`
`SERIAL TO
`PARALLEL
`
`120 6
`
`36
`/
`5/6 MTR
`DECODER
`
`/)1(1
`
`5t>
`
`10
`
`L
`
`I -
`
`BUFFER
`
`<
`
`N-24
`
`WRITE ENCODER
`
`PARALLEL
`TO SERIAL
`
`22
`
`WRITE
`PRECOMP
`
`23
`
`1Y 1 6
`
`5/6 MTR
`ENCODER
`
`lXkl 5
`
`21
`
`11-`-20
`
`INTERFACE <
`
`I/O BUS
`
`1 1
`
`LSI Corp. Exhibit 1025
`Page 1
`
`

`

`Waled *S11
`
`toot `1z tnv
`
`S Jo 1 13311S
`
`iff 8171NLV9 Sa
`
`11
`
`I/O BUS
`
`INTERFACE
`
`10
`
`FIG. 1
`
`20
`
`21
`
`22
`
`ENCODER
`5/6 MTR
`
`1Y 1
`
`TO SERIAL
`PARALLEL
`
`1wii
`WRITE ENCODER
`
`23
`
`PRECOMP
`
`WRITE
`
`N-24
`
`BUFFER
`
`L
`
`DECODER
`5/6 MTR
`
`36
`
`" t 6,
`
`PARALLEL
`SERIAL TO
`
`35
`
`DETECTOR
`
`EEPR4
`
`CONVERTER
`
`A/D
`
`34
`
`33
`
`v-30
`
`J
`
`EEPR4 FILTER
`
`31
`
`I
`__J__
`
`FILTER
`
`FIR
`
`LOW PASS
`
`FILTER
`
`/-32
`
`11,
`
`42
`
`41
`
`READ CHANNEL DECODER
`
`-F-AGC
`
`r
`
`r
`
`LSI Corp. Exhibit 1025
`Page 2
`
`

`

`Waled *S11
`
`toot `1z tnv
`
`S Jo Z 13311S
`
`iff 8171NLV9 Sa
`
`FIG. 6
`
`COMPUTER
`
`HOST
`
`?
`60
`
`J
`
`Vi
`
`+
`
`v-200
`
`J
`
`1-`- 50
`
`70
`
`SCSI
`
`-1
`
`2
`
`CONTROLLER
`
`DRIVE
`
`INTERFACE
`
`WRITE CHANNEL
`
`CIRCUITRY
`
`
`
`WRITE HEAD
`
`56
`
` READ CHANNEL k.
`
`CIRCUITRY
`
`
`
`READ HEAD
`
`57
`
`?
`51
`
`10
`
`30
`
`r
`
`DELAY
`UNIT
`
`201d
`
`DELAY
`UNIT
`
`201c
`
`i-2
`
`DELAY
`UNIT
`
`201 b
`
`I—
`
`DELAY
`UNIT
`\
`201a
`
`
`
`L
`
`Wi
`....
`
`r
`
`FIG. 2
`
`SPIN k_
`-,52
`
`53
`
`MOTOR PLL
`
`DSP
`
`MOTOR
`SPIN
`
`54 -v-
`
`I
`
`ACTUATOR
`
`55 _."--
`
`20
`?
`
`
`
`DRIVE UNIT
`HARD DISK
`
`LSI Corp. Exhibit 1025
`Page 3
`
`

`

`U.S. Patent
`
`Aug. 21, 2001
`
`Sheet 3 of 5
`
`US 6,278,748 B1
`
`0000
`
`0001
`
`0010
`
`0011
`
`0100
`
`0101
`
`0110
`
`0111
`
`1000
`
`1001
`
`1010
`
`2
`
`6
`
`2
`
`6
`
`—4
`—2
`
`2
`—4
`—2
`
`4
`—2
`
`2
`
`—2
`
`2
`
`1011
`
`—6
`—4
`—2
`0
`—6
`—4
`—2
`
`1100
`
`1101
`
`1110
`
`1111
`
`FIG. 3
`
`0000
`
`0001
`
`0010
`
`0011
`
`0100
`
`0101
`
`0110
`
`0111
`
`1000
`
`1001
`
`1010
`
`1011
`
`1100
`
`1101
`
`1110
`
`1111
`
`LSI Corp. Exhibit 1025
`Page 4
`
`

`

`U.S. Patent
`
`Aug. 21, 2001
`
`Sheet 4 of 5
`
`US 6,278,748 B1
`
`Ak+1 = x 4 k+1 ' x5 k+1 + x l k+1 • x 2 k+1 • x3k+1 +
`
`P6 = 9 1k-1 • P5
`
`Q2 =
`
`(g1k
`
`+
`
`g2 k )
`
`Q3 = g 3k • Q2
`
`Q4 = g4 k • Q3
`
`F = P3 • Q4 + P4 • Q3 +
`
`P5.02 + P6 - glk
`
`= gl k_i
`
`Y1k-1
`
`y2 k_1
`
`=
`
`92k-1
`
`Y 3 k -
`
`1
`
`=
`
`g 3
`
`k -
`
`1
`
`Y 4 k -
`
`1
`
`=
`
`g 4 1(-
`
`1
`
`Y 5 k -
`
`1
`
`=
`
`95 k -
`
`=
`
`Y6k-1
`
`96k-1
`
`1 + F
`
`+ F
`
`x 2 k+1 ' x 3k+1 ' x 4 k+1
`
`Bk+1 = x i k+1 • x 2 k+1 • x 3k+1 • x 4 k+1
`
`Z4 = (x1k + x2 k 4. x 3k + x 4k )
`
`Z5 = Z4 • x 5k
`
`
`
`C = A k Bk-
`
`D = Z5 • A k+ i
`
`E = Z4 • D• u k
`
`glk = C + Bk + E
`
`2
`9k -_
`
`AT .0 + B,K + E
`k
`k
`
`9 3k- - Tk • x 2 k + C • xl k
`
`,( • x 3k + C • P k • x3k + J k • x 2k (x3k
`g4k = i!!
`x4k) + ki k . x2k . k 4 k J + TE t (s k + s k . x5k)
`
`ED
`
`5
`9 k
`
`-
`-
`
`ft7
`k •
`
`x 4 k + C • x 2 k (x4 k EE) x 5 k )+ B k •Sk + D
`
`Sk+1 = A . x 5k + C -
`
`k + Bk •
`
`1( - x 5 k
`
`96k = B k+1 • Sk+1 + D
`
`uk+i = g6k
`
`P3 = (9 4 k-1 + 9 5 k-1 + 9 6 k-1)
`
`P4 = 93k-1 ' P3
`
`P5 = 9 2k-1 ' P4
`
`FIG. 4
`
`LSI Corp. Exhibit 1025
`Page 5
`
`

`

`U.S. Patent
`
`Aug. 21, 2001
`
`Sheet 5 of 5
`
`US 6,278,748 B1
`
`2 •^3 •^4
`1
`•
`0 'Y k•Y ICY ICY k
`
`h1 = a • 1.73- • u 6
`
`b = y ^5 k • y 6 k
`
`h2 = u2 • u3 • u6
`
`h3 = u2 • u3 •
`
`h4 = 1.71 • u2
`
`k = u4 ED u5 ED u6
`
`21 k_i = t.71 • u2 + ul • (h2 + h3 + h4)
`
`22k_1 = u1 • u3 + u1 • (h1 + h3 + h4)
`23k_1 = t.7.1 • u4 + u1 • (0 • u4 • u6 +
`u2 • u4 • u6 + u2)
`
`x4 k_1 = 1.71 • u5 + ul • (h0 + hl + h2 +
`h3 • u4 • +h4)
`
`ii5k_ 1 = t.71 • u6 + u1 • (h0 + h1 • liZ + h2 + h3 •
`
`(u4 • +u5)+(h4 • k))
`
`c = beY5 k
`
`d = bED 96 k
`
`e = a • E
`
`f = eG319 1 k
`
`g
`
`=
`
`VED1
`
`/ 2
`
`k
`
`P = f • g
`
`z1k = f
`= g
`
`, k
`2L
`
`z 3 k
`
`= 3
`Y k
`
`74 L k
`
`_
`
`k
`Y k
`
`, k
`5L
`
`=c
`
`,6k = A
`L
`u
`
`u1
`
`u2
`
`u3
`
`= zlk-,
`= z2k-,
`= z3k-,
`= z 4 k-1
`= z5k-i
`u6 = c • p + z 6k_i • 5
`
`u4
`
`u5
`
`h0 = u2 • u3 • u6
`
`FIG. 5
`
`LSI Corp. Exhibit 1025
`Page 6
`
`

`

`US 6,278,748 B1
`
`1
`RATE 5/6 MAXIMUM TRANSITION RUN
`CODE FOR READ CHANNELS
`
`FIELD OF THE INVENTION
`
`The present invention relates generally to the field of
`coding data; particularly, the present invention relates to
`encoding of data for use with a partial response maximum-
`likelihood read channel.
`
`BACKGROUND OF THE INVENTION
`
`This invention relates to coding techniques for use with
`magnetic storage media. Designs for magnetic storage
`media systems must simultaneously maximize the density of
`information stored on the media and ensure that the storage
`system has adequate error tolerance. These two goals are
`always in tension. The features of a read channel that
`maximize the permissible storage density on the storage
`media also tend to reduce the error tolerance of the storage
`device and read channel.
`Storage density can be maximized with the use of a partial
`response maximum likelihood (PRML) read channel. A
`PRML read channel always includes a partial response filter
`and a maximum likelihood decoder. The partial response
`filter provides an output signal that represents a mathemati-
`cal combination of the stored bits from a moving window of
`adjacent bits in the sequence of stored bits on the magnetic
`media. The output of the filter is then fed to a decoder that
`determines the sequence of bits most likely to have produced
`the filter output. Use of a partial response filter in the read
`channel permits higher density storage of data on the mag-
`netic media. See H. Kobayashi, D. T. Tang, "Application of
`Partial-responsc Channel Coding to Magnetic Recording
`Systems", IBM Journal of Research & Development, July
`1970, pp. 368-375.
`The decoder in a PRML read channel uses a maximum-
`likelihood sequence detection algorithm such as the Viterbi
`algorithm. The decoder converts the output of the partial
`response filter into a sequence of binary values representing
`the sequence of bits stored onto the magnetic media. Meth-
`ods for decoding PRML read channels using trellis decoders
`are shown, for example, in Jack W. Wolf & Gottfried
`Ungerboeck, "Trellis Coding for Partial Response
`Channels," IEEE Transactions on Communications, vol.
`COM-34, Aug. 1986, pp. 765-773, and G. David Forney,
`"The Viterbi Algorithm," Proceedings of the IEEE, March
`1973, pp. 268-278, which are herein incorporated by refer-
`ence.
`Write and read channels for magnetic storage devices
`often employ encoding of the sequence of bits that is to be
`stored on the magnetic device. Encoding of the symbols to
`be recorded onto the magnetic storage media can be used to
`increase the noise tolerance of the entire system. The most
`common measure of noise signal tolerance of a trellis
`decoder is the minimum free squared Euclidean distance of
`the set of permissible paths through the trellis, d 2free. The
`minimum free squared Euclidean distance measures the
`minimum difference in the path distance of any two paths in
`the trellis that start and end at the same node. One method
`of increasing the minimum free squared Euclidean distance
`of a read channel is to encode the sequence of symbols that
`are to be recorded onto the magnetic storage media. Encod-
`ing limits the set of permissible trellis paths and can be used
`to disallow alternative trellis paths that produce the worst
`case minimum free squared Euclidean distance measure. By
`disallowing these paths, the minimum free squared Euclid-
`ean distance of the remaining paths is improved.
`
`10
`
`2
`Encoding, however, comes at a cost in that it expands the
`number of bits required to store a fixed amount of user
`source data on the disk. The rate of a code indicates the
`relationship between the number of bits of user data encoded
`5 and the number of bits of encoded data stored on the storage
`media. In a rate 5/6 code, five bits of user data are encoded
`into six bits of encoded data that are stored. It is always
`possible to increase the minimum free squared Euclidean
`distance of any encoding scheme by increasing the coding
`overhead and decreasing the rate of the code. Increasing the
`rate of the code used necessitates a decrease in the storage
`density that may be used.
`One type of code that can be used for encoding is the class
`of Maximum Transition Run (MTR) codes. MTR codes
`have the property that the number of consecutive `1' sym-
`is bols is limited to some maximum transition run length. In
`the non return to zero inverse (NRZI) convention often used
`in analysis of magnetic storage systems, a `1' symbol
`indicates the existence of a transition in the magnetic state
`stored, and a `0' symbol indicates that the current state is
`20 maintained. The MTR code used in the subject invention
`limits the maximum sequence of consecutive `1' symbols to
`two. Limiting the number of consecutive `1' symbols to two
`is equivalent to limiting the number of consecutive state
`transitions to two or less. Patterns of three or more consecu-
`25 tive transitions cause most of the errors in read channel
`detection systems, so using codes that eliminate these pat-
`terns produces significant error reduction dividends. See
`Jaekyun Moon & Barrett Brickner, "Maximum Transition
`Run Codes for Data Storage Systems," IEEE Transactions
`30 oil Magnetics, vol. 32, September 1996, pp. 3992-3994.
`The central problem, therefore, for any designer of encod-
`ing and decoding channels for a storage device is to develop
`a coding procedure which maximizes the density of user
`data that may be stored on the magnetic media. This involves
`a trade-off between the coding rate used and the density of
`storage that may be achieved using any particular code. The
`designer's goal is to develop a code which maximizes the
`coding rate and provides a minimum free squared Euclidean
`distance that ensures the error detection margin required to
`support a particular storage density.
`SUMMARY OF THE INVENTION
`The present invention describes an apparatus and a
`method for encoding and decoding data. The inventive
`encoding system can be used with a storage medium that
`45 employs a partial response filter with the transfer function
`h(D)=(1—D)(1+D)3, where D represents the delay operator.
`This is known as an extended-extended partial response
`channel of Class 4 (EEPR4).
`The subject encoding system and read channel employ a
`50 rate 5/6 code. The code is an MTR code with the property
`that codewords are selected so that runs of consecutive `1'
`symbols are limited to two or less `1' symbols, and runs of
`consecutive `0' symbols are limited to runs of six or less of
`such `0' symbols. For this reason the code can be identified
`55 as a rate 5/6 MTR(2,6) code.
`The code employed in the inventive encoding system and
`read channel has a minimum free squared Euclidean dis-
`tance of 10, when used with an EEPR4 read channel. This
`value is large enough to provide an adequate margin of error
`60 for use in a magnetic disk drive system. Use of this code
`makes it possible to use an EEPR4 filter in the read channel,
`which would not be possible if a coding scheme with a lesser
`minimum free squared Euclidean distance was used.
`An advantage of the present invention is that it provides
`65 a high density, rate 5/6 code that affords a minimum free
`squared Euclidean distance of 10 when used in an EEPR4
`system.
`
`35
`
`40
`
`LSI Corp. Exhibit 1025
`Page 7
`
`

`

`US 6,278,748 B1
`
`3
`Another advantage of the present invention is that it
`permits the use of an EEPR4 read channel, which makes
`possible higher read densities than would be afforded with
`lower-order partial response filters.
`The foregoing, and other features and advantages of the
`invention, will be apparent from the following, more
`particular, description of the preferred embodiments of the
`invention, the accompanying drawings and the appended
`claims.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram illustrating the overall archi-
`tecture of a write encoder and read channel decoder that can
`be used to implement the present invention.
`FIG. 2 is an idealized EEPR4 partial response filter in
`accordance with the present invention.
`FIG. 3 is a decoding trellis for use by a Viterbi detector in
`detecting an EEPR4 filtered signal in accordance with the
`present invention.
`FIG. 4 is a sequence of boolean equations that can be used
`to implement the encoding algorithm performed by the rate
`5/6 MTR encoder of the present invention.
`FIG. 5 is a sequence of boolean equations that can be used
`to implement the decoding algorithm performed by the rate
`5/6 MTR decoder of the present invention.
`FIG. 6 is a block diagram illustrating the overall archi-
`tecture of a disk drive storage device built utilizing the write
`encoder and read channel decoder of the present invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`
`The preferred embodiment of the present invention and its
`advantages are best understood by reference to FIGS. 1
`through 6, where like reference numbers indicate like ele-
`ments.
`FIG. 1 illustrates a functional block diagram of the write
`encoder 20 and read channel decoder 30 for a hard disk drive
`system. The bidirectional interface 10 interconnects the
`write encoding circuitry and read channel circuit with a
`drive controller (not shown) through I/O bus 11. Data to be
`written to the hard disk drive is conveyed over bidirectional
`interface 10 to write encoder 20 where it is encoded. The
`output of write encoder 20 from the output buffer 24 is a
`differential analog signal which can be used with external
`magnetic read/write circuitry to write the data to the hard
`disk media. When data is read from the hard disk, the
`differential analog signal read from the disk is received by
`automatic gain control clement 31 in read channel decoder
`30. Read channel decoder 30 filters and decodes the signal
`to recover the data stored on the disk. The decoding per-
`formed by read channel decoder 30 reverses the encoding
`performed by write encoder 20 when the data was written to
`the disk. The decoded data is then transferred across I/O bus
`11 to the drive controller.
`The detailed operation of write encoder 20 will now be
`described. The external drive controller passes data that is to
`be written to write encoder 20 over I/O bus 11. A rate 5/6
`MTR encoder 21 is coupled to the bidirectional interface. 60
`Data that is to be written to the disk drive is received at
`bidirectional interface 10 in an unencoded fonn, and is
`passed through bidirectional interface 10 to rate 5/6 MTR
`encoder 21. Rate 5/6 MTR encoder 21 converts this raw data
`into an encoded format, in accordance with the code 65
`described in detail below. This code encodes five bits of raw
`data received from the drive controller into six bits of
`
`4
`encoded data that will be stored on the disk drive. While this
`has the effect of expanding the number of bits that must be
`stored on the disk drive, the use of the code permits denser
`storage of the drive media, more than offsetting the 20%
`5 overhead that results from the use of the 5/6 code. The
`output from the encoder can be thought of as a sequence of
`six-bit codewords {yk}(={yo, y1, . . . y, . . . 1), where each
`y, represents a separate six-bit codeword.
`Rate 5/6 MTR encoder 21 receives a sequence of symbols
`10 from interface circuitry 10. Each received symbol is five-bits
`wide. Encoder 21 converts each five-bit symbol received
`into an encoded output symbol that is made up of six-bits.
`In the discussion that follows, and in accordance with
`standard practice, data words are identified as a sequence of
`15 `0' and `1' characters, with the most significant bit (MSB) on
`the left and the least significant bit (LSB) on the right. The
`"first" bit in the codeword is synonymous with the MSB and
`the "last" bit in the codeword is synonymous with the LSB.
`In practice, it is purely a matter of definition as to whether
`20 the LSB or MSB is transmitted first when a word is
`transmitted serially, and the disclosed system can be imple-
`mented either way.
`Source and codewords are processed sequentially in time
`by write encoder 20. This processing is pipelined so that
`25 processing of multiple codewords is proceeding simulta-
`neously at different points in write encoder 20. When code
`or source words are described as the "current" or "preced-
`ing" or "previous" words, this indicates the nature of the
`sequential relationship between the two words. The "cur-
`30 rent" word follows directly after the "previous" or "preced-
`ing" word in the sequence of code or source words that is
`processed by the encoder/read channel.
`The encoding algorithm used by rate 5/6 MTR encoder 21
`35 has four steps. These steps must be performed in the order
`indicated. The operations performed in some of these steps
`are determined not only by the contents of the current source
`word but also by the encoded output codeword produced
`when the previous source word was encoded.
`Step 1:
`The first step of the conversion can be done as a table
`lookup. The five bits of the received symbol are used as an
`index into one of two translation tables. Each translation
`table includes 32 entries, so that each received sequence
`45 corresponds to a specific index in the table. Each entry in the
`table is occupied by a six-bit translation that will serve to
`represent the five-bit received symbol. The encoder deter-
`mines which table to use based upon whether the previous
`encoded codeword had a `0' or a `1' in its last bit position.
`50 If the previous codeword had a `0' in its last bit position,
`then the "State-0" table should be used, otherwise the
`"State-1" table is used.
`
`40
`
`55
`
`TABLE 1
`
`"STATE-0" Conversion Table
`
`Input
`
`00000
`00001
`00010
`00011
`00100
`00101
`00110
`00111
`01000
`01001
`
`Output
`
`000000
`000001
`000010
`000001
`000100
`000101
`000110
`100101
`001000
`001001
`
`LSI Corp. Exhibit 1025
`Page 8
`
`

`

`US 6,278,748 B1
`
`5
`
`TABLE 1-continued
`
`"STATE-0" Conversion Table
`
`Input
`
`01010
`01011
`01100
`01101
`01110
`01111
`10000
`10001
`10010
`10011
`10100
`10101
`10110
`10111
`11000
`11001
`11010
`11011
`11100
`11101
`11110
`11111
`
`Output
`
`001010
`100100
`001100
`001101
`100010
`100000
`010000
`010001
`010010
`101001
`010100
`010101
`010110
`101101
`011000
`011001
`011010
`101100
`101000
`101010
`110100
`110101
`
`TABLE 2
`
`"STATE-1" Conversion Table
`
`Input
`
`00000
`00001
`00010
`00011
`00100
`00101
`00110
`00111
`01000
`01001
`01010
`01011
`01100
`01101
`01110
`01111
`10000
`10001
`10010
`10011
`10100
`10101
`10110
`10111
`11000
`11001
`11010
`11011
`11100
`11101
`11110
`11111
`
`Output
`
`000000
`000001
`000010
`000001
`000100
`000101
`000110
`100101
`001000
`001001
`001010
`100100
`001100
`001101
`100010
`100000
`010000
`010001
`010010
`101001
`010100
`010101
`010110
`101101
`011000
`011001
`011010
`101100
`101000
`101010
`110010
`110110
`
`It will be observed that the "State-0" and "State-1"
`conversion tables differ only in the last two entries.
`When the "States-1" table is used, the encoder must under
`undertake one additional step that does not apply when the
`"State-0" table is used. If the received source word sequence
`to be translated using the "State-1" table is either `11110' or
``11111', the last bit of the previous codeword output of the
`encoder to use a different encoder must be inverted. The fact
`that the last bit has been inverted should not cause the
`
`5
`
`10
`
`6
`encoder to use a different encoding table with the current
`source word. For example, if the previous encoded code-
`word is `110101', the encoder will use the "State-1" table
`with the current source word. If the current source word is
``11111', the encoder must invert the last bit of the previous
`encoded codeword, making it `110100'. This does not,
`however, mean that the encoder should now use the "State-
`0" table to encode the current source word. Instead it will
`continue to use the "State-1" table, encoding `11111' as
``110110'.
`Step 2:
`If the translated six-bit output produced from Step 1 is
``000000' and the first bit of the following codeword is `0',
`then the last two bits of the current codeword must be
`15 changed to logical `1's so that the current codeword
`becomes `000011'. If this condition does not apply, the
`codeword passes through step two unchanged.
`Step 3:
`If the previous codeword has a `0' as its last bit, and the
`20 current six-bit output produced from step two has five zeroes
`in its first five bits, then the first two bits of the current
`codeword are modified to become logical ones. If this
`condition does not apply, the codeword passes through step
`three unchanged.
`Step 4:
`If the previous codeword ends with a sequence of zeroes
`and the current codeword starts with a sequence of zeroes,
`and the combined length of these sequences is seven bits or
`greater, then the last two bits of the previous codeword are
`modified to become logical ones. If this condition does not
`apply, the codeword passes through step four unchanged.
`The encoding steps performed by rate 5/6 MTR encoder
`21 can be performed by a sequence of boolean logic opera-
`35 tions. The boolean equations shown in FIG. 4 implement the
`function of rate 5/6 MTR encoder 21. In these equations the
`five-bit symbol xk represents the symbol that is provided as
`an input to rate 5/6 MTR encoder 21. The binary variables
`X1,X2k,X3k,X5k, represent the five bits of symbol xk, with
`40 X1k representing the first bit in the symbol and X5k the last.
`The corresponding six-bit codeword produced as an output
`from rate 5/6 MTR encoder 21 is identified by the symbol yk.
`The six bits that make up yk, are identified as y1k, y2, y3,
`y4k, y5k, y6k. The input to rate 5/6 MTR encoder 21 is made
`up of a continuous sequence of five-bit symbols, xi, x2,
`,
`xk-1, xk, Xk+1, • • • • The output from rate 5/6 MTR encoder
`21 is likewise made up of a continuous sequence of six-bit
`codewords, y1, v 2 ,
`, yk-1 , yk, Yk+1, • • • • The equations
`•
`•
`•
`in FIG. 4 employ a number of intermediate variables,
`including a sequence of six-bit codewords g1, g2, • . . , gk_1,
`gk, g„,i, In the equations in FIG. 4, boolean logical OR
`operations are indicated as additions or with the `+' symbol,
`and logical AND operations are indicated as multiplication
`of two binary symbols or with the
`symbol.
`Turning again to FIG. 1, a parallel to serial converter 22
`is coupled to the six-bit wide parallel output of rate 5/6 MTR
`encoder 21. Parallel to serial converter 22 serializes the
`six-bit wide output of rate 5/6 MTR encoder 21, which
`allows the encoded data to be written to the disk drive in a
`60 serial format. The serial output of parallel to serial converter
`22, which can be represented as serial binary sequence fw,I,
`is coupled to a write precompensation circuit (23).
`The purpose of the precompensation circuit is to incre-
`mentally delay or advance the time at which signal pulses
`65 appear in the stream of data values to be written to the
`magnetic media. The precompensation circuit must deter-
`mine which pulses need to be shifted. It does this by sorting
`
`25
`
`30
`
`45
`
`50
`
`55
`
`LSI Corp. Exhibit 1025
`Page 9
`
`

`

`US 6,278,748 B1
`
`7
`them into groups based upon the presence of adjacent pulses.
`The user of write encoder 20 determines how much each
`group of pulses should be shifted. The shifting parameters
`are fixed based upon the characteristics of a particular
`magentic storage drive and can be adjusted separately for
`each drive device manufactured.
`The output of precompensation circuit 23 is connected to
`output buffer 24 which is used to drive an encoded output
`signal that can be used with a standard hard disk drive write
`circuit or other storage media circuitry to store the encoded
`data onto magnetic media.
`A detailed description of the operation of read channel
`decoder 30 will now be given.
`Read channel decoder 30 receives data from an external
`disk drive read circuit (not shown). The disk drive read
`circuit produces a differential analog signal which is pro-
`vided as an input to automatic gain control (AGC) circuit 31.
`The AGC circuit is a standard feature of disk drive circuitry
`that amplifies the differential signal received from the exter-
`nal read/write circuitry. The gain on this amplifier is adjusted
`to maintain constant signal amplitude at the input to an
`EEPR4 filter 32.
`EEPR4 filter 32 is an analog circuit. The input signal
`provided to EEPR4 Filter 32 by AGC 31 and the output
`signal from filter 32 are continuous-time analog waveforms.
`The analog input signal to EEPR4 filter 32 represents a
`sequence {*j of binary values read from the storage media.
`Similarly, the output from filter 32 represents a sequence
`{v,} of discrete multilevel output values.
`EEPR4 filter 32 is best described in terms of with refer-
`ence to a discrete time model 200 of an EEPR4 filter.
`Discrete time model 200 operates on a sequence of discrete
`inputs, each of which is a binary sample of two possible
`values. From this input sequence, the discrete time model
`produces a sequence of discrete multi-level output values. In
`contrast, EEPR4 filter 32 is an analog circuit that operates on
`a continuous input signal and produces therefrom a continu-
`ous output signal. As noted above, however, the analog input
`and output signals to and from EEPR4 filter 32 represent
`discrete time sequences of binary or multi-level values. The
`relationship between the binary input sequences and the
`multi-level output sequences conveyed by these analog
`inputs and outputs is identical to the relationship between
`the discrete time input and output sequences of discrete time
`model 200.
`In FIG. 2, discrete time model 200 is illustrated. The
`schematic shown in FIG. 2 is a discrete time model of an
`extended extended partial response class 4 filter. It is not a
`schematic representation of the analog circuitry found in
`EEPR4 filter 32. Model EEPR4 filter 200 is a finite response
`filter. The filter receives a sequence of binary input values
`INFsrj selected from the set of {+1, -1} and produces an
`output sequence {V,} of multilevel symbols selected from
`the set {+6, +4, +2, 0, -2, -4, -6}. The model filter employs
`four unit delay blocks 201a-d that store previous elements
`of the input sequence so that five consecutive sequence
`members 1*,_4, *,_,, w,_2,
`*,1 are available to the
`filter simultaneously. The sequence members are scaled and
`added in accordance with the EEPR4 filter equation h(D)=
`(1-D)(1+D)3, where D represents the unit delay operator.
`Equivalently, the encoder output sequence, 1v,1, is related to
`the binary input sequence, 1w,1, by: v,=w,+2w,_,-2w,_3-
`w,-4.
`Turning again to FIG. 1, the manner in which filter
`circuitry 32 implements model EEPR4 filter 200 will now be
`described.
`
`8
`Filter circuitry 32 comprises a low-pass filter 41/and a
`finite impulse response (FIR) filter 42. Low-pass filter 41 is
`coupled to the output of AGC circuit 31. Low-pass filter 41
`is a continuous time filter, the output of which is coupled to
`5 FIR filter 42. In the preferred embodiment of the invention,
`low-pass filter 41 has programmable cutoff, boost and group
`delay settings. Low-pass filter 41 performs two functions.
`First, it filters out noise signals that have frequencies outside
`the bandwidth of the signal read from the magnetic storage
`10 device. Second, low-pass filter 41 shapes the pulse stream
`read from the magnetic storage device. The result of this
`shaping, when combined with the effect of FIR filter 42, is
`to produce a partial response filtering effect, so that the
`output of low-pass filter 41 and FIR filter 42 represents the
`15 pulse sequence originally stored on the disk filtered through
`a class 4 partial response filter. The programmable settings
`for the cutoff, boost and group delay characteristics of
`low-pass filter 41 must be set in accordance with the
`particular properties of the magnetic storage media and the
`20 disk drive read circuitry of storage device used with read
`channel decoder 30.
`FIR filter 42 is used for fine shaping of the sampled read
`signal to make it perform the function of model EEPR4 filter
`200. The output of EEPR4 filter 32 is an analog continuous
`25 time waveform, which is fed as an input to analog to digital
`(ND) converter 33. A/D converter 33 takes the analog
`output of EEPR4 filter 32 and converts it a sequence of
`discrete multilevel output samples {vj. The multilevel
`output from the filter circuitry, 1v,1, is coupled to the input
`30 of an EEPR4 detector (34). EEPR4 detector 34 is a maxi-
`mum likelihood Viterbi detector. Each element in the
`sequence can take on one of the set of values {+6, +4, +2,
`0, -2, -4, -6}. These values cannot be decoded directly into
`corresponding stored bit values. Rather, each symbol in the
`35 1v,1 sequence corresponds to a one-bit transition through the
`state trellis for EEPR4 detector 34. The detector algorithm
`tracks all possible paths that might be used to traverse the
`state trellis and selects the path which best fits the sequence
`of transition symbols received by the decoder. Once the
`40 "best fit" path has been determined, the stored bit values that
`produced the "best fit" state transition path are identified and
`EEPR4 detector 34 provides, at its output, a sequence {V,}
`of stored bit values.
`The Viterbi detection algorithm used in EEPR4 detector
`45 34 employs the state transition trellis given in FIG. 3. The
`nodes on the left and right hand sides of the trellis indicate
`the starting and ending states, respectively, of EEPR4 detec-
`tor 34.
`The trellis indicates which transitions are possible as
`so EEPR4 detector 34 advances one bit at a time through a
`sequence of bits to be decoded. Every permissible transition
`is represented as a line in the trellis, and the values indicated
`near each permissible transition represent the expected out-
`put from the EEPR4 encoder during that transition. These
`55 expected transition values may be combined with the multi-
`level transition symbol actually received (vi) to create
`branch metrics for the Viterbi decoder. Using the branch
`metrics the most likely path can be determined.
`EEPR4 detector 34 produces an output sequence {V,} of
`60 serial bits. In order to decode this sequence of bits they must
`be reassembled into six-bit wide codewords. This reassem-
`bly is done by serial to parallel circuitry 35. To assemble the
`serial sequence of data into six-bit codewords, serial to
`parallel circuitry 35 must have an indication of which bits in
`65 the serial sequence {V,} represent the first or last bit of a
`six-bit codeword. This information is provided to serial to
`parallel 35 by synchronization circuitry (not shown). The
`
`LSI Corp. Exhibit 1025
`Page 10
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`

`

`US 6,278,748 B1
`
`9
`synchronization circuitry recovers the boundaries of the
`six-bit codewords by monitoring patterns in the data
`received.
`Serial to parallel circuitry 35 produces an output sequence
`of six-bit words {yk} which represents the best estimate of
`the serial sequence {yk} that was written to the disk. The rate
`5/6 MTR code used in the in